JPS57173959A - Connecting method of electrode or wiring layer to semiconductor or conductor layer in semiconductor device - Google Patents

Connecting method of electrode or wiring layer to semiconductor or conductor layer in semiconductor device

Info

Publication number
JPS57173959A
JPS57173959A JP6006681A JP6006681A JPS57173959A JP S57173959 A JPS57173959 A JP S57173959A JP 6006681 A JP6006681 A JP 6006681A JP 6006681 A JP6006681 A JP 6006681A JP S57173959 A JPS57173959 A JP S57173959A
Authority
JP
Japan
Prior art keywords
semiconductor
windows
electrode
regions
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6006681A
Other languages
Japanese (ja)
Inventor
Yoshiharu Ozaki
Kazuo Hirata
Kazuhide Kiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6006681A priority Critical patent/JPS57173959A/en
Publication of JPS57173959A publication Critical patent/JPS57173959A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a larger contact surface by a method wherein the surface of a semiconductor layer within a window whereto an electrode is connected is provided with a ruggedly formed surface. CONSTITUTION:In a semiconductor substrate 1 with regions 3 and 4 formed inside and insulator layers 5 and 8 formed outside, the insulator layer 8 is provided with a mask 12 for boring windows and the insulators 5 and 8 are subjected to gas plasma etching in a mixture exemplifiedly of CF4 and H2. The etching is so effected that resultant windows 13 and 14 contain columns 15 and 16 surviving the process. The columns 15 and 16 act as masks in another process of etching the semiconductor regions 3 and 4 in the windows 13 and 14 to obtain rugged surfaces 18 and 19 in the regions 3 and 4. Electrodes 20 and 21 are respectively built in the windows 13 and 14 after removed of the mask layer 12 and the columns 15 and 16, which realizes very large contact surfaces between the regions 3, 4 and the electrode 20, 21.
JP6006681A 1981-04-21 1981-04-21 Connecting method of electrode or wiring layer to semiconductor or conductor layer in semiconductor device Pending JPS57173959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6006681A JPS57173959A (en) 1981-04-21 1981-04-21 Connecting method of electrode or wiring layer to semiconductor or conductor layer in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6006681A JPS57173959A (en) 1981-04-21 1981-04-21 Connecting method of electrode or wiring layer to semiconductor or conductor layer in semiconductor device

Publications (1)

Publication Number Publication Date
JPS57173959A true JPS57173959A (en) 1982-10-26

Family

ID=13131334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6006681A Pending JPS57173959A (en) 1981-04-21 1981-04-21 Connecting method of electrode or wiring layer to semiconductor or conductor layer in semiconductor device

Country Status (1)

Country Link
JP (1) JPS57173959A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209143A (en) * 1982-05-31 1983-12-06 Seiko Epson Corp Structure of multilayer wiring
JPS58209144A (en) * 1982-05-31 1983-12-06 Seiko Epson Corp Structure of multilayer wiring
JPH04314352A (en) * 1991-04-12 1992-11-05 Oki Electric Ind Co Ltd Fabrication of semiconductor device
JP2006287084A (en) * 2005-04-04 2006-10-19 Rohm Co Ltd Thin-film transistor element and manufacturing method thereof
US9625536B2 (en) 2013-10-17 2017-04-18 Mitsubishi Electric Corporation Magnetic sensor and method for manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209143A (en) * 1982-05-31 1983-12-06 Seiko Epson Corp Structure of multilayer wiring
JPS58209144A (en) * 1982-05-31 1983-12-06 Seiko Epson Corp Structure of multilayer wiring
JPH04314352A (en) * 1991-04-12 1992-11-05 Oki Electric Ind Co Ltd Fabrication of semiconductor device
JP2006287084A (en) * 2005-04-04 2006-10-19 Rohm Co Ltd Thin-film transistor element and manufacturing method thereof
US9625536B2 (en) 2013-10-17 2017-04-18 Mitsubishi Electric Corporation Magnetic sensor and method for manufacturing the same

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