JPS56125874A - Mis type semiconductor device and its manufacture - Google Patents

Mis type semiconductor device and its manufacture

Info

Publication number
JPS56125874A
JPS56125874A JP2834480A JP2834480A JPS56125874A JP S56125874 A JPS56125874 A JP S56125874A JP 2834480 A JP2834480 A JP 2834480A JP 2834480 A JP2834480 A JP 2834480A JP S56125874 A JPS56125874 A JP S56125874A
Authority
JP
Japan
Prior art keywords
insulating substrate
layer
angle
insulating
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2834480A
Other languages
Japanese (ja)
Other versions
JPS6159677B2 (en
Inventor
Keizo Shiyudo
Kinya Kato
Hirohiko Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2834480A priority Critical patent/JPS56125874A/en
Publication of JPS56125874A publication Critical patent/JPS56125874A/en
Publication of JPS6159677B2 publication Critical patent/JPS6159677B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Drying Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve dielectric breakdown strength by forming the angle of a side surface of an insular semiconductor layer to an insulating substrate at a fixed angle or lower. CONSTITUTION:A semiconductor layer 2, an insulating layer 8, a conductive layer 9 and an insulating layer 10 are successively laminated and formed on an insulating substrate 1. The semiconductor layer 2 employs a mask layer as a mask, is made up by means of etching treatment by an ion milling method using ion beams and is built up so as to contact with the insulating substrate 1 in a shape that an angle theta of a side surface 3' of the semiconductor layer 2 to the insulating substrate 1 is an angle of 30 deg. or lower. Thus, the insulating layer 8 contacts with the insulating substrate 1 in relationship of which its angle to the insulating substrate 1 is also 30 deg. or lower.
JP2834480A 1980-03-06 1980-03-06 Mis type semiconductor device and its manufacture Granted JPS56125874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2834480A JPS56125874A (en) 1980-03-06 1980-03-06 Mis type semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2834480A JPS56125874A (en) 1980-03-06 1980-03-06 Mis type semiconductor device and its manufacture

Publications (2)

Publication Number Publication Date
JPS56125874A true JPS56125874A (en) 1981-10-02
JPS6159677B2 JPS6159677B2 (en) 1986-12-17

Family

ID=12245976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2834480A Granted JPS56125874A (en) 1980-03-06 1980-03-06 Mis type semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS56125874A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01222447A (en) * 1988-03-01 1989-09-05 Furukawa Electric Co Ltd:The Formation of etched mirror by ribe

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01222447A (en) * 1988-03-01 1989-09-05 Furukawa Electric Co Ltd:The Formation of etched mirror by ribe

Also Published As

Publication number Publication date
JPS6159677B2 (en) 1986-12-17

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