JPS6480076A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6480076A
JPS6480076A JP23682487A JP23682487A JPS6480076A JP S6480076 A JPS6480076 A JP S6480076A JP 23682487 A JP23682487 A JP 23682487A JP 23682487 A JP23682487 A JP 23682487A JP S6480076 A JPS6480076 A JP S6480076A
Authority
JP
Japan
Prior art keywords
film
deposited
drain regions
substrate
intermediate insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23682487A
Other languages
Japanese (ja)
Inventor
Hiroshi Tetsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP23682487A priority Critical patent/JPS6480076A/en
Publication of JPS6480076A publication Critical patent/JPS6480076A/en
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To avoid the breakdown of basic structure of element by a method wherein a sidewall film and an intermediate insulating film respectively made of materials different in the etching selectivity are adopted. CONSTITUTION:An intermediate insulating film 28 is deposited on overall surface of a substrate 21; contact holes 29 are made in the film 28 on a low concentration doped region 24; and high concentration ion is implanted in the substrate 21 to form source.drain regions 30. Next, when the holes 29 meet with the sidewall film 27 in gate electrode 25 side, the film 27 is hardly etched away by properly selecting the selective etching ratio of the film 27 to the film 25 since the applicable material of the film 27 is different from that of the film 28 in the etching selectivity. Finally, after reflowing the ion implanted layers for rounding the shape of contact parts partly for the heat-treatment to activate the ion implanted layers, the wiring layers 30 are deposited and patterned to be connected to the source.drain regions 30 through the contact holes 28.
JP23682487A 1987-09-21 1987-09-21 Manufacture of semiconductor device Pending JPS6480076A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23682487A JPS6480076A (en) 1987-09-21 1987-09-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23682487A JPS6480076A (en) 1987-09-21 1987-09-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6480076A true JPS6480076A (en) 1989-03-24

Family

ID=17006327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23682487A Pending JPS6480076A (en) 1987-09-21 1987-09-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6480076A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008514019A (en) * 2004-09-21 2008-05-01 フリースケール セミコンダクター インコーポレイテッド Semiconductor device and method of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008514019A (en) * 2004-09-21 2008-05-01 フリースケール セミコンダクター インコーポレイテッド Semiconductor device and method of forming the same

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