JPS6427269A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6427269A
JPS6427269A JP18315387A JP18315387A JPS6427269A JP S6427269 A JPS6427269 A JP S6427269A JP 18315387 A JP18315387 A JP 18315387A JP 18315387 A JP18315387 A JP 18315387A JP S6427269 A JPS6427269 A JP S6427269A
Authority
JP
Japan
Prior art keywords
alignment margin
film
taken
insulating film
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18315387A
Other languages
Japanese (ja)
Inventor
Hiroshi Onoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP18315387A priority Critical patent/JPS6427269A/en
Publication of JPS6427269A publication Critical patent/JPS6427269A/en
Pending legal-status Critical Current

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Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To inhibit the increase of contact resistance while also preventing defective connection by removing an alignment margin to a field insulating film and widening a contact hole while being approximately adjusted to correspond to the removed section are of the alignment margin. CONSTITUTION:An insulating film is applied onto the whole surface of a semiconductor substrate 21, and a sidewall film 27 is formed onto the sidewall of a gate electrode 25 through etching. High dosage injection is conducted into source and drain regions, high concentration source-drain regions 28 are shaped, an intermediate insulating film 29 is applied onto the semiconductor substrate 21, and contact holes 30 are bored through a normal photolithographic-etching process. When the contact holes 30 are bored, the alignment margin of size L is taken on the sidewall film 27 side, but an alignment margin is not taken on the field oxide film 22 side. Consequently, the alignment margin is not taken on the field oxide film 22 side, thus widening the areas of the contact holes 30. Accordingly, the increase of contact resistance is inhibited, and defective connection is also prevented.
JP18315387A 1987-07-22 1987-07-22 Manufacture of semiconductor device Pending JPS6427269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18315387A JPS6427269A (en) 1987-07-22 1987-07-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18315387A JPS6427269A (en) 1987-07-22 1987-07-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6427269A true JPS6427269A (en) 1989-01-30

Family

ID=16130723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18315387A Pending JPS6427269A (en) 1987-07-22 1987-07-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6427269A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0379079A (en) * 1989-08-22 1991-04-04 Fujitsu Ltd Manufacture of semiconductor device
US5474465A (en) * 1993-06-04 1995-12-12 Kobayashi Denki Kogyo Kabushiki Kaisha Waterproof connector
US5648286A (en) * 1996-09-03 1997-07-15 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
KR100280930B1 (en) * 1995-06-28 2001-02-01 다니구찌 이찌로오 Semiconductor devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0379079A (en) * 1989-08-22 1991-04-04 Fujitsu Ltd Manufacture of semiconductor device
US5474465A (en) * 1993-06-04 1995-12-12 Kobayashi Denki Kogyo Kabushiki Kaisha Waterproof connector
KR100280930B1 (en) * 1995-06-28 2001-02-01 다니구찌 이찌로오 Semiconductor devices
US5648286A (en) * 1996-09-03 1997-07-15 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region

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