JPS5775424A - Ion implantation - Google Patents

Ion implantation

Info

Publication number
JPS5775424A
JPS5775424A JP15180080A JP15180080A JPS5775424A JP S5775424 A JPS5775424 A JP S5775424A JP 15180080 A JP15180080 A JP 15180080A JP 15180080 A JP15180080 A JP 15180080A JP S5775424 A JPS5775424 A JP S5775424A
Authority
JP
Japan
Prior art keywords
wafer
pattern
ion implantation
electric charge
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15180080A
Other languages
Japanese (ja)
Inventor
Hisao Matsudera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15180080A priority Critical patent/JPS5775424A/en
Publication of JPS5775424A publication Critical patent/JPS5775424A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Magnetic Films (AREA)

Abstract

PURPOSE:To contrive to curtail ion implanting time by a method wherein a metal pattern is arranged on the margin of chips or at the neighborhood thereof of a wafer having the insulating surface, and ion implantation is performed. CONSTITUTION:Although dielectric breakdown originated from electric charge generated by ion implantation can be prevented by miniaturization of wafer size or by covering the surface of wafer with a conductor thin layer, but either of them results in rising of cost. Therefore a lattice type conductor pattern 2 is provided on the surface of the wafer 1, and electric charge stored in the wafer 1 is discharged to conductor nails coming in contact with the pattern 2 at the outside circumference thereof. When the pattern 2 is arranged along the marginal parts of the chips 1, no influence is applied to elements, and moreover when a mask is formed in the same mask with a metal mask pattern for transmission path, etc., cost can be reduced. By this constitution, even when ion implantation is performed with high speed, electric charge is not generated thereon, and the method thereof is extremely profitable for manufacture of magnetic bubble elements.
JP15180080A 1980-10-29 1980-10-29 Ion implantation Pending JPS5775424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15180080A JPS5775424A (en) 1980-10-29 1980-10-29 Ion implantation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15180080A JPS5775424A (en) 1980-10-29 1980-10-29 Ion implantation

Publications (1)

Publication Number Publication Date
JPS5775424A true JPS5775424A (en) 1982-05-12

Family

ID=15526569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15180080A Pending JPS5775424A (en) 1980-10-29 1980-10-29 Ion implantation

Country Status (1)

Country Link
JP (1) JPS5775424A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248223A (en) * 1986-04-21 1987-10-29 Sumitomo Eaton Noba Kk Charging-preventive method for wafer
JPH01134916A (en) * 1987-11-19 1989-05-26 Nec Yamagata Ltd Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS549575A (en) * 1977-06-24 1979-01-24 Fujitsu Ltd Ion injection method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS549575A (en) * 1977-06-24 1979-01-24 Fujitsu Ltd Ion injection method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248223A (en) * 1986-04-21 1987-10-29 Sumitomo Eaton Noba Kk Charging-preventive method for wafer
JPH01134916A (en) * 1987-11-19 1989-05-26 Nec Yamagata Ltd Manufacture of semiconductor device

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