JPS5790969A - Electrostatic protective circuit for complementary-metal oxide semiconductor-integrated circuit - Google Patents

Electrostatic protective circuit for complementary-metal oxide semiconductor-integrated circuit

Info

Publication number
JPS5790969A
JPS5790969A JP55166889A JP16688980A JPS5790969A JP S5790969 A JPS5790969 A JP S5790969A JP 55166889 A JP55166889 A JP 55166889A JP 16688980 A JP16688980 A JP 16688980A JP S5790969 A JPS5790969 A JP S5790969A
Authority
JP
Japan
Prior art keywords
pad electrode
layer
diffusion layer
insulating film
complementary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55166889A
Other languages
Japanese (ja)
Inventor
Naoyuki Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55166889A priority Critical patent/JPS5790969A/en
Publication of JPS5790969A publication Critical patent/JPS5790969A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the dielectric resistance of electrostatic breakdown by a method wherein a deep P<-> diffusion layer and a P<+> diffusion layer are formed just under a pad electrode and used as a protective diode, and the pad electrode and a P<+> layer are ohmic-contacted without putting an insulating film. CONSTITUTION:The P<-> diffusion layer 6 is shaped in a pad forming region in a process which shapes a P well to an N<-> type substrate, and the P<+> layer 4 is formed so as to stack on the P<-> region 6 in a forming process of the P<+> diffusion layer. A passivation film 2 of a pad electrode forming section is opened in a contact hole forming process, and the pad electrode 1 is directly ohmic- contacted with the P<+> layer 4. Accordingly, the P<+>P<->N<-> diode having the same area as the pad electrode is prepared, and used as the electrostatic protective circuit for the CMOSIC. Since there is no insulating film (such as the film 2) under the pad electrode 1, the dielectric resistance against the electrostatic breakdown can be made higher than limit value by the dielectric resistance of the insulating film without special processes.
JP55166889A 1980-11-27 1980-11-27 Electrostatic protective circuit for complementary-metal oxide semiconductor-integrated circuit Pending JPS5790969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55166889A JPS5790969A (en) 1980-11-27 1980-11-27 Electrostatic protective circuit for complementary-metal oxide semiconductor-integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55166889A JPS5790969A (en) 1980-11-27 1980-11-27 Electrostatic protective circuit for complementary-metal oxide semiconductor-integrated circuit

Publications (1)

Publication Number Publication Date
JPS5790969A true JPS5790969A (en) 1982-06-05

Family

ID=15839495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55166889A Pending JPS5790969A (en) 1980-11-27 1980-11-27 Electrostatic protective circuit for complementary-metal oxide semiconductor-integrated circuit

Country Status (1)

Country Link
JP (1) JPS5790969A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263285A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Semiconductor device
US5932917A (en) * 1996-04-19 1999-08-03 Nippon Steel Corporation Input protective circuit having a diffusion resistance layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263285A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Semiconductor device
JPH0528511B2 (en) * 1985-05-17 1993-04-26 Matsushita Electronics Corp
US5932917A (en) * 1996-04-19 1999-08-03 Nippon Steel Corporation Input protective circuit having a diffusion resistance layer

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