JPS5730347A - Multilayer wiring structure and manufacture thereof - Google Patents

Multilayer wiring structure and manufacture thereof

Info

Publication number
JPS5730347A
JPS5730347A JP10569380A JP10569380A JPS5730347A JP S5730347 A JPS5730347 A JP S5730347A JP 10569380 A JP10569380 A JP 10569380A JP 10569380 A JP10569380 A JP 10569380A JP S5730347 A JPS5730347 A JP S5730347A
Authority
JP
Japan
Prior art keywords
mask
wiring
wiring layer
pattern
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10569380A
Other languages
Japanese (ja)
Inventor
Yasushige Ueoka
Kinya Kato
Takashi Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10569380A priority Critical patent/JPS5730347A/en
Publication of JPS5730347A publication Critical patent/JPS5730347A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a flat multilayer wire having mask accuracy without stepwise disconnection by laminating high resistance amorphous to polycrystalline semiconductor layer formed of low resistance region of the prescribed pattern as a wiring layer. CONSTITUTION:An amorphous to polycrystalline silicon layer K1 having high resistance is formed on a substrate 1, and impurity ions are injected in a wiring pattern shape using a mask of photoresist. Then, the mask is removed, the overall surface is irradiated with a laser beam to reduce the resistance of the ion implanted region E1, and a wiring layer W1 is formed. Similarly, a wiring connector G12 and the second wiring layer W2 are formed. Since it has flat surface, the accuracy of the pattern is improved, and a multilayer wire having no stepwise disconnection can be obtained.
JP10569380A 1980-07-31 1980-07-31 Multilayer wiring structure and manufacture thereof Pending JPS5730347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10569380A JPS5730347A (en) 1980-07-31 1980-07-31 Multilayer wiring structure and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10569380A JPS5730347A (en) 1980-07-31 1980-07-31 Multilayer wiring structure and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5730347A true JPS5730347A (en) 1982-02-18

Family

ID=14414466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10569380A Pending JPS5730347A (en) 1980-07-31 1980-07-31 Multilayer wiring structure and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5730347A (en)

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