JPH04314352A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a failure contact by forming the contact as low resistance by providing asperity on a substrate layer on the bottom of a contact hole. CONSTITUTION:A BPSG film is removed and contact holes 16, 17 are formed by patterning and dry-etching a resist with a photolithography process. Successively, etching is performed in a 500mTorr chamber using etching gas of a mixture ratio of Cl2:He=1:1 under the conditions of 200W RF power to form asperity on the surface of a diffusion layer 13 and on the surface of a polysilicon film 14. Hereby, an electric field is concentrated at the tip end of a concave portion of the asperity to facilitate the flow of a tunnel current. Further, as the current is increased, a natural oxide film is rendered to dielectric breakdown to facilitate the flow of a leakage current. Thus, a stable contact with reduced contact resistance can be formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing contact holes in a semiconductor device having laminated metal wiring using barrier metal.

0002

[Prior Art] Conventional tungsten silicide (WSi)
) is used as a barrier metal to produce a semiconductor device having a laminated aluminum wiring. In order to simplify the explanation, only the method of manufacturing the contact portion will be explained.

In FIG. 2, after forming a field oxide film 2 for element isolation, a diffusion layer 3, a conductive polysilicon film 4, and elements such as transistors (not shown) on a single crystal silicon substrate 1, The insulating film 5, for example BP
An SG film is formed on the entire surface.

Next, a resist film (not shown) is patterned by photolithography, and the BPSG film 5 is etched by dry etching to form contact holes 6 and 7 on the diffusion layer 3 and the polysilicon film 4, respectively.
Form on top. At this time, for example, CH as an etching gas.
Using a mixed gas of F3:O2 = 5:1, pressure 50m
The BPSG film can be etched by dry etching with an RF power of 300 W in a TORR chamber.

Next, a tungsten silicide film 8 and an aluminum alloy film 9 as barrier metals are sequentially deposited by sputtering or the like. When this is patterned by photolithography and etching techniques, laminated wiring is formed and connected to the diffusion layer 3 and the polysilicon film 4 through contact holes 6 and 7, respectively.

[0006] The reason why such laminated wiring is used is that in the case of a single layer of aluminum alloy film, aluminum penetrates into the diffusion layer, causing leakage current between the diffusion layer and the single crystal silicon substrate. This can be mentioned. Another problem is that silicon precipitates in the aluminum-based alloy wiring in the contact hole and a high-resistance single crystal grows, increasing the contact resistance.

[0007]

[Problems to be Solved by the Invention] However, in the two-layer structure of the tungsten silicide film and the aluminum-based alloy film described above, there are problems due to the deionized water cleaning process before depositing the tungsten silicide and the entrainment of air during the deposition of the tungsten silicide. Since a native oxide film of about 10 to 30 Å is formed on the diffusion layer 3 and the polysilicon film 4, there is a problem that the contact resistance is unstable.

[0008]

[Means for Solving the Problems] The present invention provides a semiconductor device having stacked wiring using barrier metal, in which irregularities (hereinafter referred to as asperities) are provided in the surface layer at the bottom of a contact hole.

[0009]

According to the present invention, in the method of manufacturing a semiconductor device, an asperity is provided in the surface layer at the bottom of the contact, so that the electric field is concentrated at the tip of the convex portion, making it easier for tunnel current to flow. Furthermore, when the electric field becomes high, dielectric breakdown occurs in the natural oxide film, making it easier for leakage current to flow. Therefore, a stable contact with low contact resistance can be formed.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing an embodiment of the present invention. As before, a thick field oxide film 12, a diffusion layer 13, and a conductive polysilicon film 14 are formed on a single crystal silicon substrate 11, and an insulating film 15, such as a BPSG film, is deposited to a thickness of, for example, 8000 Å over the entire surface by CVD or the like. .

Next, a resist (not shown) is patterned by photolithography, and dry etching is performed. In this dry etching, for example, first, an etching gas with a mixing ratio of CHF3:O2 = 5:1 is used,
RF power 30 in a chamber with a pressure of 50 mtorr
The BPSG film is removed under the condition of 0W. Contact holes 16 and 17 are formed by this etching. Next, when etching is performed using an etching gas with a mixing ratio of Cl2:He=1:1 in a chamber with a pressure of 500 mtorr and an RF power of 200 W, asperities are formed on the surface of the diffusion layer 13 and the polysilicon film 14. It is formed.

There are several methods for forming asperities, and typical examples include chemical etching with a gas containing chlorine or fluorine, and physical etching with Ar or other ions. Although the present invention does not limit the conditions for forming asperities, examples of the former include etching gas Cl2:O2 = 10:1;
A method of etching with RF power of 125 W at a pressure of 75 mtorr, etching gas SF6:He=4:
There is a method of etching with 90 W of RF power and a pressure of 1.0 torr. An example of the latter is in an Ar atmosphere.
There is a method of etching using ion bombardment at a pressure of 0.5 torr and an RF power of 500 W.

Next, a tungsten silicide film 18 and an aluminum alloy film 19 are sequentially deposited by sputtering or the like, and patterned by photolithography and etching to electrically connect the diffusion layer 13 and the polysilicon film 14. A laminated wiring is formed. Further, this laminated wiring may be a conductive polysilicon wiring. Finally, a silicon nitride film or the like is formed as a protective film by, for example, plasma CVD, and the semiconductor device is completed.

[0014]

As described above in detail, according to the manufacturing method of the present invention, asperities are formed in the surface layer at the bottom of the contact hole, so that the contact current increases and the contact becomes low in resistance. Defects are reduced and contact stability is increased. Therefore, it is expected that semiconductor devices with improved reliability can be manufactured with high yield.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing an example of the prior art.

[Explanation of symbols]

11 Single crystal silicon substrate 12 Field oxide film 13 Diffusion layer 14 Polysilicon 15 Insulating film 16, 17 Conct hall 18 Barrier metal 19 Aluminum alloy

Claims (1)

[Claims] 1. In a semiconductor device in which an upper layer and a lower layer of the insulating film are electrically connected through a contact hole formed in the insulating film, the step of forming an uneven surface on the surface exposed by the contact hole; A method of manufacturing a semiconductor device, comprising sequentially performing a step of forming a laminated metal wiring or a polysilicon wiring using a barrier metal as an underlying layer in the contact hole.