DE19882265B4 - Flash-Speicher-VDS-Kompensationstechniken zum Verringern von Programmierschwankungen - Google Patents

Flash-Speicher-VDS-Kompensationstechniken zum Verringern von Programmierschwankungen Download PDF

Info

Publication number
DE19882265B4
DE19882265B4 DE19882265T DE19882265T DE19882265B4 DE 19882265 B4 DE19882265 B4 DE 19882265B4 DE 19882265 T DE19882265 T DE 19882265T DE 19882265 T DE19882265 T DE 19882265T DE 19882265 B4 DE19882265 B4 DE 19882265B4
Authority
DE
Germany
Prior art keywords
source
volatile memory
voltage
memory cell
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19882265T
Other languages
German (de)
English (en)
Other versions
DE19882265T1 (de
Inventor
Stephen N. San Jose Keeney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19882265T1 publication Critical patent/DE19882265T1/de
Application granted granted Critical
Publication of DE19882265B4 publication Critical patent/DE19882265B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE19882265T 1997-03-31 1998-01-28 Flash-Speicher-VDS-Kompensationstechniken zum Verringern von Programmierschwankungen Expired - Fee Related DE19882265B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/828,873 US5798966A (en) 1997-03-31 1997-03-31 Flash memory VDS compensation techiques to reduce programming variability
US08/828,873 1997-03-31
PCT/US1998/001599 WO1998044510A1 (en) 1997-03-31 1998-01-28 Flash memory vds compensation techniques to reduce programming variability

Publications (2)

Publication Number Publication Date
DE19882265T1 DE19882265T1 (de) 2000-05-25
DE19882265B4 true DE19882265B4 (de) 2005-02-10

Family

ID=25252981

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19882265T Expired - Fee Related DE19882265B4 (de) 1997-03-31 1998-01-28 Flash-Speicher-VDS-Kompensationstechniken zum Verringern von Programmierschwankungen

Country Status (9)

Country Link
US (1) US5798966A (enExample)
JP (1) JP4173555B2 (enExample)
KR (1) KR100313746B1 (enExample)
CN (1) CN100392759C (enExample)
AU (1) AU6252398A (enExample)
DE (1) DE19882265B4 (enExample)
TW (1) TW425557B (enExample)
WO (1) WO1998044510A1 (enExample)
ZA (1) ZA981131B (enExample)

Families Citing this family (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60041050D1 (de) * 2000-07-18 2009-01-22 St Microelectronics Srl Verfahren und Schaltung zum Ändern der Schwellenspannungen von nichtflüchtigen Speicherzellen
US7247304B2 (en) * 2001-08-23 2007-07-24 Genmab A/S Methods of treating using anti-IL-15 antibodies
EP1331644B1 (en) * 2001-12-28 2007-03-14 STMicroelectronics S.r.l. Regulation method for the source voltage in a nonvolatile memory cell during programming and corresponding program circuit
US6781884B2 (en) * 2002-03-11 2004-08-24 Fujitsu Limited System for setting memory voltage threshold
JP2004110871A (ja) * 2002-09-13 2004-04-08 Fujitsu Ltd 不揮発性半導体記憶装置
US6639824B1 (en) * 2002-09-19 2003-10-28 Infineon Technologies Aktiengesellschaft Memory architecture
KR100550790B1 (ko) * 2003-03-07 2006-02-08 주식회사 하이닉스반도체 플래시 메모리용 드레인 펌프
US6909638B2 (en) * 2003-04-30 2005-06-21 Freescale Semiconductor, Inc. Non-volatile memory having a bias on the source electrode for HCI programming
US6891758B2 (en) * 2003-05-08 2005-05-10 Micron Technology, Inc. Position based erase verification levels in a flash memory device
KR100688494B1 (ko) * 2003-07-10 2007-03-02 삼성전자주식회사 플래시 메모리 장치
JP4278140B2 (ja) * 2003-09-03 2009-06-10 シャープ株式会社 半導体記憶装置
US7009887B1 (en) * 2004-06-03 2006-03-07 Fasl Llc Method of determining voltage compensation for flash memory devices
KR100606173B1 (ko) * 2004-08-24 2006-08-01 삼성전자주식회사 불휘발성 메모리 장치의 초기화 상태를 검증하는 방법 및장치
US7218570B2 (en) * 2004-12-17 2007-05-15 Sandisk 3D Llc Apparatus and method for memory operations using address-dependent conditions
JP4746326B2 (ja) * 2005-01-13 2011-08-10 株式会社東芝 不揮発性半導体記憶装置
KR100714485B1 (ko) * 2005-08-23 2007-05-07 삼성전자주식회사 비휘발성 반도체 메모리 장치
KR100735010B1 (ko) 2005-09-08 2007-07-03 삼성전자주식회사 플래시 메모리 장치 및 그것을 위한 전압 발생회로
US20070140019A1 (en) * 2005-12-21 2007-06-21 Macronix International Co., Ltd. Method and apparatus for operating a string of charge trapping memory cells
KR101333503B1 (ko) * 2006-02-03 2013-11-28 삼성전자주식회사 프로그램 셀의 수에 따라 프로그램 전압을 조절하는 반도체메모리 장치 및 그것의 프로그램 방법
US7313018B2 (en) * 2006-03-08 2007-12-25 Macronix International Co., Ltd. Methods and apparatus for a non-volatile memory device with reduced program disturb
WO2007132456A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device with adaptive capacity
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US8050086B2 (en) * 2006-05-12 2011-11-01 Anobit Technologies Ltd. Distortion estimation and cancellation in memory devices
US8060806B2 (en) * 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
WO2008068747A2 (en) 2006-12-03 2008-06-12 Anobit Technologies Ltd. Automatic defect management in memory devices
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
WO2008111058A2 (en) 2007-03-12 2008-09-18 Anobit Technologies Ltd. Adaptive estimation of memory cell read thresholds
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8429493B2 (en) * 2007-05-12 2013-04-23 Apple Inc. Memory device with internal signap processing unit
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
JP4504397B2 (ja) * 2007-05-29 2010-07-14 株式会社東芝 半導体記憶装置
US8259497B2 (en) * 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
WO2009050703A2 (en) 2007-10-19 2009-04-23 Anobit Technologies Data storage in analog memory cell arrays having erase failures
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8270246B2 (en) 2007-11-13 2012-09-18 Apple Inc. Optimized selection of memory chips in multi-chips memory devices
US8225181B2 (en) * 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) * 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
JP2009301691A (ja) * 2008-06-17 2009-12-24 Renesas Technology Corp 不揮発性半導体記憶装置
JP2010055735A (ja) * 2008-07-31 2010-03-11 Panasonic Corp 半導体記憶装置
US8498151B1 (en) 2008-08-05 2013-07-30 Apple Inc. Data storage in analog memory cells using modified pass voltages
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8094509B2 (en) * 2008-10-30 2012-01-10 Spansion Llc Apparatus and method for placement of boosting cell with adaptive booster scheme
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
KR20100058166A (ko) * 2008-11-24 2010-06-03 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8397131B1 (en) 2008-12-31 2013-03-12 Apple Inc. Efficient readout schemes for analog memory cell devices
KR20100084285A (ko) * 2009-01-16 2010-07-26 삼성전자주식회사 셀의 위치를 고려하여 니어-셀과 파-셀간 동작 전압의 차이를 보상하는 반도체 메모리 장치, 그를 포함하는 메모리 카드 및 메모리 시스템
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
JP5468023B2 (ja) * 2009-02-06 2014-04-09 パナソニック株式会社 不揮発性半導体メモリ
US8228701B2 (en) * 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8004875B2 (en) * 2009-07-13 2011-08-23 Seagate Technology Llc Current magnitude compensation for memory cells in a data storage array
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
JP5259552B2 (ja) 2009-11-02 2013-08-07 株式会社東芝 不揮発性半導体記憶装置及びその駆動方法
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
KR101644979B1 (ko) * 2010-02-01 2016-08-03 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 읽기 방법
US8619489B2 (en) 2010-04-30 2013-12-31 Stmicroelectronics S.R.L. Driving circuit for memory device
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
JP5502773B2 (ja) * 2011-02-01 2014-05-28 株式会社東芝 不揮発性半導体記憶装置
WO2012039511A1 (en) * 2010-09-24 2012-03-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US8923040B2 (en) * 2013-01-30 2014-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Accommodating balance of bit line and source line resistances in magnetoresistive random access memory
US9202579B2 (en) * 2013-03-14 2015-12-01 Sandisk Technologies Inc. Compensation for temperature dependence of bit line resistance
JP6149598B2 (ja) * 2013-08-19 2017-06-21 ソニー株式会社 記憶制御装置、記憶装置、情報処理システムおよび記憶制御方法
US9633742B2 (en) 2014-07-10 2017-04-25 Sandisk Technologies Llc Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices
US9728262B2 (en) * 2015-10-30 2017-08-08 Sandisk Technologies Llc Non-volatile memory systems with multi-write direction memory units
CN106297887B (zh) * 2016-07-27 2020-05-19 深圳市航顺芯片技术研发有限公司 一种提升eeprom存储器编程精度的升压电路及其方法
JP7031672B2 (ja) * 2017-09-01 2022-03-08 ソニーグループ株式会社 メモリコントローラ、メモリシステムおよび情報処理システム
US10199100B1 (en) * 2017-09-28 2019-02-05 Inston Inc. Sensing circuit and memory using thereof
CN110718257A (zh) * 2018-07-11 2020-01-21 西安格易安创集成电路有限公司 一种电压偏置电路及方法
US10755788B2 (en) 2018-11-06 2020-08-25 Sandisk Technologies Llc Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses
US10910064B2 (en) * 2018-11-06 2021-02-02 Sandisk Technologies Llc Location dependent impedance mitigation in non-volatile memory
US10650898B1 (en) * 2018-11-06 2020-05-12 Sandisk Technologies Llc Erase operation in 3D NAND flash memory including pathway impedance compensation
US11205480B1 (en) * 2020-09-11 2021-12-21 Micron Technology, Inc. Ramp-based biasing in a memory device
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402370A (en) * 1993-09-10 1995-03-28 Intel Corporation Circuitry and method for selecting a drain programming voltage for a nonvolatile memory
US5440405A (en) * 1992-09-02 1995-08-08 Ricoh Company, Ltd. Method and system for error correction using asynchronous digital facsimile protocol
US5497354A (en) * 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010520A (en) * 1987-07-29 1991-04-23 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with stabilized data write characteristic
US5077691A (en) * 1989-10-23 1991-12-31 Advanced Micro Devices, Inc. Flash EEPROM array with negative gate voltage erase operation
US5557572A (en) * 1992-04-24 1996-09-17 Nippon Steel Corporation Non-volatile semiconductor memory device
US5420370A (en) * 1992-11-20 1995-05-30 Colorado School Of Mines Method for controlling clathrate hydrates in fluid systems
DE4328581A1 (de) * 1993-08-25 1995-03-02 Nico Pyrotechnik Nebelwurfkörper
US5422845A (en) * 1993-09-30 1995-06-06 Intel Corporation Method and device for improved programming threshold voltage distribution in electrically programmable read only memory array
US5477499A (en) * 1993-10-13 1995-12-19 Advanced Micro Devices, Inc. Memory architecture for a three volt flash EEPROM
US5440505A (en) * 1994-01-21 1995-08-08 Intel Corporation Method and circuitry for storing discrete amounts of charge in a single memory element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440405A (en) * 1992-09-02 1995-08-08 Ricoh Company, Ltd. Method and system for error correction using asynchronous digital facsimile protocol
US5402370A (en) * 1993-09-10 1995-03-28 Intel Corporation Circuitry and method for selecting a drain programming voltage for a nonvolatile memory
US5497354A (en) * 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells

Also Published As

Publication number Publication date
JP4173555B2 (ja) 2008-10-29
CN100392759C (zh) 2008-06-04
KR20010005825A (ko) 2001-01-15
ZA981131B (en) 1999-08-11
AU6252398A (en) 1998-10-22
JP2001517350A (ja) 2001-10-02
KR100313746B1 (ko) 2001-11-16
TW425557B (en) 2001-03-11
CN1251683A (zh) 2000-04-26
US5798966A (en) 1998-08-25
DE19882265T1 (de) 2000-05-25
WO1998044510A1 (en) 1998-10-08

Similar Documents

Publication Publication Date Title
DE19882265B4 (de) Flash-Speicher-VDS-Kompensationstechniken zum Verringern von Programmierschwankungen
DE69514450T2 (de) Prüfung eines nichtflüchtigen Speichers
DE69521882T2 (de) Verfahren und schaltung zur speicherung von diskreten ladungspaketen in einem einzigen speicherelement
DE69706873T2 (de) Löschverfahren für mehrere-bits-pro-zelle flash -eeprom mit seitenmodus
DE69636063T2 (de) Verfahren zum Programmieren eines nichtflüchtigen Speichers
DE69603742T2 (de) Überlöschungskorrektur für flash-speicher mit überlöschungsbegrenzung und vermeidung von löschprüffehlern
DE60202077T2 (de) Spannungserhöhungs-schaltung mit bestimmung der versorgungsspannung zur kompensation von schwankungen der versorungsspannung beim lesen
DE69702256T2 (de) Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren
DE4433098C2 (de) Halbleiter-Permanentspeichervorrichtung
DE69614787T2 (de) Speichermatrix mit mehrzustandsspeicherzellen
DE69524913T2 (de) Nichtflüchtige Halbleiter-Speicherzelle mit Korrekturmöglichkeit einer überschriebenen Zelle, und Korrekturverfahren
DE4232025C2 (de) Elektrisch löschbarer und programmierbarer nichtflüchtiger Halbleiterspeicher mit automatischem Schreibprüfungs-Controller
DE69420651T2 (de) Korrekturstruktur für überlöschte Bits einer integrierten Halbleiterspeicherschaltung
DE60115716T2 (de) Weichprogrammierung und weichprogrammierverifikation von flash-speicherzellen
DE60127651T2 (de) Bitleitungs-Vorladungs- und -Entladungsschaltung zum Programmieren eines nichtflüchtigen Speichers
DE69511661T2 (de) Referenzschaltung
DE69122537T2 (de) EEPROM mit Schwellwertmessschaltung
DE69500143T2 (de) Schaltung zum Wählen von Redundanzspeicherbauelementen und diese enthaltende FLASH EEPROM
DE69417712T2 (de) Nichtflüchtige Halbleiter-Speichereinrichtung
DE3786819T2 (de) Nichtflüchtige Halbleiterspeicheranordnung.
DE102007041845A1 (de) Verfahren zum Betreiben eines integrierten Schaltkreises mit mindestens einer Speicherzelle
DE4207934A1 (de) Elektrisch loesch- und programmierbares, nichtfluechtiges speichersystem mit schreib-pruef-einsteller unter verwendung zweier bezugspegel
DE102005022611A1 (de) Programmierverfahren für ein nichtflüchtiges Speicherbauelement
DE102006003260A1 (de) Nichtflüchtiges Halbleiterspeicherbauelement mit Zellenkette
DE102008007685B4 (de) Integrierte Schaltung und Verfahren zum Betreiben einer integrierten Schaltung

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G11C 1612

8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee