DE112020000035T5 - Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm zur handhabung von befehlsfehlern - Google Patents
Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm zur handhabung von befehlsfehlern Download PDFInfo
- Publication number
- DE112020000035T5 DE112020000035T5 DE112020000035.4T DE112020000035T DE112020000035T5 DE 112020000035 T5 DE112020000035 T5 DE 112020000035T5 DE 112020000035 T DE112020000035 T DE 112020000035T DE 112020000035 T5 DE112020000035 T5 DE 112020000035T5
- Authority
- DE
- Germany
- Prior art keywords
- data
- memory
- command
- test
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31935—Storing data, e.g. failure memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Debugging And Monitoring (AREA)
- Microcomputers (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962795456P | 2019-01-22 | 2019-01-22 | |
US62/795,456 | 2019-01-22 | ||
PCT/EP2020/051543 WO2020152232A1 (en) | 2019-01-22 | 2020-01-22 | Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors |
Publications (1)
Publication Number | Publication Date |
---|---|
DE112020000035T5 true DE112020000035T5 (de) | 2020-12-31 |
Family
ID=69192062
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE112020000469.4T Pending DE112020000469T5 (de) | 2019-01-22 | 2020-01-22 | Automatisierte testeinrichtung, die ein auf-chip-system-teststeuergerät verwendet |
DE112020000035.4T Pending DE112020000035T5 (de) | 2019-01-22 | 2020-01-22 | Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm zur handhabung von befehlsfehlern |
DE112020000036.2T Pending DE112020000036T5 (de) | 2019-01-22 | 2020-01-22 | Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm unter verwendung eines pufferspeichers |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE112020000469.4T Pending DE112020000469T5 (de) | 2019-01-22 | 2020-01-22 | Automatisierte testeinrichtung, die ein auf-chip-system-teststeuergerät verwendet |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE112020000036.2T Pending DE112020000036T5 (de) | 2019-01-22 | 2020-01-22 | Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm unter verwendung eines pufferspeichers |
Country Status (7)
Country | Link |
---|---|
US (3) | US11385285B2 (ko) |
JP (3) | JP7058759B2 (ko) |
KR (3) | KR102604010B1 (ko) |
CN (3) | CN112703409B (ko) |
DE (3) | DE112020000469T5 (ko) |
TW (3) | TW202202865A (ko) |
WO (3) | WO2020152232A1 (ko) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11204849B2 (en) * | 2020-03-13 | 2021-12-21 | Nvidia Corporation | Leveraging low power states for fault testing of processing cores at runtime |
US11809570B2 (en) * | 2020-10-06 | 2023-11-07 | Newae Technology Inc | Method and apparatus for analyzing side channel-related security vulnerabilities in digital devices |
US11719749B1 (en) * | 2020-10-22 | 2023-08-08 | Cadence Design Systems, Inc. | Method and system for saving and restoring of initialization actions on dut and corresponding test environment |
US11836059B1 (en) | 2020-12-14 | 2023-12-05 | Sanblaze Technology, Inc. | System and method for testing non-volatile memory express storage devices |
CN112597006B (zh) * | 2020-12-14 | 2023-10-03 | 中国航发控制系统研究所 | 一种嵌入式软件集成测试自动化执行系统及方法 |
US11431379B1 (en) * | 2021-03-31 | 2022-08-30 | Teradyne, Inc. | Front-end module |
CN115391108A (zh) * | 2021-05-25 | 2022-11-25 | 爱德万测试股份有限公司 | 自动测试设备系统及其自动测试设备方法 |
CN113572661B (zh) * | 2021-07-28 | 2022-12-27 | 迈普通信技术股份有限公司 | 一种测试多激活检测性能的系统和方法 |
CN113836060B (zh) * | 2021-09-24 | 2024-05-28 | 北京机电工程研究所 | 一种适用于仿真模型及流程模型的分布式实时仿真平台 |
CN113961405B (zh) * | 2021-09-30 | 2022-10-28 | 北京百度网讯科技有限公司 | 状态切换指令验证方法、装置、电子设备及存储介质 |
CN118829890A (zh) * | 2021-11-08 | 2024-10-22 | 爱德万测试集团 | 自动测试设备、被测设备、测试装置、使用触发线的方法 |
CN114167258B (zh) * | 2021-11-29 | 2024-03-22 | 上海御渡半导体科技有限公司 | 一种ate测试系统的数据存储和读取装置及方法 |
CN113904970B (zh) * | 2021-12-09 | 2022-03-01 | 伟恩测试技术(武汉)有限公司 | 一种半导体测试设备的传输系统及方法 |
CN114461150B (zh) * | 2022-02-09 | 2024-08-16 | 马来西亚明试国际有限公司 | 一种用于自动测试设备数据聚合的方法、系统及存储介质 |
KR102461404B1 (ko) * | 2022-04-08 | 2022-10-31 | 주식회사 세미파이브 | 시스템 온 칩과 메모리 사이의 통신을 위한 io 파라미터를 설정하는 방법 및 장치 |
US11853251B2 (en) | 2022-05-04 | 2023-12-26 | Qualcomm Incorporated | On-die chip-to-chip (C2C) link state monitor |
US20240096432A1 (en) * | 2022-09-15 | 2024-03-21 | Advantest Corporation | Memory queue operations to increase throughput in an ate system |
TWI847363B (zh) * | 2022-11-14 | 2024-07-01 | 華邦電子股份有限公司 | 積體電路測試方法及裝置 |
TWI847391B (zh) * | 2022-11-28 | 2024-07-01 | 英業達股份有限公司 | 適用於SlimSAS插槽的檢測系統及其方法 |
CN116340191B (zh) * | 2023-05-31 | 2023-08-08 | 合肥康芯威存储技术有限公司 | 一种存储器固件的测试方法、装置、设备及介质 |
Family Cites Families (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2966417B2 (ja) * | 1988-09-05 | 1999-10-25 | 株式会社アドバンテスト | 論理集積回路試験装置 |
US5103450A (en) * | 1989-02-08 | 1992-04-07 | Texas Instruments Incorporated | Event qualified testing protocols for integrated circuits |
US7328387B2 (en) * | 2004-12-10 | 2008-02-05 | Texas Instruments Incorporated | Addressable tap domain selection circuit with selectable ⅗ pin interface |
US5321702A (en) * | 1989-10-11 | 1994-06-14 | Teradyne, Inc. | High speed timing generator |
JP3114753B2 (ja) * | 1991-10-31 | 2000-12-04 | 九州日本電気株式会社 | Lsiテスト方法 |
JPH07244130A (ja) * | 1994-03-02 | 1995-09-19 | Sony Tektronix Corp | テストパターン発生器 |
JPH08129508A (ja) * | 1994-10-31 | 1996-05-21 | Toshiba Corp | コンピュータシステム及びその共有メモリ制御方法 |
JPH10240560A (ja) * | 1997-02-26 | 1998-09-11 | Toshiba Corp | 波形信号処理装置 |
GB9805054D0 (en) * | 1998-03-11 | 1998-05-06 | Process Intelligence Limited | Memory test system with buffer memory |
WO2000000836A1 (en) * | 1998-06-29 | 2000-01-06 | Iliya Valeryevich Klochkov | A skew calibration means and a method of skew calibration |
US6452411B1 (en) * | 1999-03-01 | 2002-09-17 | Formfactor, Inc. | Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses |
JP2001210685A (ja) * | 1999-11-19 | 2001-08-03 | Hitachi Ltd | テストシステムおよび半導体集積回路装置の製造方法 |
US6424926B1 (en) | 2000-03-31 | 2002-07-23 | Intel Corporation | Bus signature analyzer and behavioral functional test method |
KR100374328B1 (ko) * | 2000-06-03 | 2003-03-03 | 박현숙 | 칩 설계 검증 및 테스트 장치 및 방법 |
JP2002156404A (ja) * | 2000-11-20 | 2002-05-31 | Seiko Epson Corp | 半導体測定方法及び半導体測定装置 |
JP2002311095A (ja) | 2001-04-12 | 2002-10-23 | Tritec:Kk | Lsi検査装置 |
US6988232B2 (en) | 2001-07-05 | 2006-01-17 | Intellitech Corporation | Method and apparatus for optimized parallel testing and access of electronic circuits |
JP2003121499A (ja) * | 2001-10-09 | 2003-04-23 | Hitachi Ltd | 組込みテスト機能付き半導体集積回路、テストコード生成プログラムから成る電子設計データを保存する記憶媒体、該半導体集積回路のテスト方法、テストコード生成自動化方法及びそのプログラム |
JP2005524852A (ja) * | 2002-05-08 | 2005-08-18 | エヌピーテスト, インコーポレイテッド | 多目的メモリを有するテスタシステム |
JP2004030765A (ja) * | 2002-06-25 | 2004-01-29 | Fujitsu Ltd | 自己診断機能内蔵の半導体記憶装置 |
JP3614838B2 (ja) | 2002-09-19 | 2005-01-26 | Necエレクトロニクス株式会社 | 半導体検査システム及び半導体デバイスの検査方法 |
US7131046B2 (en) * | 2002-12-03 | 2006-10-31 | Verigy Ipco | System and method for testing circuitry using an externally generated signature |
GB0315931D0 (en) * | 2003-07-08 | 2003-08-13 | Koninkl Philips Electronics Nv | Radio device testing system |
US7310752B2 (en) * | 2003-09-12 | 2007-12-18 | Micron Technology, Inc. | System and method for on-board timing margin testing of memory modules |
JP4602004B2 (ja) | 2004-06-22 | 2010-12-22 | 株式会社東芝 | テストパターン作成装置、テストパターン作成方法及びテストパターン作成プログラム |
US7089139B2 (en) * | 2004-08-16 | 2006-08-08 | Agilent Technologies, Inc. | Method and apparatus for configuration of automated debug of in-circuit tests |
US7627798B2 (en) * | 2004-10-08 | 2009-12-01 | Kabushiki Kaisha Toshiba | Systems and methods for circuit testing using LBIST |
US7437517B2 (en) * | 2005-01-11 | 2008-10-14 | International Business Machines Corporation | Methods and arrangements to manage on-chip memory to reduce memory latency |
JP2006266835A (ja) * | 2005-03-23 | 2006-10-05 | Advantest Corp | 試験装置、試験方法、及び試験制御プログラム |
US20070168809A1 (en) * | 2005-08-09 | 2007-07-19 | Naoki Kiryu | Systems and methods for LBIST testing using commonly controlled LBIST satellites |
CN1925384A (zh) * | 2005-09-02 | 2007-03-07 | 上海乐金广电电子有限公司 | 数字广播信息流传输错误检测装置及方法 |
US7562271B2 (en) | 2005-09-26 | 2009-07-14 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US7389461B2 (en) * | 2005-09-28 | 2008-06-17 | Teradyne, Inc. | Data capture in automatic test equipment |
CN1987236A (zh) * | 2005-12-22 | 2007-06-27 | 乐金电子(天津)电器有限公司 | 空调器的错误记录管理控制装置及其管理控制方法 |
US7552370B2 (en) * | 2006-03-31 | 2009-06-23 | Robert Pochowski | Application specific distributed test engine architecture system and method |
EP2003653B1 (en) * | 2006-04-06 | 2010-08-04 | Advantest Corporation | Test device and test method |
US7769558B2 (en) * | 2006-07-10 | 2010-08-03 | Asterion, Inc. | Digital waveform generation and measurement in automated test equipment |
WO2008014827A1 (en) * | 2006-08-04 | 2008-02-07 | Verigy (Singapore) Pte. Ltd. | Test module with blocks of universal and specific resources |
US7698088B2 (en) * | 2006-11-15 | 2010-04-13 | Silicon Image, Inc. | Interface test circuitry and methods |
US7486205B2 (en) * | 2006-11-28 | 2009-02-03 | Samplify Systems, Inc. | Compression and decompression of stimulus and response waveforms in automated test systems |
US7788562B2 (en) * | 2006-11-29 | 2010-08-31 | Advantest Corporation | Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data |
US20080196103A1 (en) * | 2007-02-09 | 2008-08-14 | Chao-Yu Lin | Method for analyzing abnormal network behaviors and isolating computer virus attacks |
KR100897681B1 (ko) * | 2007-04-05 | 2009-05-14 | 베리지 (싱가포르) 피티이. 엘티디. | 테스트 프로그램 적응 시스템 및 자동화 테스트 시스템 |
US20090112548A1 (en) * | 2007-10-30 | 2009-04-30 | Conner George W | A method for testing in a reconfigurable tester |
US7717752B2 (en) | 2008-07-01 | 2010-05-18 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US20100023294A1 (en) * | 2008-07-28 | 2010-01-28 | Credence Systems Corporation | Automated test system and method |
US8677198B2 (en) * | 2009-03-04 | 2014-03-18 | Alcatel Lucent | Method and apparatus for system testing using multiple processors |
US8195419B2 (en) * | 2009-03-13 | 2012-06-05 | Teradyne, Inc. | General purpose protocol engine |
US8170828B2 (en) | 2009-06-05 | 2012-05-01 | Apple Inc. | Test method using memory programmed with tests and protocol to communicate between device under test and tester |
US8386867B2 (en) * | 2009-07-02 | 2013-02-26 | Silicon Image, Inc. | Computer memory test structure |
US8261119B2 (en) * | 2009-09-10 | 2012-09-04 | Advantest Corporation | Test apparatus for testing device has synchronization module which synchronizes analog test module to digital test module based on synchronization signal received from digital test module |
US20110273197A1 (en) * | 2010-05-07 | 2011-11-10 | Qualcomm Incorporated | Signal generator for a built-in self test |
JP2011248597A (ja) * | 2010-05-26 | 2011-12-08 | Yokogawa Electric Corp | テスタシミュレーション装置、テスタシミュレーションプログラムおよびテスタシミュレーション方法 |
KR101789848B1 (ko) * | 2010-05-28 | 2017-10-25 | 주식회사 아도반테스토 | 가변 병렬성 및 펌웨어 업그레이드 기능을 갖는 유연한 저장 인터페이스 테스터 |
CN103109275B (zh) * | 2010-09-07 | 2016-02-03 | 爱德万测试公司 | 在半导体测试环境中使用虚拟仪器的系统、方法和设备 |
US8598898B2 (en) * | 2010-10-05 | 2013-12-03 | Silicon Image, Inc. | Testing of high-speed input-output devices |
US9043665B2 (en) * | 2011-03-09 | 2015-05-26 | Intel Corporation | Functional fabric based test wrapper for circuit testing of IP blocks |
US20120324302A1 (en) * | 2011-06-17 | 2012-12-20 | Qualcomm Incorporated | Integrated circuit for testing using a high-speed input/output interface |
US9470759B2 (en) * | 2011-10-28 | 2016-10-18 | Teradyne, Inc. | Test instrument having a configurable interface |
US20130227367A1 (en) * | 2012-01-17 | 2013-08-29 | Allen J. Czamara | Test IP-Based A.T.E. Instrument Architecture |
TW201337236A (zh) | 2012-03-15 | 2013-09-16 | Le & Der Co Ltd | 流體自動化採樣控制裝置 |
US9606183B2 (en) * | 2012-10-20 | 2017-03-28 | Advantest Corporation | Pseudo tester-per-site functionality on natively tester-per-pin automatic test equipment for semiconductor test |
US9026869B1 (en) * | 2012-11-01 | 2015-05-05 | Amazon Technologies, Inc. | Importance-based data storage verification |
US9959186B2 (en) * | 2012-11-19 | 2018-05-01 | Teradyne, Inc. | Debugging in a semiconductor device test environment |
US9183952B2 (en) * | 2013-02-20 | 2015-11-10 | Micron Technology, Inc. | Apparatuses and methods for compressing data received over multiple memory accesses |
US11009550B2 (en) * | 2013-02-21 | 2021-05-18 | Advantest Corporation | Test architecture with an FPGA based test board to simulate a DUT or end-point |
US20140236527A1 (en) * | 2013-02-21 | 2014-08-21 | Advantest Corporation | Cloud based infrastructure for supporting protocol reconfigurations in protocol independent device testing systems |
US9952276B2 (en) * | 2013-02-21 | 2018-04-24 | Advantest Corporation | Tester with mixed protocol engine in a FPGA block |
US20140237292A1 (en) * | 2013-02-21 | 2014-08-21 | Advantest Corporation | Gui implementations on central controller computer system for supporting protocol independent device testing |
US10161993B2 (en) | 2013-02-21 | 2018-12-25 | Advantest Corporation | Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block |
US10162007B2 (en) * | 2013-02-21 | 2018-12-25 | Advantest Corporation | Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently |
US9810729B2 (en) * | 2013-02-28 | 2017-11-07 | Advantest Corporation | Tester with acceleration for packet building within a FPGA block |
US9310427B2 (en) * | 2013-07-24 | 2016-04-12 | Advantest Corporation | High speed tester communication interface between test slice and trays |
US20150153405A1 (en) * | 2013-12-04 | 2015-06-04 | Princeton Technology Corporation | Automatic testing system and method |
CN204044309U (zh) * | 2014-01-24 | 2014-12-24 | 矽创电子股份有限公司 | 自动测试设备和升级自动测试设备的集成电路测试界面 |
US9934831B2 (en) * | 2014-04-07 | 2018-04-03 | Micron Technology, Inc. | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters |
US9304846B2 (en) * | 2014-04-29 | 2016-04-05 | Ford Global Technologies, Llc | Apparatus and method of error monitoring with a diagnostic module |
US9811420B2 (en) * | 2015-03-27 | 2017-11-07 | Intel Corporation | Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) |
JP6458626B2 (ja) * | 2015-05-07 | 2019-01-30 | 富士通株式会社 | デバッグ回路、半導体装置及びデバッグ方法 |
KR102377362B1 (ko) * | 2015-07-08 | 2022-03-23 | 삼성전자주식회사 | 보조 테스트 장치, 그것을 포함하는 테스트 보드 및 그것의 테스트 방법 |
JP6386434B2 (ja) * | 2015-10-08 | 2018-09-05 | 株式会社アドバンテスト | 試験装置、試験信号供給装置、試験方法、およびプログラム |
CN105895163B (zh) * | 2016-03-28 | 2018-09-28 | 工业和信息化部电子第五研究所 | 基于镜像备份的单粒子效应检测方法和系统 |
US10395748B2 (en) * | 2016-06-15 | 2019-08-27 | Micron Technology, Inc. | Shared error detection and correction memory |
JP2018006406A (ja) * | 2016-06-28 | 2018-01-11 | 東京エレクトロン株式会社 | 基板検査装置 |
JP6686769B2 (ja) | 2016-07-27 | 2020-04-22 | 富士通株式会社 | テストパタン生成装置及びテストパタン生成方法 |
US11309056B2 (en) * | 2017-01-31 | 2022-04-19 | Octavo Systems Llc | Automatic test equipment method for testing system in a package devices |
JP6878071B2 (ja) | 2017-03-21 | 2021-05-26 | 株式会社東芝 | 半導体集積回路及び半導体集積回路の診断方法 |
US10580200B2 (en) | 2017-04-07 | 2020-03-03 | Intel Corporation | Virtual reality apparatus and method including prioritized pixel shader operations, alternate eye rendering, and/or augmented timewarp |
CN107390109B (zh) * | 2017-06-09 | 2019-12-24 | 苏州迅芯微电子有限公司 | 高速adc芯片的自动测试平台及其软件架构设计方法 |
TWI661208B (zh) * | 2017-10-11 | 2019-06-01 | 致茂電子股份有限公司 | 測試裝置及其測試電路板 |
-
2020
- 2020-01-22 WO PCT/EP2020/051543 patent/WO2020152232A1/en active Application Filing
- 2020-01-22 JP JP2020560932A patent/JP7058759B2/ja active Active
- 2020-01-22 CN CN202080005127.6A patent/CN112703409B/zh active Active
- 2020-01-22 DE DE112020000469.4T patent/DE112020000469T5/de active Pending
- 2020-01-22 DE DE112020000035.4T patent/DE112020000035T5/de active Pending
- 2020-01-22 CN CN202080010066.2A patent/CN113330322B/zh active Active
- 2020-01-22 WO PCT/EP2020/051540 patent/WO2020152231A1/en active Application Filing
- 2020-01-22 JP JP2021532983A patent/JP7295954B2/ja active Active
- 2020-01-22 KR KR1020217026464A patent/KR102604010B1/ko active IP Right Grant
- 2020-01-22 DE DE112020000036.2T patent/DE112020000036T5/de active Pending
- 2020-01-22 KR KR1020217015271A patent/KR102591340B1/ko active IP Right Grant
- 2020-01-22 JP JP2020561063A patent/JP7101814B2/ja active Active
- 2020-01-22 KR KR1020217015278A patent/KR102569335B1/ko active IP Right Grant
- 2020-01-22 WO PCT/EP2020/051538 patent/WO2020152230A1/en active Application Filing
- 2020-01-22 CN CN202080002335.0A patent/CN111989580B/zh active Active
- 2020-07-06 TW TW109122802A patent/TW202202865A/zh unknown
- 2020-07-06 TW TW109122801A patent/TWI853054B/zh active
- 2020-07-06 TW TW109122800A patent/TWI853053B/zh active
- 2020-10-14 US US17/070,696 patent/US11385285B2/en active Active
- 2020-11-10 US US17/094,129 patent/US11913990B2/en active Active
- 2020-11-10 US US17/094,047 patent/US11415628B2/en active Active
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE112020000035T5 (de) | Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm zur handhabung von befehlsfehlern | |
DE102013114564B4 (de) | System zur Reduzierung einer Leistungsspitze während einer Abtastverschiebung auf lokaler Ebene für abtastbasierte Prüfungen | |
DE3903835C2 (ko) | ||
DE10343227A1 (de) | System und Verfahren zum Testen eines Schaltungsaufbaus unter Verwendung einer extern erzeugten Signatur | |
DE3750236T2 (de) | Gerät zur In-line-Abfragesteuerung für Datenprozessorprüfung. | |
DE69019402T2 (de) | Prüfverfahren und -gerät für integrierte Schaltungen. | |
DE4402796C2 (de) | Verbesserte Redundanzanalysiereinrichtung für eine automatische Speichertestvorrichtung | |
DE69705813T2 (de) | Diagnosesystem und Verfahren bei einer integrierten Halbleiterschaltung | |
DE102008012337A1 (de) | Programmcode-Trace-Signatur | |
DE112008000542T5 (de) | Verfahren und Vorrichtungen zum Schätzen einer Position eines Hängenbleibe-Defekts in einer Abtastkette eines Testobjekts | |
DE102013114512B4 (de) | Globales Einfangschema mit niedriger Leistung für Kerne | |
DE69717385T2 (de) | Verfahren und System zur Speichereinrichtungsprüfung | |
EP1720100A1 (de) | Verfahren und Vorrichtung zur Emulation einer programmierbaren Einheit | |
EP0104635A2 (de) | Verfahren und Anordnung zum Prüfen eines digitalen Rechners | |
DE102010012904A1 (de) | Systeme zum Testen von Verbindungen zwischen Chips | |
DE10250875B4 (de) | Vorrichtung und Verfahren zum Konfigurieren einer integrierten Schaltung mit eingebettetem Speicher | |
DE112019007386T5 (de) | Verbesserte jtag-register mit gleichzeitigen eingängen | |
DE69600327T2 (de) | Ausgangschnittstelle für binäre Daten | |
EP0037965B1 (de) | Einrichtung zum Prüfen einer digitalen Schaltung mittels in diese Schaltung eingebauter Prüfschaltungen | |
EP0009600A2 (de) | Verfahren und Schnittstellenadapter zum Durchführen von Wartungsoperationen über eine Schnittstelle zwischen einem Wartungsprozessor und einer Mehrzahl einzeln zu prüfender Funktionseinheiten eines datenverarbeitenden Systems | |
CH694927A5 (de) | Verfahren und Vorrichtung zur Fehleranalyse digitaler Logikschatungen.. | |
DE102022203611A1 (de) | Hochfrequente ereignisbasierte hardware-diagnosen | |
DE112021006446T5 (de) | Automatische zuweisung von debug-kommunikationspins einer vorrichtung | |
DE102020130330A1 (de) | Verpackungsmaschine für mikroelektronische Bauteile mit einer Prüfung auf verdeckte mechanische Beschädigungen | |
DE19604375C2 (de) | Verfahren zur Auswertung von Testantworten zu prüfender digitaler Schaltungen und Schaltungsanordnung zur Durchführung des Verfahrens |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R012 | Request for examination validly filed |