DE10063621A1 - Verfahren zum Bilden feiner Muster und dieses Verfahren verwendendes Verfahren zum Herstellen von Halbleiter- oder Flüssigkristallvorrichtungen - Google Patents
Verfahren zum Bilden feiner Muster und dieses Verfahren verwendendes Verfahren zum Herstellen von Halbleiter- oder FlüssigkristallvorrichtungenInfo
- Publication number
- DE10063621A1 DE10063621A1 DE10063621A DE10063621A DE10063621A1 DE 10063621 A1 DE10063621 A1 DE 10063621A1 DE 10063621 A DE10063621 A DE 10063621A DE 10063621 A DE10063621 A DE 10063621A DE 10063621 A1 DE10063621 A1 DE 10063621A1
- Authority
- DE
- Germany
- Prior art keywords
- film
- pattern
- hard mask
- etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Semiconductor Memories (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000188160A JP2002009056A (ja) | 2000-06-22 | 2000-06-22 | 微細パターン形成方法およびその方法により製造した装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE10063621A1 true DE10063621A1 (de) | 2002-01-10 |
Family
ID=18688000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10063621A Ceased DE10063621A1 (de) | 2000-06-22 | 2000-12-20 | Verfahren zum Bilden feiner Muster und dieses Verfahren verwendendes Verfahren zum Herstellen von Halbleiter- oder Flüssigkristallvorrichtungen |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6589880B2 (https=) |
| JP (1) | JP2002009056A (https=) |
| KR (1) | KR100388591B1 (https=) |
| CN (1) | CN1199257C (https=) |
| DE (1) | DE10063621A1 (https=) |
| TW (1) | TW495855B (https=) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4034164B2 (ja) | 2002-10-28 | 2008-01-16 | 富士通株式会社 | 微細パターンの作製方法及び半導体装置の製造方法 |
| JP4181853B2 (ja) | 2002-11-15 | 2008-11-19 | Nec液晶テクノロジー株式会社 | 積層膜の複合ウェットエッチング方法 |
| JP4040515B2 (ja) | 2003-03-26 | 2008-01-30 | 株式会社東芝 | マスクのセット、マスクデータ作成方法及びパターン形成方法 |
| JP2004356469A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
| US7122903B2 (en) * | 2003-10-21 | 2006-10-17 | Sharp Kabushiki Kaisha | Contact plug processing and a contact plug |
| US20060191863A1 (en) * | 2005-02-25 | 2006-08-31 | Benjamin Szu-Min Lin | Method for fabricating etch mask and patterning process using the same |
| KR100725795B1 (ko) | 2005-12-26 | 2007-06-08 | 제일모직주식회사 | 레지스트 하층막용 하드마스크 조성물 및 이를 이용한반도체 집적회로 디바이스의 제조방법 |
| JP2008091720A (ja) * | 2006-10-03 | 2008-04-17 | Toshiba Corp | 半導体装置の製造方法 |
| JP4614995B2 (ja) * | 2007-08-23 | 2011-01-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| KR100932334B1 (ko) | 2007-11-29 | 2009-12-16 | 주식회사 하이닉스반도체 | 반도체 소자의 하드 마스크 패턴 형성 방법 |
| KR100933868B1 (ko) | 2008-03-10 | 2009-12-24 | 주식회사 하이닉스반도체 | 마스크 패턴 형성 방법 |
| JP5638413B2 (ja) | 2011-02-08 | 2014-12-10 | 東京エレクトロン株式会社 | マスクパターンの形成方法 |
| US8916337B2 (en) * | 2012-02-22 | 2014-12-23 | International Business Machines Corporation | Dual hard mask lithography process |
| US9041217B1 (en) * | 2013-12-18 | 2015-05-26 | Intel Corporation | Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects |
| US9236342B2 (en) * | 2013-12-18 | 2016-01-12 | Intel Corporation | Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects |
| CN112309835B (zh) * | 2019-07-31 | 2023-11-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0394597A1 (en) * | 1989-04-28 | 1990-10-31 | International Business Machines Corporation | Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns |
| JPH05315322A (ja) * | 1992-05-12 | 1993-11-26 | Sony Corp | 配線層のテーパエッチング方法 |
| JPH05326899A (ja) | 1992-05-25 | 1993-12-10 | Sony Corp | 半導体装置およびその製造方法 |
| JPH06244156A (ja) | 1993-02-15 | 1994-09-02 | Nippon Telegr & Teleph Corp <Ntt> | パタ―ン形成法 |
| JPH06291116A (ja) | 1993-04-01 | 1994-10-18 | Nec Corp | 半導体装置の製造方法 |
| JP3246806B2 (ja) * | 1993-06-30 | 2002-01-15 | ローム株式会社 | 半導体装置の製造方法 |
| JP2614403B2 (ja) * | 1993-08-06 | 1997-05-28 | インターナショナル・ビジネス・マシーンズ・コーポレイション | テーパエッチング方法 |
| US5431770A (en) * | 1993-10-13 | 1995-07-11 | At&T Corp. | Transistor gate formation |
| KR100434133B1 (ko) * | 1995-07-14 | 2004-08-09 | 텍사스 인스트루먼츠 인코포레이티드 | 중간층리쏘그래피 |
| JPH09186166A (ja) * | 1996-01-08 | 1997-07-15 | Toshiba Corp | 半導体装置の製造方法 |
| JPH09304912A (ja) * | 1996-05-15 | 1997-11-28 | Mitsubishi Electric Corp | 位相シフトマスク、位相シフトマスク用ブランクスおよび位相シフトマスクの製造方法 |
| US6270948B1 (en) * | 1996-08-22 | 2001-08-07 | Kabushiki Kaisha Toshiba | Method of forming pattern |
| JP2815004B2 (ja) * | 1996-10-30 | 1998-10-27 | 日本電気株式会社 | 表示装置およびその製造方法 |
| JPH1126719A (ja) * | 1997-06-30 | 1999-01-29 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| JP3351716B2 (ja) * | 1997-09-11 | 2002-12-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6323132B1 (en) * | 1998-01-13 | 2001-11-27 | Applied Materials, Inc. | Etching methods for anisotropic platinum profile |
| KR20000025529A (ko) * | 1998-10-13 | 2000-05-06 | 윤종용 | 마스크 디멘션 변경에 의한 백금 식각 방법 |
| US6306560B1 (en) * | 1998-12-02 | 2001-10-23 | Advanced Micro Devices, Inc. | Ultra-thin resist and SiON/oxide hard mask for metal etch |
-
2000
- 2000-06-22 JP JP2000188160A patent/JP2002009056A/ja active Pending
- 2000-12-20 DE DE10063621A patent/DE10063621A1/de not_active Ceased
- 2000-12-28 US US09/749,834 patent/US6589880B2/en not_active Expired - Fee Related
-
2001
- 2001-02-21 TW TW090103886A patent/TW495855B/zh not_active IP Right Cessation
- 2001-02-27 KR KR10-2001-0009882A patent/KR100388591B1/ko not_active Expired - Fee Related
- 2001-02-28 CN CNB011089490A patent/CN1199257C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1199257C (zh) | 2005-04-27 |
| KR100388591B1 (ko) | 2003-06-25 |
| JP2002009056A (ja) | 2002-01-11 |
| US6589880B2 (en) | 2003-07-08 |
| KR20020000481A (ko) | 2002-01-05 |
| US20020006730A1 (en) | 2002-01-17 |
| TW495855B (en) | 2002-07-21 |
| CN1332472A (zh) | 2002-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE10063621A1 (de) | Verfahren zum Bilden feiner Muster und dieses Verfahren verwendendes Verfahren zum Herstellen von Halbleiter- oder Flüssigkristallvorrichtungen | |
| DE19526011C1 (de) | Verfahren zur Herstellung von sublithographischen Ätzmasken | |
| DE4138842C2 (de) | Gateelektrode und Verfahren zu deren Herstellung | |
| DE19834917A1 (de) | Verfahren zum Bilden von selbstausrichtenden Durchgängen in integrierten Schaltungen mit mehreren Metallebenen | |
| DE68920291T2 (de) | Verfahren zum Herstellen von leitenden Bahnen und Stützen. | |
| DE102009004550B4 (de) | Verfahren zur Bildung von Zwischenverbindungen | |
| DE19925657B4 (de) | Verfahren zum Ausbilden eines selbstpositionierenden Kontakts in einem Halbleiterbauelement | |
| DE19626039C2 (de) | Verfahren zum Herstellen einer Metalleitung | |
| DE19929239A1 (de) | Verfahren zur Herstellung von Halbleitern | |
| DE2723944A1 (de) | Anordnung aus einer strukturierten schicht und einem muster festgelegter dicke und verfahren zu ihrer herstellung | |
| DE19943175B4 (de) | Ätzverfahren und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung des Ätzverfahrens | |
| DE102007026879A1 (de) | Verfahren zum Herstellen einer Struktur auf oder in einem Substrat, Abbildungsschicht zum Erzeugen sublithographischer Strukturen, Verfahren zum Invertieren eines sublithographischen Musters, durch Herstellung einer Struktur erhältliche Einrichtung | |
| DE102004025925B4 (de) | Verfahren zum Ausbilden einer selbstausgerichteten Kontaktstruktur in einem Halbleiterbauelement unter Verwendung einer Opfermaskenschicht | |
| DE19919939B4 (de) | Verfahren zur Bildung von elektrisch leitenden Leitungen in integrierten Speicherschaltungen unter Verwendung von selbstjustierenden Silicid-Sperrschichten | |
| DE69712478T2 (de) | Eine bildumkehrtechnik zu ausbildung kleiner strukturen in integrierten schaltkreisen | |
| DE69930027T2 (de) | Metallisierungsverfahren für Halbleiter | |
| DE69615642T2 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
| DE19852256A1 (de) | Verfahren zum Ätzen von Platin | |
| DE4446850A1 (de) | Verfahren zur Herstellung eines Transistors für eine Halbleitervorrichtung | |
| DE4212494C2 (de) | Verfahren zur Herstellung einer Halbleitereinrichtung mit einer sich nach oben in der Breite verringernden Seitenwandisolierschicht und Halbleitereinrichtung | |
| DE19829864A1 (de) | Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung | |
| DE69219998T2 (de) | Verfahren zur Entfernung von Polymeren aus Sacklöchern in Halbleitervorrichtungen | |
| DE19820488A1 (de) | Herstellungsverfahren einer Halbleitervorrichtung | |
| DE10334406A1 (de) | Verfahren zur Ausbildung eines Kontaktes in einem Halbleiterprozeß | |
| DE19719909A1 (de) | Zweifaches Damaszierverfahren |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| 8131 | Rejection |