CN1902710A - 用于非易失性存储器阵列中的读取误差检测的方法、电路和系统 - Google Patents

用于非易失性存储器阵列中的读取误差检测的方法、电路和系统 Download PDF

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CN1902710A
CN1902710A CNA2004800392341A CN200480039234A CN1902710A CN 1902710 A CN1902710 A CN 1902710A CN A2004800392341 A CNA2004800392341 A CN A2004800392341A CN 200480039234 A CN200480039234 A CN 200480039234A CN 1902710 A CN1902710 A CN 1902710A
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盖伊·科亨
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Spansion Israel Ltd
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Abstract

本发明是一种用于确定将在读取被编程到给定编程状态的单元时使用的参考电压的方法、电路和系统。本发明的一些实施例涉及用于建立一组将用于操作(例如读取)NVM块或阵列中的单元的操作参考单元的系统、方法和电路。作为本发明的一部分，可以读取NVM块或阵列的单元中的至少一个子集，并且可以将在与该阵列相关的给定状态发现的单元数量与一个或多个校验和值进行比较，所述一个或多个校验和值是在单元的所述至少一个子集的编程期间获得的。根据比较的结果，可以调节与给定编程状态相关的或与相邻状态相关的读取验证阈值参考电压。

Description

用于非易失性存储器阵列中的读取误差检测 的方法、电路和系统
发明领域
本发明一般涉及非易失性存储器(“NVM”)单元领域。更具体而言，本发明涉及用于选择一个或多个参考单元的参考电压以便读取存储器单元阵列内的一个或多个存储单元的方法和系统。
发明背景
NVM单元一般采用一个或多个参考结构或单元来操作(例如，编程、读取和擦除)。一个或多个参考结构或单元中的每一个可以与正在工作的存储单元进行比较，以便确定正在工作的存储单元的条件或状态。众所周知，NVM单元的状态可以由其阈值电压来定义和确定，该阈值电压是单元开始导通电流的电压。NVM单元的阈值电压电平通常与储存在单元的电荷储存区中的电荷量有关。不同的阈值电压范围与NVM单元的不同状态相关。图1A是示出在二进制NVM单元的两种状态即擦除和编程之间的边界以及这两种状态之间的缓冲区域的曲线。
一般情况下，为了确定NVM单元是否处于特定状态，例如，擦除、编程或在多电平单元(“MLC”)的多个可能编程状态中的一个状态下编程，将该单元的阈值电平与参考结构或单元的电压相比较，所述参考结构或单元的阈值电平被设置在或者公知为处于与正在测试的特定状态相关的电压电平上。将NVM单元的阈值电压与参考单元的阈值电压进行比较通常是使用读出放大器或类似电路来完成的。用于比较NVM的阈值电压与一个或多个参考单元或结构的阈值电压以便确定NVM的单元状态的各种技术是公知的，并且可适用于本发明。目前已知的或将来要设计的用于将参考单元或结构的阈值电压电平与NVM单元的阈值电压进行比较的任何方法或电路都可适用于本发明。
当将NVM单元编程为所希望的状态时，在每个编程脉冲之后，NVM单元的阈值电压可以与具有设置在定义为“编程验证”电平的电压电平的参考阈值的参考单元进行比较。具有设置在定义为用于给定状态的“编程验证”电平的电压电平的阈值电压的参考单元可以与正在编程(即，充电)的单元的阈值电压进行比较，以便确定正在编程的单元的电荷储存区或区域是否已经被充分充电，以便将该单元设置为在所希望的状态下可以被认为是“编程”的条件下。
当读取NVM单元时，为了确定它是否处于特定状态，可以将该单元的阈值电压与具有被定义为用于特定状态的“读取”电平的参考阈值电压的参考单元的阈值电压进行比较。“读取”电平通常设置为低于“编程验证”电平并高于擦除验证电平，以便补偿在工作期间可能发生的电压漂移。如果单元的Vt高于读取参考的Vt，则将该单元的逻辑状态定义为“0”；如果比它低，则定义为“1”。
在MLC中，两个或多个编程电平可以同时存在于同一单元中，如图1B所示。在读取MLC单元以便确定该单元处于多个逻辑状态中的哪个状态的情况下，必须使用至少两个读取参考单元。在读取操作期间，必须确定MLC单元的阈值处于由两个或多个阈值电压限制的三个或多个区域中的一个区域中，其中所述两个或多个阈值电压是由读取参考单元定义的。如图1B所示。限定MLC中的给定状态的电压阈值边界通常远小于二进制NVM单元的电压阈值边界。现在参考的图1B示出了MLC的四个不同的阈值电压区域，其中每个区域与MLC的编程状态之一或与MLC的擦除状态相关。由于在MLC中，潜在阈值电压的相当固定的范围(例如3伏到9伏)需要分成几个子范围或区域，MLC中的每个子范围或区域的尺寸通常小于二进制NVM单元的区域，该二进制单元只需要两个电压阈值区域，如图1A所示。
NVM单元的电压阈值很少保持固定。阈值电压漂移是可能导致存储单元的阈值电压产生大变化的现象。这些变化可能是由于从单元的电荷储存区泄漏电荷、温度变化以及由于来自相邻NVM单元的工作的干扰引起的。现在参考的图2是示出由于漂移引起的与示例的MLC的两个编程状态相关的阈值电压(Vt)变化作为时间的函数、对于10个周期和1000个周期的曲线。如该曲线所示，电压漂移可能在各个单元上发生，并且可能在这些单元上以相关图形发生。还知道漂移的幅度和方向取决于NVM经历编程和擦除周期的次数以及MLC的编程电平。还知道单元中的偏移(Vt)可以是在向上或向下的方向上。
存储单元的阈值电压的变化可能导致状态的错误读取，并且还可能导致存储阵列中的数据破坏。电压漂移在MLC单元中尤其有问题，在MLC单元中与每个编程状态相关的Vt区域或子范围相对小于典型的二进制单元的Vt区域或子范围。
为了减少由于NVM阵列的单元的阈值电压中的漂移引起的数据损失和数据破坏，应该补偿NVM阵列中的单元的阈值电压漂移。对于给定的NVM阵列，希望提供一个或一组参考单元，其参考阈值电压从定义的验证阈值电平偏移一定值，该值涉及待读取的NVM单元所经历的实际电压漂移。完全应当理解，需要一种确定一组参考电压电平的有效和可靠的方法，这些参考电压电平可适应NVM阵列的单元以及具有确定的参考电压的已建立的参考单元的阈值电压的变化。
发明内容
本发明是一种用于确定参考电压的方法、电路和系统。本发明的一些实施例涉及用于建立将被用于操作(例如读取)NVM块或阵列中的单元的一组操作参考单元的系统、方法和电路。作为本发明的一部分，NVM块或阵列的单元中的至少一个子集可以使用两组或更多组测试参考单元中的每一个来读取，其中每组测试参考单元可产生或提供至少稍微偏离每个其它组测试参考单元的参考电压。对于用于读取NVM块的至少一个子集的每组测试参考单元，可以计算或确定读取误差率。与相对低的读取误差率相关的一组测试参考单元可以被选择作为用于操作(例如读取)NVM块或阵列中的该单元子集之外的其它单元的操作参考单元组。在另一实施例中，所选择的测试参考单元组可用于建立操作的参考单元组，其具有基本上等于所选的测试组的参考电压。
根据本发明的一些实施例，在对NVM阵列中的一组单元进行编程之前或编程期间，可以计算将被编程为与该组单元相关的一个或多个逻辑或编程状态中的每个状态的单元的数量，并且例如可以将其存储在校验和(check sum)表格中。作为本发明的一些实施例的一部分，将被编程到高达和/或低于每个逻辑或编程状态的单元数量可以被计算和/或被存储在与该组NVM单元处于相同阵列的表中或在与NVM阵列相同芯片上的存储器中。
在读取该组编程单元之后，根据本发明的一些实施例，可以将被发现为处于给定逻辑或编程状态下的单元数量与在编程期间储存的相应值(例如被编程到给定状态的单元的数量)进行比较，或者与从编程期间储存的值获得的值(例如，在给定状态或给定状态以上编程的单元数量减去被编程到相邻较高逻辑状态或其以上的单元的数量)进行比较。如果在给定状态读取的单元数量与以在编程期间确定/计算/储存的数值为基础的预期数量之间存在差异，则可以将与给定编程状态相关的读取验证参考阈值向上或向下调整，以便补偿检测的误差。根据本发明的一些实施例，相邻逻辑状态的读取验证电平也可以向上或向下移动，以便补偿在给定状态检测到的读取误差。
例如，根据本发明的一些实施例，如果在给定的编程状态下发现(例如读取)的单元数量低于预期数量，则可以减小与这个给定状态相关的读取验证参考电压，或者如果发现在给定状态以上读取的单元的数量超过预期数量，则可以升高与比给定状态高且与给定状态相邻的逻辑状态相关的读取验证参考。相反，如果在给定编程状态下发现(例如读取)的单元数量高于预期，则可以增加与这个给定状态相关的读取验证参考电压，或者如果发现在给定状态以上读取的单元数量低于预期数量，则可以降低与比给定状态高且与给定状态相邻的逻辑状态相关的读取验证参考。因此，可以选择用于一组单元的读取验证参考电压，使得在与该组相关的每个状态中发现/读取的单元数量可以基本上等于从在该组单元的编程期间计算的值读取或获得的数量，这些值可能已经被存储在校验和表格中。
根据本发明的一些实施例，校验和表格可以位于与该组NVM单元相同的芯片上，并且根据本发明的另一实施例，控制器可适于进行上述误差检测和读取验证参考值调节。校验和表格可以被存储在与该组NVM单元相同的NVM阵列中，或者被存储在位于与NVM阵列相同的芯片上的一些其它存储单元上，例如，在编程和/或读取期间由控制器使用的寄存器或缓冲器中。根据本发明的其它实施例，可以包含特殊的误差编码和检测电路且在相同芯片和被操作NVM阵列上设有控制器。
附图简述
在本说明书的结论部分中特别指出和明确要求了作为本发明的主题。但是，通过结合附图来阅读以下非限制性的详细说明可以更好地理解本发明的构造和操作方法，以及其目的、特征和优点，在附图中：
图1A是与二进制NVM单元的不同状态相关的不同阈值电压的曲线图，其中可看见编程验证和读取验证阈值电平；
图1B是各自与多电平单元(MLC)的不同编程状态的边界相关的不同阈值电压的曲线图；
图2是示出由于Vt漂移而产生的与示例的多电平单元(MLC)的每个编程状态相关的阈值电压(Vt)的测量变化作为时间的函数、对于10个周期和对于1000个周期的曲线；
图3是根据本发明的一些实施例选择将在操作NVM块或阵列时使用的一组参考单元的方法的流程图；
图4是根据本发明一些实施例与支持图3的方法的一个实施方式的NVM阵列相关的一种可能电路结构的方框图；和
图5是与用于建立和使用一组操作参考单元的NVM阵列相关的一种可能电路结构的方框图，其中所述一组操作参考单元具有基本上等于被选测试组的参考电压的参考电压；
图6是根据本发明一些实施例的与用于进行基于校验和的误差检测算法和用于根据校验和算法的结果来选择一组参考单元的NVM阵列相关的一种可能电路结构的方框图；
图7A根据本发明的一些实施例示出列出了校验和算法的基本步骤的流程图；
图7B根据本发明的一些实施例示出可使用校验和算法来调节与在给定编程状态下读取单元相关的参考电压(例如读取验证)的步骤的流程图；
图8A和8B示出根据本发明一些实施例的可被储存且用作校验和算法的一部分的校验和值的组合的两个例子。
应该了解，为了这些非限制性说明的简洁和清楚，图中所示的元件不必按比例绘制。例如，为了清楚起见，可以将有些元件的尺寸相对于其它元件进行放大。此外，应该理解，在图中可以重复参考标记，以表示相应或相似的元件。
发明的详细说明
在下面的详细说明中，为了提供本发明的全面理解，阐述了很多具体的细节。然而，本领域普通技术人员应该理解，本发明可以在没有这些具体细节的情况下实施。在其他情况下，为了避免使本发明不明确，不详细介绍公知的方法和过程。
本发明是一种用于确定参考电压的方法、电路和系统。本发明的一些实施例涉及用于建立将用于操作(例如读取)NVM块或阵列中的单元的一组操作参考单元。作为本发明的一部分，NVM块或阵列的单元中的至少一个子集可以使用两组或多组测试参考单元中的每一个来读取，其中每组测试参考单元可产生或提供至少稍微偏离每一个其它组测试参考单元的参考电压。对于用于读取NVM块的至少一个子集的每组测试参考单元，可以计算或确定读取误差率。与相对低的读取误差率相关的一组测试参考单元可以被选择作为用于在NVM块或阵列中操作(例如读取)该单元子集之外的其它单元的一组操作参考单元。在另一实施例中，所选择的测试参考单元组可用于建立(例如编程)操作的参考单元组，其具有基本上等于所选的测试组的参考电压。
现在参照图3，其是根据本发明一些实施例的选择将要在操作NVM块或阵列时使用的一组参考单元的方法步骤的流程图。作为本发明的一些实施例的一部分，对于给定的具有相关误差检测特征和与N组测试参考单元相关的NVM块或阵列，可以将组计数器“n”初始设置为1(方框310)。接着，从第一组开始的第n组测试参考单元可用于读取NVM块的至少一个子集(方框320)。
在方框320读取的数据可以用于确定与第n组测试参考单元相关的读取误差率(方框330)。根据本发明的一些实施例，NVM块的所述至少一个子集可以是NVM块的预定部分或段，其中源数据连同在编程期间得到的额外误差检测数据/代码一起被储存在NVM单元上。读取误差率可以使用各种误差率采样和/或误差检测技术来确定，例如校验位、校验和、CRC和各种其它技术。目前已知的或者将来可以想到的任何误差检测编码和/或评估技术都可适用于本发明。
一旦使用第n组测试参考单元对于NVM块的所述至少一个子集计算或确定了误差率之后，就可以记录与第n组测试参考单元相关的误差率(方框340)。然后可以将计数器“n”加1(方框350)，并且可以检查计数器，看看新的“n”是否等于N+1，一个大于测试参考单元组的总数的值(方框360)。在新的“n”小于(不等于)N+1的情况下，可以重复执行方框320-360，并因此可以确定和记录与使用每个测试参考单元组来读取NVM块的至少一个子集相关的误差率。
一旦计数器“n”等于N+1，并且已经确定了与每个测试组相关的误差率，则可以选择与相对低的(例如，最低的)读取误差率相关的参考测试单元组(方框370)。所选择的参考单元组可以用于操作NVM块或阵列上的单元(方框380)，或者可以用于建立一个操作的参考单元组，其参考阈值电压基本上对应于所选择的组的参考阈值电压(方框390)，使得所建立的操作组可以用于操作NVM阵列中的单元。
上面以建立将要在操作NVM块或阵列时使用的一组操作参考单元的方法的一个实施例为例进行了说明。应该理解的是，本发明的其它实施例也可以偏离上面的说明。所选的测试可用作操作参考组，可用于选择或编程操作组，或者可以用于调节一组可调节参考结构上的参考电平。此外，本发明的方法可以以各种实施方式来实现，包括目前已知的或将来可以想到的硬件和/或软件模块。下面将参照图4介绍根据本发明的一些实施例的建立将要在操作NVM块或阵列的单元时使用的一组操作参考单元的方法的可能实施方式的一个例子。
现在参照图4，其是结合NVM阵列400展示的一种可能实施方式的方框图。作为本发明一些实施例的一部分，用于操作NVM块或阵列400的电路401可包括控制器410、可控电压源412、读出放大器414和两组或多组测试参考单元432、434和436。每组测试参考单元432、434和436可包括两个或多个测试参考单元。每组测试参考单元432、434和436可具有至少稍微偏离每一个其它测试参考单元组的参考电压。例如，每组测试参考单元(例如432)可以是增量偏离的，使得每组可以与稍微高于与前一组测试参考单元(不包括第一组)相关的相应系列的阈值电压的一系列阈值电压相关。作为另一例子，如果第一组测试参考单元包括具有参考电压的单元；单元1＝4.2V，单元2＝5.2V，单元3＝6.2V，则第二组可包括具有参考电压偏移量的单元，使得：单元1＝4.3V，单元2＝5.3V，单元3＝6.3V，等等。
在所示实施例中，控制器410可实现计数器“n”(未示出)。然而，也可使用任何其它结构，包括但不限于：与众不同的计数器模块。控制器410可以被构成为控制可控电压源412和读出放大器414的操作。根据本发明的一些实施例，例如图3所示的实施例，控制器410开始可以将参考测试组计数器“n”设置为1。接着，控制器410可以操作可控电压源412，并使用第n组测试参考单元(最初为第一组432)来读取NVM块或阵列的单元402的至少一个子集。作为本发明的一些实施例的一部分，控制器410可指示电压源412将增加的电压脉冲施加于子集区域402中的每个存储单元并且施加于来自第n组测试参考单元(例如432)的一个或多个测试参考单元。可以例如使用读出放大器414将子集区域402中的每个存储单元的阈值电压与第n组测试参考单元(例如432)中的一个或多个测试参考单元的阈值电压进行比较。通过将这些单元的阈值电压与来自第n组测试参考单元的参考单元的阈值电压进行比较，可以读取或确定单元402的子集中的每个单元的状态。为了确定存储单元的状态，用于比较存储单元的阈值电压与一个或多个参考单元和/或结构的阈值电压的各种其它技术是公知的，并且可以根据本发明的其它实施例来实施。
控制器410可以接收从子集区域402中的NVM单元读取的数据。控制器410可以处理这些数据，并且可以确定与用于读取子集区域402中的存储单元的第n组测试参考单元相关的读取误差率。读取误差率可以使用各种误差率采样和/或误差检测技术来确定，例如，校验位、校验和、CRC和各种其它技术。NVM块400的子集区域402和/或任何其它元件和/或补充电路401，包括需要的任何附加元件，可以被构成为支持选择的误差率采样和/或误差检测技术。在所示的实施例中，子集区域402可包括支持奇偶检查误差检测的一个或多个奇偶校验位(标记为Pn)。控制器410可被构成为处理从子集区域402读取的数据并根据奇偶检查误差检测来确定读取误差率。在本发明的另一实施例中，可以包括分开的误差编码和检测电路(未示出)。
一旦计算完，控制器410可在内部或在指定的误差率表416中记录每一组测试参考单元或结构的读取误差率，该误差率表可以是NVM块或阵列的一部分。读取误差率可以以如下方式进行记录：保持每个记录的读取误差率与用于产生它的一组测试参考单元相关。
在为第n组测试参考单元建立读取误差率之后，可以指示计数器使n增加“1”。可以参考控制器410，以检查‘n’的新值是否已经超过测试参考单元组的总数。如果是，则可以由控制器410中断确定和记录与每个测试参考单元组相关的读取误差率的过程。换言之，确定和记录读取误差率的过程可以为N组测试参考单元中的每一组(例如432、434和436)重复进行。
然后控制器410可以从记录的读取误差率中选择相对低(例如最低)的读取误差率。与所选的相对低的读取误差率相关的一组测试参考单元可以被选择作为将要在操作NVM块或阵列400的单元时使用的一组操作参考单元。根据本发明的一个任选实施例，控制器410还可以确定与所选的测试组相关的一组参考电压，所述被选测试组与所选的相对低的读取误差率相关。这组参考电压还可以被记录在例如误差率表416中。可以储存这组参考电压，从而保持被储存的这组参考电压与所选的测试参考单元组(例如432)的相关性。
根据本发明的一些实施例，在控制器410确定所产生的一个以上的读取误差率是最低的情况下，其中每个读取误差率与不同的测试参考单元组相关，例如，当两个或多个相等的读取误差率同样都是最低时，可能需要附加处理来确定哪一组更可能提供较低的读取误差率。例如，为这两组或多组测试参考单元中的每一组产生且记录读取误差率的过程可以根据不同的标准或在NVM块的附加子集上重复进行。或者，可以任意选择最低读取误差率中的一个。
作为本发明的另外实施例的一部分，从多组测试参考单元(例如432、434和436)中选择被预期提供相对低的读取误差率的一组就足够了。在这种情况下，例如，在如上所述使用每一组测试参考单元读取NVM块的至少一个子集，并且产生与使用的组相关的读取误差率之后，可以检查读取误差率。在读取误差率低于预定阈值的情况下，可以选择和记录与该读取误差率相关的这组测试参考单元，并且在检查所有的测试组之前，可以中断产生和记录读取误差率的过程。根据本发明的又一些实施例，在产生的读取误差率都不低于预定阈值的情况下，可以根据上述讨论内容来选择最低误差率。
在本发明的另一实施例中，所选的测试参考单元组可用于建立具有基本上等于所选的测试组的参考电压的操作参考单元组。
现在参见图5，其是用于建立和使用具有基本上等于所选的测试组的参考电压的一组操作参考单元的NVM阵列的一种可能结构的示意图。图5所示的补充电路401可以基本上与图4所示的相似，并且可以以相似的方式工作，并附加了一组全局参考单元520和偏移电路510。
初始地，补充电路401和NVM块400可以被操作来确定与所述两组或多组测试参考单元432、434和436中的每一个相关的读取误差率，并且选择这两组或多组测试参考单元432、434和436中与相对低(例如最低)读取误差率相关的一组。接着，所选的这组测试参考单元可以用于确定该组全局参考单元520的一个或多个全局参考单元的偏移值。偏移值可以直接地或者经过控制器410输入到偏移电路510。单独的或者与可控电压源412结合的偏移电路510可以适于使来自这组全局参考单元510的全局参考单元的一个或多个参考电压偏移。在一个实施例中，偏移电路510可以构成为使全局参考单元的参考电压偏移，使得全局参考组520中的参考单元的参考电压可以基本上等于所选的测试组中的相应的参考单元。
在本发明的另一实施例中，可以通过控制器410获得与所选的测试组相关的一组参考电压。如上所述，这组参考电压可以记录在例如误差率表416中。在这种情况下，通过从表416简单地恢复相关数据就可以获得这组参考电压数据。控制器410可以指示偏移电路510根据这组参考电压来使这组全局参考单元520中的一个或多个参考单元的阈值电压偏移。在本发明的又一实施例中，控制器410可以指示偏移电路510使这组全局参考单元510中的一个或多个全局参考单元的参考电压偏移，使得这组全局参考单元510的阈值电压可以基本上等于所选的测试组的阈值电压。
根据本发明的另一些实施例，偏移电路510和这组全局参考单元520可以用一排(bank)参考单元(未示出)来代替。这排参考单元可以包括两个或多个参考单元，这排中的每个参考单元相对于这排中的其它参考单元是增加地偏移。例如，这排中的每个参考单元可具有稍微高于前一参考单元(不包括第一参考单元)的阈值电压的阈值电压。
根据本发明的一些实施例，一旦进行了选择，则所选的这组测试参考单元可以用于确定这排参考单元中的哪个参考单元将被用于建立一个操作参考单元组。从这排参考单元选择的参考单元组可以被选择成使得从这排选择的组可具有基本上等于所选的测试组的参考电压的参考电压。因此，从这排选择的这组参考单元可以提供一组具有基本上等于所选的测试组的参考电压的参考电压的操作参考单元。这组操作参考单元可以用于操作NVM阵列。
根据本发明的一些实施例，在NVM阵列中的一组单元编程之前或编程期间，可以计算将被编程到与这组单元相关的一个或多个逻辑或编程状态中的每个状态的单元的数量，并且可以将其储存在例如校验和表格中。作为本发明的一些实施例的一部分，将要被编程到高达和/或低于每个逻辑或编程状态的单元数量可以被计算和/或储存在与这组NVM单元处于相同阵列上的表格中或储存在与NVM阵列相同芯片上的存储器中的表格中。
在读取这组编程单元之后，根据本发明的一些实施例，被发现处于给定逻辑或编程状态下的单元的数量可以与编程期间储存的相应值(例如被编程到给定状态的单元数量)或者与从编程期间储存的值获得的值(例如，在给定状态或在给定状态以上被编程的单元的数量减去被编程到相邻更高的逻辑状态或其以上的单元的数量)进行比较。如果在给定状态下读取的单元数量与以在编程期间确定/计算/储存的值为基础的预期数量之间存在差异，则可以将与给定编程状态相关的读取验证参考阈值向上或向下调节，以便补偿检测到的误差。根据本发明的一些实施例，还可以将相邻逻辑状态的读取验证电平向上或向下移动，以便补偿在给定状态检测到的读取误差。
例如，根据本发明的一些实施例，如果在给定编程状态下发现(例如读取)的单元数量低于预期值，则可以减小与给定状态相关的读取验证参考电压，或者如果发现在给定状态以上读取的单元数量超过预期数量，则可以增加与比给定状态高且与给定状态相邻的逻辑状态相关的读取验证参考电压。相反，如果在给定编程状态下发现(例如读取)的单元数量高于预期值，则可以增加与给定状态相关的读取验证参考电压，或者如果发现在给定状态以上读取的单元数量低于预期数量，则可以减小与比给定状态高且与给定状态相邻的逻辑状态相关的读取验证参考电压。因此，可以选择用于一组单元的读取验证参考电压，使得在与该组相关的每个状态中发现/读取的单元数量可以基本上等于从该组单元的编程期间计算的值读取或得到的数量，这些值可能已经被储存在校验和表格中。
根据本发明的一些实施例，校验和表格可位于与这组NVM单元相同的芯片上，并且根据本发明的另一实施例，控制器可以适于进行上述误差检测和读取验证参考值调节。校验和表格可以被储存在与该组NVM单元相同的NVM阵列中，或者被储存在位于与NVM阵列相同的芯片上的一些其它存储单元上，例如，被储存在在编程和/或读取期间由控制器使用的寄存器或缓冲器中。根据本发明的其它实施例，可以包含特殊化误差代码和检测电路且在同一芯片和被操作NVM阵列上设有控制器。
现在参照图6，其示出了与NVM阵列相关的一种可能电路结构的方框图，用于进行基于校验和的误差检测算法并且用于根据校验和算法的结果选择一组参考单元。结合示出了列出根据本发明一些实施例的校验和算法的基本步骤的流程图的图7A来看图6，显示出在一定数量的NVM单元例如1000个单元的编程之前或期间，可以计算将要在与这组单元相关的每个编程状态、之上或之下编程的单元数量(方框600)。所述计算可以通过控制器410来进行，并且结果可以储存在校验和表格418中。根据本发明的一些其它的实施例，校验和表格418可以被储存在与NVM阵列相同的芯片上、直接被储存在NVM阵列上或在另一个存储器上，例如被储存在在NVM阵列的编程和/或读取期间也被控制器410使用的储存寄存器或缓冲器上。
现在参照图8A和8B，其中示出了根据本发明一些实施例的如何可以计算、储存和用作校验和算法的一部分的校验和值的两个例子。图8A示出单元的计数，使得用于一组单元的校验和值是以每个逻辑或编程状态以下的单元数量为基础的，而图8B示出单元的计数，使得用于一组单元的校验和值是以每个逻辑编程状态以上的单元数量为基础的。为了讨论的目的，编程状态可以被定义为擦除状态以外的任何逻辑状态。不论图8A和8B所示的内容，本领域普通技术人员应该知道，存在着各种方法和设置来产生用于确定被编程到与一组NVM单元相关的每个编程状态的单元数量的校验和值。
在从被编程的单元组读取单元期间，控制器410或一些其他误差检测电路(未示出)可以将读取期间在每个编程状态中计算的单元数量与在编程期间或之前储存的相应校验和值进行比较。例如，如果该组中的单元总数为1000，在第三编程状态中读取的单元数量是235，并且被储存的校验和值之一表示在第三编程状态以下被编程的单元数量是750，则可以得出应该有250个单元被编程到第三编程状态，并且由此这组的读取丢失了15个单元，这15个单元应该已经被读取为被编程到第三编程状态(方框610)。
可以响应于在步骤610期间在读取中检测到的误差来调节与每个编程状态相关的读取验证参考阈值电压(方框620)。图7B示出根据本发明一些实施例列出可以采用校验和算法来调节与在一个或多个编程状态读取单元相关的参考电压(例如读取验证)的步骤的流程图。一般地描述图7B，它示出了：如果在给定编程状态发现的单元数量超过从校验和值获得的值，则可以升高与这个给定的编程状态相关的读取验证阈值，或者可以降低与相邻更高的状态相关的读取验证参考电平。相反，如果在给定编程状态发现的单元数量低于预期数量，则可以降低与这个给定的编程状态相关的读取验证阈值，或者可以升高与下一个更高相邻的状态相关的读取验证阈值。
参照图7B，根据本发明的一些实施例，如果在给定编程状态中发现(例如读取)的单元数量低于预期值，则可以降低与这个给定状态相关的读取验证参考电压，或者，如果发现在给定状态以上读取的单元数量超过期望值，则可以升高与高于且相邻于给定状态的逻辑状态相关的读取验证参考。相反，如果在给定编程状态发现(例如读取)的单元数量高于预期，则可以增加与这个给定状态相关的读取验证参考电压，或者如果发现在给定状态以上读取的单元数量低于预期值，则可以降低与高于且相邻于给定状态的逻辑状态相关的读取验证参考。因此，可以选择用于一组单元的读取验证参考电压，使得在与该组相关的每个状态中发现/读取的单元数量可以基本上等于从在该组单元的编程期间计算的值读取的或得到的数量，所述值可以已经被储存在校验和表格中。图7B中的步骤可以作为循环过程的一部分而重复进行，直到在每个编程状态读取的单元数量基本上对应于在其它实施例中预期的单元数量为止，可以并行检查被编程到几个不同状态的单元。
尽管这里已经说明和介绍了本发明的某些特征，但是对于本领域普通技术人员来说可以想到很多修改、替换、变化和等价物。因此，应该理解，所附权利要求书旨在覆盖落入本发明的实质范围内的所有这些修改和变化。

Claims (8)

1、一种在一组NVM单元中检测读取误差的方法，所述方法包括：
在该组单元编程期间或之前，计算将被编程到、高达和/或高于与所述NVM单元相关的一组逻辑状态中的一个或多个逻辑状态的单元数量；和
将在给定状态读取的单元数量与对应于许多单元的值进行比较，根据编程期间或之前进行的所述计算，所述许多单元应该处于所述给定状态。
2、根据权利要求1的方法，其中计算包括计算将被编程到与该组单元相关的每个逻辑状态或以上的单元的数量。
3、根据权利要求1的方法，其中比较包括将在给定状态读取的单元数量与该组中被编程在或高于所述给定状态的单元的数量以及该组中被编程到或高于与所述给定状态相邻且更高的逻辑状态的单元的数量进行比较。
4、根据权利要求3的方法，还包括通过将该组中在给定状态或以上编程的单元的数量减去该组中被编程在或高于与所述给定状态相邻且更高状态的单元的数量来确定应该处于所述给定状态的单元的数量。
5、一种调节一组单元的一个或多个读取验证参考电平的方法，包括：
在该组单元的编程期间或之前，计算将被编程到、高达和/或高于与该NVM单元相关的一组逻辑状态中的一个或多个逻辑状态的单元的数量；
将在给定状态读取的单元数量与对应于许多单元的值进行比较，根据编程期间或之前进行的所述计算，所述许多单元应该处于所述给定状态；和
根据所述比较，升高或降低与所述给定状态相关的、或与相邻状态相关的读取验证电平。
6、根据权利要求5的方法，其中计算包括计算将被编程到与该组单元相关的每个逻辑状态或以上的单元的数量，比较包括将在给定状态读取的单元数量与该组中被编程在或高于所述给定状态的单元的数量以及该组中被编程到或高于与所述给定状态相邻且更高的逻辑状态的单元的数量进行比较。
7、根据权利要求6的方法，其中如果在给定逻辑状态读取的单元数量低于预期在所述给定状态的单元数量，则可以降低与所述给定状态相关的读取验证电平，或者可以升高相邻更高的状态的读取验证电平。
8、根据权利要求6的方法，其中如果在给定逻辑状态读取的单元数量大于预期在所述给定状态的单元数量，则可以升高与所述给定状态相关的读取验证电平，或者可以降低相邻更高的状态的读取验证电平。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101960533A (zh) * 2008-02-29 2011-01-26 美光科技公司 在存储器装置的编程期间的电荷损失补偿
CN101377953B (zh) * 2007-08-29 2011-08-24 旺宏电子股份有限公司 虚拟接地阵列存储器及其编程方法
CN102216999A (zh) * 2009-06-03 2011-10-12 马维尔国际贸易有限公司 闪存的参考电压最优化
CN103140894A (zh) * 2010-08-17 2013-06-05 技术研究及发展基金公司 在非易失性存储器（nvm）单元中减轻单元间耦合效应
CN104051020A (zh) * 2013-03-12 2014-09-17 旺宏电子股份有限公司 存储器装置及其操作方法
CN105632554A (zh) * 2014-11-03 2016-06-01 旺宏电子股份有限公司 存储装置的操作方法
CN109215717A (zh) * 2017-07-05 2019-01-15 北京兆易创新科技股份有限公司 Nand型浮栅存储器的读取方法及装置
CN113628658A (zh) * 2020-05-07 2021-11-09 西部数据技术公司 校准非易失性存储器读取阈值
CN113628658B (zh) * 2020-05-07 2024-07-02 西部数据技术公司 校准非易失性存储器读取阈值

Families Citing this family (271)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7372731B2 (en) * 2003-06-17 2008-05-13 Sandisk Il Ltd. Flash memories with adaptive reference voltages
JP2007534105A (ja) * 2004-04-22 2007-11-22 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子回路、データ読み出し方法、符号化回路、データワード符号化方法
US20060108667A1 (en) * 2004-11-22 2006-05-25 Macronix International Co., Ltd. Method for manufacturing a small pin on integrated circuits or other devices
US7535765B2 (en) * 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
US7220983B2 (en) * 2004-12-09 2007-05-22 Macronix International Co., Ltd. Self-aligned small contact phase-change memory method and device
US7709334B2 (en) 2005-12-09 2010-05-04 Macronix International Co., Ltd. Stacked non-volatile memory device and methods for fabricating the same
EP1686592A3 (en) * 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US7238994B2 (en) 2005-06-17 2007-07-03 Macronix International Co., Ltd. Thin film plate phase change ram circuit and manufacturing method
US7514367B2 (en) * 2005-06-17 2009-04-07 Macronix International Co., Ltd. Method for manufacturing a narrow structure on an integrated circuit
US7321130B2 (en) * 2005-06-17 2008-01-22 Macronix International Co., Ltd. Thin film fuse phase change RAM and manufacturing method
US8237140B2 (en) * 2005-06-17 2012-08-07 Macronix International Co., Ltd. Self-aligned, embedded phase change RAM
US7534647B2 (en) 2005-06-17 2009-05-19 Macronix International Co., Ltd. Damascene phase change RAM and manufacturing method
US7696503B2 (en) 2005-06-17 2010-04-13 Macronix International Co., Ltd. Multi-level memory cell having phase change element and asymmetrical thermal boundary
US7598512B2 (en) * 2005-06-17 2009-10-06 Macronix International Co., Ltd. Thin film fuse phase change cell with thermal isolation layer and manufacturing method
US7447077B2 (en) * 2005-08-05 2008-11-04 Halo Lsi, Inc. Referencing scheme for trap memory
US7397060B2 (en) 2005-11-14 2008-07-08 Macronix International Co., Ltd. Pipe shaped phase change memory
US7635855B2 (en) * 2005-11-15 2009-12-22 Macronix International Co., Ltd. I-shaped phase change memory cell
US7394088B2 (en) * 2005-11-15 2008-07-01 Macronix International Co., Ltd. Thermally contained/insulated phase change memory device and method (combined)
US7786460B2 (en) * 2005-11-15 2010-08-31 Macronix International Co., Ltd. Phase change memory device and manufacturing method
US7414258B2 (en) 2005-11-16 2008-08-19 Macronix International Co., Ltd. Spacer electrode small pin phase change memory RAM and manufacturing method
TWI318003B (en) * 2005-11-21 2009-12-01 Macronix Int Co Ltd Air cell thermal isolation for a memory array formed of a programmable resistive material
US7449710B2 (en) 2005-11-21 2008-11-11 Macronix International Co., Ltd. Vacuum jacket for phase change memory element
US7829876B2 (en) * 2005-11-21 2010-11-09 Macronix International Co., Ltd. Vacuum cell thermal isolation for a phase change memory device
US7479649B2 (en) * 2005-11-21 2009-01-20 Macronix International Co., Ltd. Vacuum jacketed electrode for phase change memory element
US7599217B2 (en) * 2005-11-22 2009-10-06 Macronix International Co., Ltd. Memory cell device and manufacturing method
US7688619B2 (en) 2005-11-28 2010-03-30 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7459717B2 (en) * 2005-11-28 2008-12-02 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7521364B2 (en) * 2005-12-02 2009-04-21 Macronix Internation Co., Ltd. Surface topology improvement method for plug surface areas
US7605079B2 (en) * 2005-12-05 2009-10-20 Macronix International Co., Ltd. Manufacturing method for phase change RAM with electrode layer process
US7642539B2 (en) * 2005-12-13 2010-01-05 Macronix International Co., Ltd. Thin film fuse phase change cell with thermal isolation pad and manufacturing method
US7531825B2 (en) * 2005-12-27 2009-05-12 Macronix International Co., Ltd. Method for forming self-aligned thermal isolation cell for a variable resistance memory array
US8062833B2 (en) 2005-12-30 2011-11-22 Macronix International Co., Ltd. Chalcogenide layer etching method
US20070158632A1 (en) * 2006-01-09 2007-07-12 Macronix International Co., Ltd. Method for Fabricating a Pillar-Shaped Phase Change Memory Element
US7595218B2 (en) * 2006-01-09 2009-09-29 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7741636B2 (en) 2006-01-09 2010-06-22 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7560337B2 (en) * 2006-01-09 2009-07-14 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7742339B2 (en) * 2006-01-10 2010-06-22 Saifun Semiconductors Ltd. Rd algorithm improvement for NROM technology
US7825396B2 (en) * 2006-01-11 2010-11-02 Macronix International Co., Ltd. Self-align planerized bottom electrode phase change memory and manufacturing method
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7432206B2 (en) * 2006-01-24 2008-10-07 Macronix International Co., Ltd. Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram
US7456421B2 (en) * 2006-01-30 2008-11-25 Macronix International Co., Ltd. Vertical side wall active pin structures in a phase change memory and manufacturing methods
US7956358B2 (en) * 2006-02-07 2011-06-07 Macronix International Co., Ltd. I-shaped phase change memory cell with thermal isolation
US7910907B2 (en) 2006-03-15 2011-03-22 Macronix International Co., Ltd. Manufacturing method for pipe-shaped electrode phase change memory
US7554144B2 (en) 2006-04-17 2009-06-30 Macronix International Co., Ltd. Memory device and manufacturing method
US7928421B2 (en) 2006-04-21 2011-04-19 Macronix International Co., Ltd. Phase change memory cell with vacuum spacer
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US8129706B2 (en) * 2006-05-05 2012-03-06 Macronix International Co., Ltd. Structures and methods of a bistable resistive random access memory
US7471562B2 (en) * 2006-05-08 2008-12-30 Macronix International Co., Ltd. Method and apparatus for accessing nonvolatile memory with read error by changing read reference
US7773421B2 (en) * 2006-05-08 2010-08-10 Macronix International Co., Ltd. Method and apparatus for accessing memory with read error by changing comparison
US8077516B2 (en) * 2006-05-08 2011-12-13 Macronix International Co., Ltd. Method and apparatus for accessing memory with read error by changing comparison
US7608848B2 (en) * 2006-05-09 2009-10-27 Macronix International Co., Ltd. Bridge resistance random access memory device with a singular contact structure
US8239735B2 (en) * 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
US7697326B2 (en) * 2006-05-12 2010-04-13 Anobit Technologies Ltd. Reducing programming error in memory devices
CN103280239B (zh) 2006-05-12 2016-04-06 苹果公司 存储设备中的失真估计和消除
WO2007132457A2 (en) * 2006-05-12 2007-11-22 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US7820997B2 (en) 2006-05-30 2010-10-26 Macronix International Co., Ltd. Resistor random access memory cell with reduced active area and reduced contact areas
US7732800B2 (en) * 2006-05-30 2010-06-08 Macronix International Co., Ltd. Resistor random access memory cell with L-shaped electrode
US7696506B2 (en) 2006-06-27 2010-04-13 Macronix International Co., Ltd. Memory cell with memory material insulation and manufacturing method
US7785920B2 (en) * 2006-07-12 2010-08-31 Macronix International Co., Ltd. Method for making a pillar-type phase change memory element
US7442603B2 (en) * 2006-08-16 2008-10-28 Macronix International Co., Ltd. Self-aligned structure and method for confining a melting point in a resistor random access memory
US7567461B2 (en) * 2006-08-18 2009-07-28 Micron Technology, Inc. Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
WO2008026203A2 (en) 2006-08-27 2008-03-06 Anobit Technologies Estimation of non-linear distortion in memory devices
US7772581B2 (en) * 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
US8264884B2 (en) * 2006-09-12 2012-09-11 Spansion Israel Ltd Methods, circuits and systems for reading non-volatile memory cells
WO2008039692A2 (en) * 2006-09-27 2008-04-03 Sandisk Corporation Memory with cell population distribution assisted read margining
US7504653B2 (en) * 2006-10-04 2009-03-17 Macronix International Co., Ltd. Memory cell device with circumferentially-extending memory element
US7510929B2 (en) * 2006-10-18 2009-03-31 Macronix International Co., Ltd. Method for making memory cell device
US20080094885A1 (en) * 2006-10-24 2008-04-24 Macronix International Co., Ltd. Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States
US7527985B2 (en) * 2006-10-24 2009-05-05 Macronix International Co., Ltd. Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas
US7863655B2 (en) * 2006-10-24 2011-01-04 Macronix International Co., Ltd. Phase change memory cells with dual access devices
US7388771B2 (en) 2006-10-24 2008-06-17 Macronix International Co., Ltd. Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
JP5177991B2 (ja) * 2006-10-25 2013-04-10 株式会社東芝 不揮発性半導体記憶装置
WO2008053472A2 (en) 2006-10-30 2008-05-08 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7821826B2 (en) 2006-10-30 2010-10-26 Anobit Technologies, Ltd. Memory cell readout using successive approximation
TWI307100B (en) 2006-11-07 2009-03-01 Macronix Int Co Ltd Memory and method for reading error checking thereof
US8067762B2 (en) 2006-11-16 2011-11-29 Macronix International Co., Ltd. Resistance random access memory structure for enhanced retention
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US8151163B2 (en) * 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US7476587B2 (en) * 2006-12-06 2009-01-13 Macronix International Co., Ltd. Method for making a self-converged memory material element for memory cell
US7473576B2 (en) * 2006-12-06 2009-01-06 Macronix International Co., Ltd. Method for making a self-converged void and bottom electrode for memory cell
US7682868B2 (en) 2006-12-06 2010-03-23 Macronix International Co., Ltd. Method for making a keyhole opening during the manufacture of a memory cell
US20080137400A1 (en) * 2006-12-06 2008-06-12 Macronix International Co., Ltd. Phase Change Memory Cell with Thermal Barrier and Method for Fabricating the Same
US7697316B2 (en) 2006-12-07 2010-04-13 Macronix International Co., Ltd. Multi-level cell resistance random access memory with metal oxides
US7903447B2 (en) * 2006-12-13 2011-03-08 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on programmable resistive memory cell
US8344347B2 (en) * 2006-12-15 2013-01-01 Macronix International Co., Ltd. Multi-layer electrode structure
US7593263B2 (en) * 2006-12-17 2009-09-22 Anobit Technologies Ltd. Memory device with reduced reading latency
US7900102B2 (en) * 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7394698B1 (en) * 2006-12-28 2008-07-01 Macronix International Co., Ltd. Method and apparatus for adjusting a read reference level under dynamic power conditions
US7718989B2 (en) * 2006-12-28 2010-05-18 Macronix International Co., Ltd. Resistor random access memory cell device
US7515461B2 (en) * 2007-01-05 2009-04-07 Macronix International Co., Ltd. Current compliant sensing architecture for multilevel phase change memory
US7433226B2 (en) * 2007-01-09 2008-10-07 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on multiple programmable resistive memory cell
US7751240B2 (en) * 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US8151166B2 (en) * 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US7663135B2 (en) 2007-01-31 2010-02-16 Macronix International Co., Ltd. Memory cell having a side electrode contact
US7619311B2 (en) * 2007-02-02 2009-11-17 Macronix International Co., Ltd. Memory cell device with coplanar electrode surface and method
US7701759B2 (en) * 2007-02-05 2010-04-20 Macronix International Co., Ltd. Memory cell device and programming methods
US7483292B2 (en) * 2007-02-07 2009-01-27 Macronix International Co., Ltd. Memory cell with separate read and program paths
US7463512B2 (en) * 2007-02-08 2008-12-09 Macronix International Co., Ltd. Memory element with reduced-current phase change element
US8138028B2 (en) * 2007-02-12 2012-03-20 Macronix International Co., Ltd Method for manufacturing a phase change memory device with pillar bottom electrode
US20080192544A1 (en) * 2007-02-13 2008-08-14 Amit Berman Error correction coding techniques for non-volatile memory
US7884343B2 (en) * 2007-02-14 2011-02-08 Macronix International Co., Ltd. Phase change memory cell with filled sidewall memory element and method for fabricating the same
US7619237B2 (en) * 2007-02-21 2009-11-17 Macronix International Co., Ltd. Programmable resistive memory cell with self-forming gap
US8008643B2 (en) * 2007-02-21 2011-08-30 Macronix International Co., Ltd. Phase change memory cell with heater and method for fabricating the same
KR100865830B1 (ko) * 2007-02-22 2008-10-28 주식회사 하이닉스반도체 메모리 소자의 독출 방법
US7956344B2 (en) * 2007-02-27 2011-06-07 Macronix International Co., Ltd. Memory cell with memory element contacting ring-shaped upper end of bottom electrode
WO2008111058A2 (en) * 2007-03-12 2008-09-18 Anobit Technologies Ltd. Adaptive estimation of memory cell read thresholds
KR100907218B1 (ko) * 2007-03-28 2009-07-10 삼성전자주식회사 읽기 레벨 제어 장치 및 그 방법
US7786461B2 (en) 2007-04-03 2010-08-31 Macronix International Co., Ltd. Memory structure with reduced-size memory element between memory material portions
US8610098B2 (en) * 2007-04-06 2013-12-17 Macronix International Co., Ltd. Phase change memory bridge cell with diode isolation device
US7755076B2 (en) 2007-04-17 2010-07-13 Macronix International Co., Ltd. 4F2 self align side wall active phase change memory
US8001320B2 (en) * 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
WO2008139441A2 (en) 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8234545B2 (en) * 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
WO2008140171A1 (en) * 2007-05-14 2008-11-20 Samsung Electronics Co., Ltd. Apparatus for reading data and method using the same
US8513637B2 (en) * 2007-07-13 2013-08-20 Macronix International Co., Ltd. 4F2 self align fin bottom electrodes FET drive phase change memory
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US7777215B2 (en) 2007-07-20 2010-08-17 Macronix International Co., Ltd. Resistive memory structure with buffer layer
US7884342B2 (en) * 2007-07-31 2011-02-08 Macronix International Co., Ltd. Phase change memory bridge cell
US7729161B2 (en) * 2007-08-02 2010-06-01 Macronix International Co., Ltd. Phase change memory with dual word lines and source lines and method of operating same
US9018615B2 (en) * 2007-08-03 2015-04-28 Macronix International Co., Ltd. Resistor random access memory structure having a defined small area of electrical contact
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US7642125B2 (en) * 2007-09-14 2010-01-05 Macronix International Co., Ltd. Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing
US8178386B2 (en) 2007-09-14 2012-05-15 Macronix International Co., Ltd. Phase change memory cell array with self-converged bottom electrode and method for manufacturing
US7864588B2 (en) * 2007-09-17 2011-01-04 Spansion Israel Ltd. Minimizing read disturb in an array flash cell
US8098525B2 (en) * 2007-09-17 2012-01-17 Spansion Israel Ltd Pre-charge sensing scheme for non-volatile memory (NVM)
US7864606B2 (en) * 2007-09-18 2011-01-04 Spansion Israel Ltd Method, device and system for regulating access to an integrated circuit (IC) device
US8174905B2 (en) * 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US7551473B2 (en) * 2007-10-12 2009-06-23 Macronix International Co., Ltd. Programmable resistive memory with diode structure
US8068360B2 (en) * 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
WO2009050703A2 (en) * 2007-10-19 2009-04-23 Anobit Technologies Data storage in analog memory cell arrays having erase failures
US7919766B2 (en) 2007-10-22 2011-04-05 Macronix International Co., Ltd. Method for making self aligning pillar memory cell device
US20090109755A1 (en) * 2007-10-24 2009-04-30 Mori Edan Neighbor block refresh for non-volatile memory
US20090150595A1 (en) * 2007-10-24 2009-06-11 Avi Lavan Balanced programming rate for memory cells
US8120960B2 (en) * 2007-11-07 2012-02-21 Spansion Israel Ltd. Method and apparatus for accessing a non-volatile memory array comprising unidirectional current flowing multiplexers
KR101509836B1 (ko) * 2007-11-13 2015-04-06 애플 인크. 멀티 유닛 메모리 디바이스에서의 메모리 유닛의 최적화된 선택
US7804083B2 (en) * 2007-11-14 2010-09-28 Macronix International Co., Ltd. Phase change memory cell including a thermal protect bottom electrode and manufacturing methods
US7945825B2 (en) * 2007-11-25 2011-05-17 Spansion Isreal, Ltd Recovery while programming non-volatile memory (NVM)
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US7646631B2 (en) * 2007-12-07 2010-01-12 Macronix International Co., Ltd. Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods
US8209588B2 (en) * 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) * 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
KR101436505B1 (ko) * 2008-01-03 2014-09-02 삼성전자주식회사 메모리 장치
US7879643B2 (en) * 2008-01-18 2011-02-01 Macronix International Co., Ltd. Memory cell with memory element contacting an inverted T-shaped bottom electrode
KR101368694B1 (ko) 2008-01-22 2014-03-03 삼성전자주식회사 메모리 프로그래밍 장치 및 방법
US7879645B2 (en) * 2008-01-28 2011-02-01 Macronix International Co., Ltd. Fill-in etching free pore device
US8158965B2 (en) 2008-02-05 2012-04-17 Macronix International Co., Ltd. Heating center PCRAM structure and methods for making
US8156398B2 (en) * 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) * 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US7929363B1 (en) * 2008-02-26 2011-04-19 Cypress Semiconductor Corporation Memory test and setup method
US8230300B2 (en) * 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8059457B2 (en) * 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8084842B2 (en) 2008-03-25 2011-12-27 Macronix International Co., Ltd. Thermally stabilized electrode structure
US8030634B2 (en) 2008-03-31 2011-10-04 Macronix International Co., Ltd. Memory array with diode driver and method for fabricating the same
US7825398B2 (en) 2008-04-07 2010-11-02 Macronix International Co., Ltd. Memory cell having improved mechanical stability
US7791057B2 (en) * 2008-04-22 2010-09-07 Macronix International Co., Ltd. Memory cell having a buried phase change region and method for fabricating the same
US8077505B2 (en) * 2008-05-07 2011-12-13 Macronix International Co., Ltd. Bipolar switching of phase change device
US7701750B2 (en) 2008-05-08 2010-04-20 Macronix International Co., Ltd. Phase change device having two or more substantial amorphous regions in high resistance state
KR101423052B1 (ko) * 2008-06-12 2014-07-25 삼성전자주식회사 메모리 장치 및 읽기 레벨 제어 방법
US8415651B2 (en) * 2008-06-12 2013-04-09 Macronix International Co., Ltd. Phase change memory cell having top and bottom sidewall contacts
US8134857B2 (en) * 2008-06-27 2012-03-13 Macronix International Co., Ltd. Methods for high speed reading operation of phase change memory and device employing same
US8458536B2 (en) 2008-07-17 2013-06-04 Marvell World Trade Ltd. Data recovery in solid state memory devices
US7932506B2 (en) 2008-07-22 2011-04-26 Macronix International Co., Ltd. Fully self-aligned pore-type memory cell having diode access device
US20100019215A1 (en) * 2008-07-22 2010-01-28 Macronix International Co., Ltd. Mushroom type memory cell having self-aligned bottom electrode and diode access device
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US8498151B1 (en) 2008-08-05 2013-07-30 Apple Inc. Data storage in analog memory cells using modified pass voltages
US7903457B2 (en) * 2008-08-19 2011-03-08 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US7719913B2 (en) 2008-09-12 2010-05-18 Macronix International Co., Ltd. Sensing circuit for PCRAM applications
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8324605B2 (en) * 2008-10-02 2012-12-04 Macronix International Co., Ltd. Dielectric mesh isolated phase change structure for phase change memory
US7897954B2 (en) * 2008-10-10 2011-03-01 Macronix International Co., Ltd. Dielectric-sandwiched pillar memory device
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8036014B2 (en) * 2008-11-06 2011-10-11 Macronix International Co., Ltd. Phase change memory program method without over-reset
US8664689B2 (en) 2008-11-07 2014-03-04 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
US8907316B2 (en) * 2008-11-07 2014-12-09 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions
US8208304B2 (en) * 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US7869270B2 (en) 2008-12-29 2011-01-11 Macronix International Co., Ltd. Set algorithm for phase change memory cell
US8248831B2 (en) * 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8397131B1 (en) 2008-12-31 2013-03-12 Apple Inc. Efficient readout schemes for analog memory cell devices
US8089137B2 (en) * 2009-01-07 2012-01-03 Macronix International Co., Ltd. Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method
US8107283B2 (en) * 2009-01-12 2012-01-31 Macronix International Co., Ltd. Method for setting PCRAM devices
US8030635B2 (en) 2009-01-13 2011-10-04 Macronix International Co., Ltd. Polysilicon plug bipolar transistor for phase change memory
US8064247B2 (en) 2009-01-14 2011-11-22 Macronix International Co., Ltd. Rewritable memory device based on segregation/re-absorption
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8933536B2 (en) 2009-01-22 2015-01-13 Macronix International Co., Ltd. Polysilicon pillar bipolar transistor with self-aligned memory element
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8832354B2 (en) * 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8084760B2 (en) 2009-04-20 2011-12-27 Macronix International Co., Ltd. Ring-shaped electrode and manufacturing method for same
US8173987B2 (en) * 2009-04-27 2012-05-08 Macronix International Co., Ltd. Integrated circuit 3D phase change memory array and manufacturing method
US8097871B2 (en) 2009-04-30 2012-01-17 Macronix International Co., Ltd. Low operational current phase change memory structures
US8351263B2 (en) * 2009-05-12 2013-01-08 Infinite Memory Ltd. Method circuit and system for operating an array of non-volatile memory (“NVM”) cells and a corresponding NVM device
US7933139B2 (en) * 2009-05-15 2011-04-26 Macronix International Co., Ltd. One-transistor, one-resistor, one-capacitor phase change memory
US7968876B2 (en) 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US8350316B2 (en) 2009-05-22 2013-01-08 Macronix International Co., Ltd. Phase change memory cells having vertical channel access transistor and memory plane
US8809829B2 (en) * 2009-06-15 2014-08-19 Macronix International Co., Ltd. Phase change memory having stabilized microstructure and manufacturing method
US8406033B2 (en) 2009-06-22 2013-03-26 Macronix International Co., Ltd. Memory device and method for sensing and fixing margin cells
US8238149B2 (en) 2009-06-25 2012-08-07 Macronix International Co., Ltd. Methods and apparatus for reducing defect bits in phase change memory
US8363463B2 (en) 2009-06-25 2013-01-29 Macronix International Co., Ltd. Phase change memory having one or more non-constant doping profiles
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US7894254B2 (en) 2009-07-15 2011-02-22 Macronix International Co., Ltd. Refresh circuitry for phase change memory
US8198619B2 (en) 2009-07-15 2012-06-12 Macronix International Co., Ltd. Phase change memory cell structure
US8407564B2 (en) * 2009-07-15 2013-03-26 Intel Corporation Prediction and cancellation of systematic noise sources in non-volatile memory
US8110822B2 (en) 2009-07-15 2012-02-07 Macronix International Co., Ltd. Thermal protect PCRAM structure and methods for making
US8064248B2 (en) 2009-09-17 2011-11-22 Macronix International Co., Ltd. 2T2R-1T1R mix mode phase change memory array
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8178387B2 (en) 2009-10-23 2012-05-15 Macronix International Co., Ltd. Methods for reducing recrystallization time for a phase change material
JP2010055746A (ja) * 2009-12-07 2010-03-11 Toshiba Corp 記憶媒体再生装置、記憶媒体再生方法および記憶媒体再生プログラム
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8351258B1 (en) * 2010-01-22 2013-01-08 Marvell International Ltd. Adapting read reference voltage in flash memory device
KR101655306B1 (ko) * 2010-02-24 2016-09-07 삼성전자주식회사 메모리 시스템 및 그것의 액세스 방법
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8729521B2 (en) 2010-05-12 2014-05-20 Macronix International Co., Ltd. Self aligned fin-type programmable memory cell
US8310864B2 (en) 2010-06-15 2012-11-13 Macronix International Co., Ltd. Self-aligned bit line under word line memory array
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US8395935B2 (en) 2010-10-06 2013-03-12 Macronix International Co., Ltd. Cross-point self-aligned reduced cell size phase change memory
US8497705B2 (en) 2010-11-09 2013-07-30 Macronix International Co., Ltd. Phase change device for interconnection of programmable logic device
US8467238B2 (en) 2010-11-15 2013-06-18 Macronix International Co., Ltd. Dynamic pulse operation for phase change memory
JP2011238346A (ja) * 2011-06-16 2011-11-24 Sandisk Il Ltd フラッシュメモリ内のエラーから復旧するための方法
US8987700B2 (en) 2011-12-02 2015-03-24 Macronix International Co., Ltd. Thermally confined electrode for programmable resistance memory
US9208022B2 (en) * 2012-03-29 2015-12-08 Intel Corporation Techniques for adaptive moving read references for memory cell read error recovery
KR20160062214A (ko) * 2012-03-29 2016-06-01 인텔 코포레이션 메모리 셀을 위한 적응적 판독 기준 이동
US9299459B2 (en) 2012-09-07 2016-03-29 Macronix International Co., Ltd. Method and apparatus of measuring error correction data for memory
KR20140045168A (ko) 2012-10-08 2014-04-16 삼성전자주식회사 불휘발성 메모리 장치, 메모리 시스템 및 불휘발성 메모리 장치의 동작방법
KR20140072637A (ko) * 2012-12-05 2014-06-13 삼성전자주식회사 비휘발성 메모리 장치 및 메모리 컨트롤러의 동작 방법
US9076545B2 (en) 2013-01-17 2015-07-07 Sandisk Tecnologies Inc. Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution
US9813080B1 (en) 2013-03-05 2017-11-07 Microsemi Solutions (U.S.), Inc. Layer specific LDPC decoder
US10230396B1 (en) 2013-03-05 2019-03-12 Microsemi Solutions (Us), Inc. Method and apparatus for layer-specific LDPC decoding
US9136015B2 (en) 2013-04-24 2015-09-15 Apple Inc. Threshold adjustment using data value balancing in analog memory device
JP2014225310A (ja) * 2013-05-16 2014-12-04 株式会社東芝 不揮発性半導体記憶装置
US10319460B2 (en) * 2013-08-14 2019-06-11 Infineon Technologies Ag Systems and methods utilizing a flexible read reference for a dynamic read window
TWI549229B (zh) 2014-01-24 2016-09-11 旺宏電子股份有限公司 應用於系統單晶片之記憶體裝置內的多相變化材料
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9159412B1 (en) 2014-07-15 2015-10-13 Macronix International Co., Ltd. Staggered write and verify for phase change memory
US10332613B1 (en) 2015-05-18 2019-06-25 Microsemi Solutions (Us), Inc. Nonvolatile memory system with retention monitor
US9672906B2 (en) 2015-06-19 2017-06-06 Macronix International Co., Ltd. Phase change memory with inter-granular switching
US9799405B1 (en) 2015-07-29 2017-10-24 Ip Gem Group, Llc Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
KR20170058066A (ko) * 2015-11-18 2017-05-26 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US9886214B2 (en) 2015-12-11 2018-02-06 Ip Gem Group, Llc Nonvolatile memory system with erase suspend circuit and method for erase suspend management
US9747965B2 (en) * 2015-12-28 2017-08-29 Headway Technologies, Inc. Adaptive reference scheme for magnetic memory applications
US9892794B2 (en) 2016-01-04 2018-02-13 Ip Gem Group, Llc Method and apparatus with program suspend using test mode
US9899092B2 (en) 2016-01-27 2018-02-20 Ip Gem Group, Llc Nonvolatile memory system with program step manager and method for program step management
US10291263B2 (en) 2016-07-28 2019-05-14 Ip Gem Group, Llc Auto-learning log likelihood ratio
US10157677B2 (en) 2016-07-28 2018-12-18 Ip Gem Group, Llc Background reference positioning and local reference positioning using threshold voltage shift read
US10236915B2 (en) 2016-07-29 2019-03-19 Microsemi Solutions (U.S.), Inc. Variable T BCH encoding
US10269422B2 (en) * 2017-09-08 2019-04-23 Cnex Labs, Inc. Storage system with data reliability mechanism and method of operation thereof
US10347317B2 (en) 2017-10-05 2019-07-09 Gyrfalcon Technology Inc. Method of self-testing and reusing of reference cells in a memory architecture
US10733047B2 (en) * 2018-09-28 2020-08-04 Sandisk Technologies Llc Hard and soft bit data from single read
US10658047B1 (en) 2018-10-31 2020-05-19 Micron Technology, Inc. Implementing sticky read using error control success rate associated with a memory sub-system
US10756849B2 (en) 2019-01-21 2020-08-25 Apple Inc. Self referenced single-ended chip to chip communication
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory
US11972823B2 (en) * 2022-09-11 2024-04-30 Apple Inc. Mitigation of transistor reliability degradation within memory circuits

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342102A (en) 1980-06-18 1982-07-27 Signetics Corporation Semiconductor memory array
US4389705A (en) 1981-08-21 1983-06-21 Mostek Corporation Semiconductor memory circuit with depletion data transfer transistor
US4388705A (en) 1981-10-01 1983-06-14 Mostek Corporation Semiconductor memory circuit
US4527257A (en) 1982-08-25 1985-07-02 Westinghouse Electric Corp. Common memory gate non-volatile transistor memory
US4667217A (en) 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
US5268870A (en) 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US5027321A (en) 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
EP0461904A3 (en) 1990-06-14 1992-09-09 Creative Integrated Systems, Inc. An improved semiconductor read-only vlsi memory
KR920006991A (ko) 1990-09-25 1992-04-28 김광호 반도체메모리 장치의 고전압발생회로
JP2987193B2 (ja) 1990-11-20 1999-12-06 富士通株式会社 半導体記憶装置
US5218569A (en) 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
US6002614A (en) 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5142496A (en) 1991-06-03 1992-08-25 Advanced Micro Devices, Inc. Method for measuring VT 's less than zero without applying negative voltages
US5245572A (en) 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
JP2965415B2 (ja) 1991-08-27 1999-10-18 松下電器産業株式会社 半導体記憶装置
KR960013022B1 (ko) 1991-09-11 1996-09-25 가와사끼 세이데쯔 가부시끼가이샤 반도체 집적회로
JP3358663B2 (ja) 1991-10-25 2002-12-24 ローム株式会社 半導体記憶装置およびその記憶情報読出方法
JP2564067B2 (ja) 1992-01-09 1996-12-18 株式会社東芝 センス回路を有する読み出し出力回路
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
JPH05290584A (ja) 1992-04-08 1993-11-05 Nec Corp 半導体記憶装置
US5657332A (en) 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
JP2904645B2 (ja) * 1992-05-28 1999-06-14 株式会社東芝 不揮発性半導体メモリ
US5289412A (en) 1992-06-19 1994-02-22 Intel Corporation High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories
US5450341A (en) 1992-08-31 1995-09-12 Nippon Steel Corporation Non-volatile semiconductor memory device having memory cells, each for at least three different data writable thereinto selectively and a method of using the same
US5450354A (en) 1992-08-31 1995-09-12 Nippon Steel Corporation Non-volatile semiconductor memory device detachable deterioration of memory cells
US5412238A (en) 1992-09-08 1995-05-02 National Semiconductor Corporation Source-coupling, split-gate, virtual ground flash EEPROM array
US5418743A (en) 1992-12-07 1995-05-23 Nippon Steel Corporation Method of writing into non-volatile semiconductor memory
US5335198A (en) 1993-05-06 1994-08-02 Advanced Micro Devices, Inc. Flash EEPROM array with high endurance
US5463586A (en) 1993-05-28 1995-10-31 Macronix International Co., Ltd. Erase and program verification circuit for non-volatile memory
US5477499A (en) 1993-10-13 1995-12-19 Advanced Micro Devices, Inc. Memory architecture for a three volt flash EEPROM
US5828601A (en) 1993-12-01 1998-10-27 Advanced Micro Devices, Inc. Programmed reference
JP3076185B2 (ja) 1993-12-07 2000-08-14 日本電気株式会社 半導体メモリ装置及びその検査方法
EP0678871B1 (en) 1994-03-22 2000-05-31 STMicroelectronics S.r.l. Memory array cell reading device
US5568085A (en) 1994-05-16 1996-10-22 Waferscale Integration Inc. Unit for stabilizing voltage on a capacitive node
US5508968A (en) 1994-08-12 1996-04-16 International Business Machines Corporation Dynamic random access memory persistent page implemented as processor register sets
US5822256A (en) 1994-09-06 1998-10-13 Intel Corporation Method and circuitry for usage of partially functional nonvolatile memory
US5583808A (en) 1994-09-16 1996-12-10 National Semiconductor Corporation EPROM array segmented for high performance and method for controlling same
US5694356A (en) 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5537358A (en) 1994-12-06 1996-07-16 National Semiconductor Corporation Flash memory having adaptive sensing and method
US6353554B1 (en) 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
EP0740307B1 (en) 1995-04-28 2001-12-12 STMicroelectronics S.r.l. Sense amplifier circuit for semiconductor memory devices
KR100187656B1 (ko) 1995-05-16 1999-06-01 김주용 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법
AU6185196A (en) 1995-07-03 1997-02-05 Elvira Gulerson Method of fabricating a fast programming flash e2prm cell
DE69514790T2 (de) 1995-07-14 2000-08-03 St Microelectronics Srl Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle
US5633603A (en) 1995-12-26 1997-05-27 Hyundai Electronics Industries Co., Ltd. Data output buffer using pass transistors biased with a reference voltage and a precharged data input
US5748534A (en) 1996-03-26 1998-05-05 Invox Technology Feedback loop for reading threshold voltage
US5777923A (en) 1996-06-17 1998-07-07 Aplus Integrated Circuits, Inc. Flash memory read/write controller
US5712815A (en) 1996-04-22 1998-01-27 Advanced Micro Devices, Inc. Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
US5847441A (en) 1996-05-10 1998-12-08 Micron Technology, Inc. Semiconductor junction antifuse circuit
WO2004090908A1 (ja) 1996-06-11 2004-10-21 Nobuyoshi Takeuchi ベリファイ機能を有する不揮発性記憶装置
EP0907954B1 (en) * 1996-06-24 2000-06-07 Advanced Micro Devices, Inc. A method for a multiple bits-per-cell flash eeprom with page mode program and read
KR100265574B1 (ko) 1996-06-29 2000-09-15 김영환 반도체 메모리장치의 감지증폭기
US6381670B1 (en) * 1997-01-07 2002-04-30 Aplus Flash Technology, Inc. Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation
US5812456A (en) 1996-10-01 1998-09-22 Microchip Technology Incorporated Switched ground read for EPROM memory array
US5717632A (en) 1996-11-27 1998-02-10 Advanced Micro Devices, Inc. Apparatus and method for multiple-level storage in non-volatile memories
JP3532725B2 (ja) 1997-02-27 2004-05-31 株式会社東芝 半導体集積回路
JP3920415B2 (ja) 1997-03-31 2007-05-30 三洋電機株式会社 不揮発性半導体メモリ装置
US6252799B1 (en) 1997-04-11 2001-06-26 Programmable Silicon Solutions Device with embedded flash and EEPROM memories
US5805500A (en) 1997-06-18 1998-09-08 Sgs-Thomson Microelectronics S.R.L. Circuit and method for generating a read reference signal for nonvolatile memory cells
JP3189740B2 (ja) 1997-06-20 2001-07-16 日本電気株式会社 不揮発性半導体メモリのデータ修復方法
JP3039458B2 (ja) 1997-07-07 2000-05-08 日本電気株式会社 不揮発性半導体メモリ
IL125604A (en) 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US5940332A (en) 1997-11-13 1999-08-17 Stmicroelectronics, Inc. Programmed memory with improved speed and power consumption
US5867429A (en) 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US5949728A (en) 1997-12-12 1999-09-07 Scenix Semiconductor, Inc. High speed, noise immune, single ended sensing scheme for non-volatile memories
US5946258A (en) 1998-03-16 1999-08-31 Intel Corporation Pump supply self regulation for flash memory cell pair reference circuit
JP3544859B2 (ja) * 1998-05-11 2004-07-21 富士通株式会社 不揮発性半導体メモリを使用した２次記憶装置
JP3999900B2 (ja) 1998-09-10 2007-10-31 株式会社東芝 不揮発性半導体メモリ
DE69828966D1 (de) 1998-09-15 2005-03-17 St Microelectronics Srl Verfahren zum Schutz des Inhalts nichtflüchtiger Speicherzellen
US6308265B1 (en) * 1998-09-30 2001-10-23 Phoenix Technologies Ltd. Protection of boot block code while allowing write accesses to the boot block
US6044019A (en) 1998-10-23 2000-03-28 Sandisk Corporation Non-volatile memory with improved sensing and method therefor
JP2000222892A (ja) * 1999-02-01 2000-08-11 Matsushita Electric Ind Co Ltd 半導体記憶装置のしきい値制御方法およびスクリーニング方法
US6233180B1 (en) 1999-02-04 2001-05-15 Saifun Semiconductors Ltd. Device for determining the validity of word line conditions and for delaying data sensing operation
US6108240A (en) 1999-02-04 2000-08-22 Tower Semiconductor Ltd. Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions
US6128226A (en) 1999-02-04 2000-10-03 Saifun Semiconductors Ltd. Method and apparatus for operating with a close to ground signal
US6147904A (en) 1999-02-04 2000-11-14 Tower Semiconductor Ltd. Redundancy method and structure for 2-bit non-volatile memory cells
US6134156A (en) 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays
US6044022A (en) 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6084794A (en) 1999-05-28 2000-07-04 Winbond Electronics Corp. High speed flat-cell mask ROM structure with select lines
US6469935B2 (en) 1999-08-05 2002-10-22 Halo Lsi Design & Device Technology, Inc. Array architecture nonvolatile memory and its operation methods
JP3912937B2 (ja) 1999-08-10 2007-05-09 スパンション インク 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ
JP3348432B2 (ja) 1999-09-14 2002-11-20 日本電気株式会社 半導体装置および半導体記憶装置
US6331950B1 (en) 1999-10-19 2001-12-18 Fujitsu Limited Write protect input implementation for a simultaneous operation flash memory device
US6201737B1 (en) 2000-01-28 2001-03-13 Advanced Micro Devices, Inc. Apparatus and method to characterize the threshold distribution in an NROM virtual ground array
US6185143B1 (en) 2000-02-04 2001-02-06 Hewlett-Packard Company Magnetic random access memory (MRAM) device including differential sense amplifiers
US6205056B1 (en) 2000-03-14 2001-03-20 Advanced Micro Devices, Inc. Automated reference cell trimming verify
US6240040B1 (en) 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory
KR100414146B1 (ko) * 2000-06-27 2004-01-13 주식회사 하이닉스반도체 플래쉬 메모리 소자의 소거 방법
JP2002184190A (ja) 2000-12-11 2002-06-28 Toshiba Corp 不揮発性半導体記憶装置
JP2002216496A (ja) * 2001-01-16 2002-08-02 Umc Japan 半導体メモリ装置
TW550576B (en) * 2001-02-20 2003-09-01 Toshiba Corp Data writing method of semiconductor memory device and semiconductor device
JP4467815B2 (ja) 2001-02-26 2010-05-26 富士通マイクロエレクトロニクス株式会社 不揮発性半導体メモリの読み出し動作方法および不揮発性半導体メモリ
US6351415B1 (en) 2001-03-28 2002-02-26 Tower Semiconductor Ltd. Symmetrical non-volatile memory array architecture without neighbor effect
US6535434B2 (en) 2001-04-05 2003-03-18 Saifun Semiconductors Ltd. Architecture and scheme for a non-strobed read sequence
JP2002319287A (ja) 2001-04-20 2002-10-31 Fujitsu Ltd 不揮発性半導体メモリ
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
US6522585B2 (en) 2001-05-25 2003-02-18 Sandisk Corporation Dual-cell soft programming for virtual-ground memory arrays
US6574139B2 (en) 2001-06-20 2003-06-03 Fujitsu Limited Method and device for reading dual bit memory cells using multiple reference cells with two side read
KR100390959B1 (ko) * 2001-06-29 2003-07-12 주식회사 하이닉스반도체 센싱회로를 이용한 멀티레벨 플래시 메모리 프로그램/리드방법
US6643178B2 (en) 2001-07-31 2003-11-04 Fujitsu Limited System for source side sensing
US6525969B1 (en) 2001-08-10 2003-02-25 Advanced Micro Devices, Inc. Decoder apparatus and methods for pre-charging bit lines
US6469929B1 (en) 2001-08-21 2002-10-22 Tower Semiconductor Ltd. Structure and method for high speed sensing of memory arrays
US6456528B1 (en) * 2001-09-17 2002-09-24 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode
US6510082B1 (en) 2001-10-23 2003-01-21 Advanced Micro Devices, Inc. Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold
TW506123B (en) 2001-10-24 2002-10-11 Macronix Int Co Ltd Multi-level NROM memory cell and its operating method
US6678192B2 (en) * 2001-11-02 2004-01-13 Sandisk Corporation Error management for writable tracking storage units
US6529412B1 (en) 2002-01-16 2003-03-04 Advanced Micro Devices, Inc. Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
US6639844B1 (en) 2002-03-13 2003-10-28 Advanced Micro Devices, Inc. Overerase correction method
US6594181B1 (en) 2002-05-10 2003-07-15 Fujitsu Limited System for reading a double-bit memory cell
JP4113423B2 (ja) * 2002-12-04 2008-07-09 シャープ株式会社 半導体記憶装置及びリファレンスセルの補正方法
US7742339B2 (en) * 2006-01-10 2010-06-22 Saifun Semiconductors Ltd. Rd algorithm improvement for NROM technology

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