CN1825628A - 包括高介电常数绝缘层的半导体器件及其制造方法 - Google Patents

包括高介电常数绝缘层的半导体器件及其制造方法 Download PDF

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CN1825628A
CN1825628A CNA2006100050218A CN200610005021A CN1825628A CN 1825628 A CN1825628 A CN 1825628A CN A2006100050218 A CNA2006100050218 A CN A2006100050218A CN 200610005021 A CN200610005021 A CN 200610005021A CN 1825628 A CN1825628 A CN 1825628A
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insulating barrier
doped region
layer
silicate
storage unit
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田尚勋
崔圣圭
金桢雨
黄显相
韩祯希
崔相武
朴星昊
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Samsung Electronics Co Ltd
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Abstract

一种半导体存储器件,包括第一掺杂区和第二掺杂区,所述第一掺杂区和第二掺杂区设置在半导体衬底中;绝缘层,设置得与所述第一掺杂区和第二掺杂区接触,所述绝缘层包括从包括Hf、Zr、Y和Ln的组中选择的材料;和设置在所述绝缘层上的栅电极层。

Description

包括高介电常数绝缘层的半导体器件及其制造方法
技术领域
本公开涉及一种包括高介电常数(高k)绝缘层的半导体存储器件及其制造方法。
背景技术
半导体存储器件的发展集中于增加信息存储容量以及信息记录和擦除的速度。这样的半导体存储器件包括大量的以电路相互连接的单位存储单元。
例如动态随机存取存储器(DRAM)DRAM的半导体存储器件的每个单位单元包括晶体管和电容器。DRAM是能够快速进行存取但对于存储的信号具有短的维持时间的易失性存储器件。
易失性存储器件的典型例子是闪存。已经发展出各种其他类型的易失性存储器件,例如硅-氮化物-氧化物半导体(silicon-nitride-oxide,SNOS)存储器件、MRAM、PRAM等。闪存器件、SNOS存储器件和浮置栅极型存储器件通常使用具有高介电常数(高k)的材料。
图1A和1B是示出制造具有高k材料的常规SNOS存储器件的工艺的截面图。参照图1A,隧穿氧化物层13、电荷俘获层14、阻隔氧化物层15和栅电极层16依次形成在半导体衬底11上。隧穿氧化物层13可以由SiO2形成为约30厚度,电荷俘获层14可以由HfO2形成,且阻隔氧化物层15可以由Al2O3形成为约100厚度。
接着,隧穿氧化物层13、电荷俘获层14、阻隔氧化物层15和栅电极层16的每个的两侧均被除去以形成栅极。结果,在栅极两侧暴露出半导体衬底11的上表面。
参照图1B,通过离子注入法,栅极两侧的半导体衬底11的上表面被例如硼(B)或磷(P)的掺杂剂掺杂。此处,根据半导体衬底11的掺杂类型选择掺杂剂。换句话说,如果半导体衬底11是n型衬底,第一和第二掺杂区12a和12b被注入属于III族的材料以掺杂p型掺杂剂。如果半导体衬底11是p型衬底,第一和第二掺杂区12a和12b被注入属于V族的材料以掺杂n型掺杂剂。
在半导体衬底11如图1B所示被注入掺杂剂后,进行退火工艺以激活第一和第二掺杂区12a和12b,如图1C所示。为此,第一和第二掺杂区12a和12b在约900℃与1000℃之间的高温被加热。第一和第二掺杂区12a和12b被此高温退火工艺结晶化,变为第一和第二掺杂区12a’和12b’。
然而,上述高温退火工艺也可能引起通常用在半导体存储器件的栅结构中的高k材料变得结晶。通常,在高k材料在初始淀积状态中是非晶的情况下,在半导体存储器件工作过程中,高k材料必须与栅电极层16绝缘。然而,在用于阻隔氧化物层15的材料被高温退火工艺结晶化的情况下,可能通过晶粒边界区产生漏电流,且可能对半导体存储器件的特性具有不利影响。
例如,图2A和2B示出了图1A-1C所示的采用上述高温退火工艺制造的存储器件的特性。
图2A示出了在氧气氛下,在700℃、800℃和900℃的温度退火的常规半导体存储器件的电流-电压(I-V)特性。参照图2A,当电压接近0V时,电流密度逐渐减小。然而,电流密度仍然接近大于零的值。具体地,当半导体存储器件在900℃的更高温度被退火时,电流密度具有更大值。
图2B是示出根据上述图1A和1B所示的工艺制造的半导体存储器件在700℃、800℃、900℃、950℃和1000℃的温度退火后所测量的X射线衍射(XRD)图。参照图2B,可以看出随着退火温度增加,Al2O3峰在约68°变得显著。此峰显示结晶已经发生。换句话说,随着退火温度增加,结晶更容易发生。
图2C是示出根据图1A和1B所述的工艺制造的半导体存储器件的维持特性相对于退火温度的曲线图。半导体存储器件在800℃或以下的退火温度下具有小于或等于“0.2”的高维持值,但在900℃的退火温度下具有低维持值。
因此,可以看出,由高温退火工艺引起的高k材料的结晶对常规半导体存储器件的特性具有不利影响。
本发明的实施例解决了常规技术的这些及其他缺点。
发明内容
本发明提供了一种半导体存储器件,其包括例如硅酸铪(Hf)、硅酸锆(Zr)、硅酸钇(Y)或镧系金属硅酸盐的高k材料,使得即使在用于激活第一和第二掺杂区的高温退火工艺中也保持热稳定,以及制造该半导体存储器件的方法。
附图说明
通过参照附图对本发明示范性实施例的描述,本发明的上述及其他特定和优点将变得更为明显。
图1A到1C是示出制造SNOS半导体存储器件的常规方法的截面图。
图2A是示出图1A-1C的半导体存储器件的电学特性的曲线图。
图2B是示出图1A-1C的半导体存储器件的XRD的曲线图。
图2C是示出图1A到1C所示的半导体存储器件的维持特性相对于退火温度的曲线图。
图3A到3D是示出用于根据本发明的实施例制造包括高k绝缘层的半导体存储器件的方法的截面图。
图4是示出Zr或Hf硅酸盐的介电常数相对于Zr或Hf硅酸盐的原子百分比的曲线图。
图5A是示出具有66∶33的原子百分比的ZrO2和SiO2化合物的XRD的曲线图。
图5B是示出具有45∶55的原子百分比的ZrO2和SiO2化合物的XRD的曲线图。
图5C是示出具有17∶83的原子百分比的ZrO2和SiO2化合物的XRD的曲线图。
图6A是示出具有82∶18的原子百分比的HfO2和SiO2化合物的XRD的曲线图。
图6B是示出具有57∶43的原子百分比的HfO2和SiO2化合物的XRD的曲线图。
图6C是示出具有26∶73的原子百分比的HfO2和SiO2化合物的XRD的曲线图。
具体实施方式
下面参照附图描述根据本发明的一些实施例的包括高k绝缘层的半导体存储器件及制造该半导体存储器件的方法。
图3A到3D是示出根据本发明一些实施例的包括高k绝缘层的半导体存储器件的制造方法的截面图。在附图中,为了清楚而夸大了层和区域的厚度。在示出的实施例中,以SONOS存储器件作为例子进行描述。然而,应该理解,包括在示出的实施例中的本发明的原理可以应用到其他包括高k材料的存储器件中,例如闪存器件、浮置栅极型存储器等。
参照图3A,第一氧化物层33、电荷俘获层34、第二氧化物层35和栅电极层36依次形成在半导体衬底31上。通常,第一氧化物层33、电荷俘获层34和第二氧化物层35由介电材料形成,并具有绝缘体的性质。此处,在SONOS存储器件的情况中,第一氧化物层33可以称为隧穿氧化物层,且第二氧化物层35可以称为阻隔氧化物层。
根据本发明的实施例,介电层包括高k介电材料。高k介电材料可以包括硅酸铪(Hf)、硅酸锆(Zr)、硅酸钇(Y)或镧(Ln)系金属硅酸盐的一种或多种,其中Ln通常用于称镧系金属中的十五种元素(La、Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb或Lu)中的任意一种。
具体地,高k介电材料包括((Hf、Zr、Y或Ln)O2)x(SiO2)1-x, 其中x在0.03与0.26之间的范围内(0.03≤x≤0.26)。换句话说,添加到硅酸盐的Hf、Zr、Y或Ln的量可以在3%的原子百分比与26%的原子百分比的范围之间选择性地调整。因此,如同在下面将详细描述的,半导体存储器件可以在制造该半导体存储器件工艺中的高温退火工艺中保持热稳定。在一些实施例中,例如铝(Al)或氮(N)的材料可以添加到((Hf、Zr、Y或Ln)O2)x(SiO2)1-x中,以保证热稳定性。
在可选实施例中,Al可以取代硅(Si)使用为高k介电材料。在这种情况下,高k介电材料的化学式为((Hf、Zr、Y或Ln)O2)x(Al2O3)1-x,其中(0.03≤x≤0.26)。
参照图3B,隧穿氧化物层33、电荷俘获层34、阻隔氧化物层35和栅电极层36的每个的两侧被依次蚀刻,以限定预定宽度的栅极区域。结果,暴露出栅极区域两侧的半导体衬底31的上表面。图3A和3B所示的所得结构可以通过通常公知的半导体工艺容易地制造。
参照图3C,采用离子注入工艺等对半导体衬底31的暴露的上表面掺杂掺杂剂。此处,掺杂剂可以根据半导体衬底31的掺杂状态而选择性地使用。如果半导体衬底31是p型衬底,半导体衬底31的上表面可以掺杂属于V族的材料以形成第一和第二掺杂区32a和32b。如果半导体衬底31是n型衬底,半导体衬底31的上表面可以掺杂属于III族的材料,以形成第一和第二掺杂区32a和32b。
参照图3D,在约950℃与1000℃之间的温度下进行退火工艺。如果退火工艺进行几秒到几分钟,可以形成被激活的即结晶的第一和第二掺杂区32a’和32b’。退火工艺应该在900℃或以上的温度下进行,以如上所述激活第一和第二掺杂区32a和32b。
如上面所解释的,如果温度高于或等于高k材料被重结晶(re-crystallized)的温度,高k材料从非晶态转变为晶态。因此,在常规SONOS存储器件的情况,在阻隔氧化物层35中,由于晶粒边界而产生不希望的电流泄漏。因此,俘获在数据存储区中的电荷很可能移动,且器件的维持特性劣化。
然而,根据本发明的实施例,当高k绝缘层包括Hf、Zr、Y或镧系金属的硅酸盐或由其组成时,高k绝缘层即使在高温退火工艺中也保持在稳定的非晶态。这防止了半导体存储器件的电特性的劣化。
根据本发明一些实施例的高k绝缘层的特性将参照附图进一步描述。具体地,将描述Zr硅酸盐或Hf硅酸盐绝缘层。
图4是示出Zr硅酸盐或Hf硅酸盐的介电常数相对于硅酸盐中的Zr或Hf的原子百分比的图。参照图4,介电常数随着Zr或Hf相对于Si的原子百分比的增加而增加。根据本发明的实施例,如果Zr或Hf添加到SiO2,Zr或Hf的原子百分比可以为26%或更小。在这种情况下,Zr硅酸盐或Hf硅酸盐的介电常数稍小于十(10)。这样,Zr或Hf硅酸盐是具有比SiO2的介电常数大的、约3.9的介电常数的高k材料。结果,根据本发明的实施例,高k材料的介电常数位于3.9与10之间的范围内(3.9<k<10)。
图5A到图5C是示出相对于添加到硅酸盐的Zr量的XRD的曲线图。
图5A是示出在具有66∶33的原子百分比的ZrO2和SiO2样品被制造并在600℃、800℃、900℃和1000℃温度下退火后测量的XRD图。参照图5A,当退火温度高时,观察到了结晶特征的峰。具体地,在约30°观察到了ZrO晶体特征峰。因此,可以确定样品已经结晶。
图5B是示出在具有45∶55的原子百分比的ZrO2和SiO2样品被制造且然后在600℃、800℃、900℃和1000℃温度下退火后测量的XRD图。参照图5B,当退火温度高时,观察到了结晶特征的峰。从在900℃和1000℃温度下退火的样品中在约30°观察到了ZrO晶体特征峰。结果,可以确定高k材料已经在半导体存储器件的制造工艺中结晶,在该工艺中在900℃或以上的温度下进行退火。
图5C是示出在具有17∶83的原子百分比的ZrO2和SiO2样品被制造且然后在600℃、800℃、900℃和1000℃温度下退火后测量的XRD图。参照图5C,可以看到,即使在高的退火温度下,也没有观测到存在约30°处的ZrO晶体特征峰。在约57°观察到的特征峰是Si衬底的特征峰。因此,当进行高温退火时,具有由本发明实施例所教导的范围内的原子百分比的Zr硅酸盐不结晶,而是保持非晶。
图6A到6C是示出相对于添加到硅酸盐的Hf的原子百分比的XRD的曲线图。
图6A是示出在具有82∶18的原子百分比的HfO2和SiO2的样品制造并随后在600℃、800℃、900℃和1000℃温度下退火后测量的XRD图。参照图6A,当退火温度高时,在约30°清楚地观察到了HfO2的结晶特征峰。因此,可以确定结晶已经进行。
图6B是示出在具有57∶43的原子百分比的HfO2和SiO2样品制造并随后在600℃、800℃、900℃和1000℃温度下退火后测量的XRD图。参照图6B,在600℃和800℃温度未观察到特征峰。因此,可以确定,非晶态被保持了。然而,在900℃和1000℃的温度下,在约30°观察到了HfO2特征峰。因此,可以确定,在这些温度结晶已经进行了。结果,高k材料在半导体存储器件的制造工艺中被结晶,在该工艺中,退火在900℃或更高的温度下进行。
图6C是示出在具有26∶73的原子百分比的HfO2和SiO2样品制造并随后在600℃、800℃、900℃和1000℃温度下退火后测量的XRD图。参照图6C,在600℃和800℃温度未观察到特征峰。因此,可以确定,非晶态被保持了。然而,在900℃和1000℃的温度下,在约30°观察到了HfO2特征峰。因此,在这些温度结晶已经进行了。结果,高k材料在半导体存储器件的制造工艺中被结晶,在该工艺中,退火在900℃或更高的温度下进行。
因此,根据本发明的实施例,具有小于或等于26%的原子百分比的组分比的Zr或Hf硅酸盐在900℃或以上的温度下进行的高温退火工艺中是热稳定的。因此,Zr或Hf硅酸盐不是被结晶而是保持为非晶。此处,Zr或Hf硅酸盐的介电常数保持在“10”或以下。即使在Y硅酸盐或镧族金属(Ln)硅酸盐用作介电层的情况中,也可以观察到这些特征。在这种情况下,建立了化学式“((Hf、Zr、Y或Ln)O2)x(SiO2)1-x(0.03≤x≤0.26)”。而且,Al可以取代Si用在该化学式中。在这种情况下,可以表述为化学式“((Hf、Zr、 Y或Ln)O2)x(Al2O3)1-x(0.03≤x≤0.26)”。
如上所述,根据本发明的实施例,Zr或Hf硅酸盐可以用作闪存器件、SONOS存储器件、浮置栅型存储器件、或电荷俘获存储器中的高k材料。因此,可以防止高k材料(铁电层)的结晶化,以避免由于高温退火工艺而对半导体存储器件特性的不利影响。漏电流可以减少,且半导体存储器件的维持特性也可以改进。同时,尽管根据上述的发明原理进行了改进,仍可以采用通常公知的用于制造半导体器件的制造工艺。
本发明可以实施为许多方式。下面是对本发明的一些实施例的示范性、非限制性的描述。
根据一些实施例,半导体存储器件包括形成在半导体衬底中的第一和第二掺杂区;形成在该半导体衬底上以接触第一和第二掺杂区的绝缘层,该绝缘层包括Hf硅酸盐、Zr硅酸盐、Y硅酸盐、或镧系金属硅酸盐;以及形成在该绝缘层上的栅电极层。
绝缘层可以具有((Hf、Zr、Y或Ln)O2)x(SiO2)1-x(0.03≤x≤0.26)的组分和小于或等于十(10)的介电常数。
绝缘层可以包括依次形成的隧穿氧化物层、数据存储层和阻隔氧化物层,其中隧穿氧化物层和阻隔氧化物层之一是具有“((Hf、Zr、Y或Ln)O2)x(SiO2)1-x(0.03≤x≤0.26)”的化学式的介电层。
绝缘层可以包括Al或N。
根据一些实施例,制造半导体存储器件的方法包括在半导体衬底上形成包括Hf硅酸盐、Zr硅酸盐、Y硅酸盐或镧系金属硅酸盐的绝缘层;在绝缘层上形成栅电极层;除去绝缘层和栅电极层的每个的两侧以形成栅极区,并暴露栅极区两侧的半导体衬底的上表面;用掺杂剂掺杂半导体衬底的暴露的上表面以形成第一和第二掺杂区,以及进行退火从而激活第一和第二掺杂区。
绝缘层可以通过在半导体衬底上依次淀积隧穿氧化物层、电荷俘获层和阻隔氧化物层而形成。此处,隧穿氧化物层或阻隔氧化物层可以是具有化学式“((Hf、Zr、Y或Ln)O2)x(SiO2)1-x(0.03≤x≤0.26)”的介电层。
绝缘层可以具有小于或等于十(10)的介电常数,且绝缘层可以包括Al或N。
根据本发明的一些实施例,半导体存储器件包括形成在半导体衬底上的第一和第二掺杂区、形成在半导体衬底上以接触第一和第二掺杂区并具有((Hf、Zr、Y或Ln)O2)x(Al2O3)1-x(0.03≤x≤0.26)的组分的绝缘层、和形成在绝缘层上的栅电极层。
上述优选实施例应该理解为包含在优选实施例中的本发明的原理的示范性的和说明性的,而不是对本发明范畴的限制。例如,虽然在SONOS存储器件的情况下描述了优选实施例,但包含在这些优选实施例中的发明原理可以应用到使用高k材料的其他存储器件,例如闪存器件、浮置栅型存储器件、或电荷俘获存储器。因此,本发明的范畴不是由发明的详细描述限定,而是由权利要求限定。
此外,对于本发明的具体实施例,所述说明书包含一个或多个参考,每个具体实施例用于示出一个或多个本发明所教导的发明原理。应该理解,所有的实施例包括至少一个上述发明原理,且这些实施例可以包括多于一个所示的发明原理。
本申请要求2005年1月18日向韩国知识产权局提交的韩国专利申请第10-2005-0004455号的优先权。韩国专利申请第10-2005-0004455号全文引用在此处作为参考。

Claims (20)

1、一种半导体存储器件,包括:
第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区设置在半导体衬底中;
绝缘层,设置得与所述第一掺杂区和所述第二掺杂区接触,所述绝缘层包括Hf硅酸盐、Zr硅酸盐、Y硅酸盐和Ln硅酸盐中的至少一种;和
栅电极层,设置在所述绝缘层上。
2、如权利要求1所述的半导体存储器件,所述绝缘层包括一材料,该材料具有化学式((Hf、Zr、Y或Ln)O2)x(SiO2)1-x,其中0.03≤x≤0.26,所述材料具有大于3.9且小于或等于10的介电常数。
3、如权利要求1所述的半导体存储器件,所述绝缘层包括:
隧穿氧化物层,设置得与所述第一掺杂区和第二掺杂区接触;
数据存储层,设置在所述隧穿氧化物层上;和
阻隔氧化物层,设置在所述数据存储层上,所述隧穿氧化物层和所述阻隔氧化物层之一由化学式为((Hf、Zr、Y或Ln)O2)x(SiO2)1-x的介电层构成,其中0.03≤x≤0.26。
4、如权利要求1所述的半导体存储器件,所述绝缘层包括Al和N之一。
5、如权利要求1所述的半导体器件,所述绝缘层包括Hf硅酸盐。
6、如权利要求1所述的半导体器件,所述绝缘层包括Zr硅酸盐。
7、如权利要求1所述的半导体器件,所述绝缘层包括Y硅酸盐。
8、如权利要求1所述的半导体器件,所述绝缘层包括Ln硅酸盐。
9、一种制造半导体存储器件的方法,该方法包括:
在半导体衬底上形成绝缘层,所述绝缘层包括从包括Hf、Zr、Y和Ln的组中选择的至少一种;
在所述绝缘层上形成栅电极层;
除去一部分所述绝缘层和一部分所述栅电极层,以限定栅极,并暴露位于栅极两侧的所述半导体衬底的上表面;
用掺杂剂掺杂所述半导体衬底的所述上表面,以形成第一掺杂区和第二掺杂区;和
退火所述半导体衬底的所述上表面以激活所述第一掺杂区和所述第二掺杂区。
10、如权利要求9所述的方法,其中形成所述绝缘层包括:
在所述半导体衬底上淀积隧穿氧化物层;
在所述隧穿氧化物层上淀积电荷俘获层;和
在所述电荷俘获层上淀积阻隔氧化物层,所述隧穿氧化物层和所述阻隔氧化物层之一由化学式为((Hf、Zr、Y或Ln)O2)x(SiO2)1-x的介电层构成,其中0.03≤x≤0.26。
11、如权利要求9所述的方法,其中形成所述绝缘层包括:
在所述半导体衬底上淀积隧穿氧化物层;
在所述隧穿氧化物层上淀积电荷俘获层;和
在所述电荷俘获层上淀积阻隔氧化物层,所述隧穿氧化物层和所述阻隔氧化物层之一由化学式为((Hf、Zr、Y或Ln)O2)x(Al2O3)1-x的介电层构成,其中0.03≤x≤0.26。
12、如权利要求9所述的方法,其中所述绝缘层具有大于3.9且小于或等于10的介电常数。
13、如权利要求9所述的方法,其中所述绝缘层包括Al和N之一。
14、一种半导体存储器件,包括:
第一掺杂区和第二掺杂区,所述第一掺杂区和所述第二掺杂区设置在半导体衬底中;
绝缘层,设置得接触所述第一掺杂区和所述第二掺杂区,所述绝缘层包括从包括Hf、Zr、Y和Ln的组中选择的材料;和
栅电极层,设置在所述绝缘层上。
15、如权利要求14所述的半导体存储器件,所述绝缘层包括:
隧穿氧化物层,设置得接触所述第一掺杂区和所述第二掺杂区;
数据存储层,设置在所述隧穿氧化物层上;和
阻隔氧化物层,设置在所述数据存储层上,所述隧穿氧化物层和所述阻隔氧化物层之一由化学式为((Hf、Zr、Y或Ln)O2)x(SiO2)1-x的介电层构成,其中0.03≤x≤0.26。
16、如权利要求14所述的半导体存储器件,其中所述绝缘层包括:
隧穿氧化物层,设置得接触所述第一掺杂区和所述第二掺杂区;
数据存储层,设置在所述隧穿氧化物层上;和
阻隔氧化物层,设置在所述数据存储层上,所述隧穿氧化物层和所述阻隔氧化物层之一由化学式为((Hf、Zr、Y或Ln)O2)x(Al2O3))1-x的介电层构成,其中0.03≤x≤0.26。
17、如权利要求14所述的半导体器件,所述绝缘层包括Hf。
18、如权利要求14所述的半导体器件,所述绝缘层包括Zr。
19、如权利要求14所述的半导体器件,所述绝缘层包括Y。
20、如权利要求14所述的半导体器件,所述绝缘层包括Ln。
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