CN1670958A - 硅氧化物氮化物氧化物半导体型存储器件 - Google Patents
硅氧化物氮化物氧化物半导体型存储器件 Download PDFInfo
- Publication number
- CN1670958A CN1670958A CNA2005100036659A CN200510003665A CN1670958A CN 1670958 A CN1670958 A CN 1670958A CN A2005100036659 A CNA2005100036659 A CN A2005100036659A CN 200510003665 A CN200510003665 A CN 200510003665A CN 1670958 A CN1670958 A CN 1670958A
- Authority
- CN
- China
- Prior art keywords
- layer
- memory
- impurity range
- tunnel oxidation
- storage node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims description 35
- 238000007254 oxidation reaction Methods 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- -1 silicon oxide nitride Chemical class 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 3
- 229910052691 Erbium Inorganic materials 0.000 claims description 3
- 229910052693 Europium Inorganic materials 0.000 claims description 3
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 3
- 229910052689 Holmium Inorganic materials 0.000 claims description 3
- 229910052765 Lutetium Inorganic materials 0.000 claims description 3
- 229910052779 Neodymium Inorganic materials 0.000 claims description 3
- 229910052777 Praseodymium Inorganic materials 0.000 claims description 3
- 229910052772 Samarium Inorganic materials 0.000 claims description 3
- 229910052771 Terbium Inorganic materials 0.000 claims description 3
- 229910052775 Thulium Inorganic materials 0.000 claims description 3
- 229910052769 Ytterbium Inorganic materials 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052747 lanthanoid Inorganic materials 0.000 claims description 3
- 150000002602 lanthanoids Chemical class 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 238000013500 data storage Methods 0.000 abstract description 6
- 230000000903 blocking effect Effects 0.000 abstract 4
- 230000005641 tunneling Effects 0.000 abstract 4
- 238000000034 method Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 230000010354 integration Effects 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005264 electron capture Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000013213 extrapolation Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31616—Deposition of Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
提供了一种SONOS型存储器,包括半导体衬底;配置在半导体衬底中、用预定导电性的杂质离子掺杂的、彼此分开预定距离的、并且之间插入沟道区的第一杂质区和第二杂质区;和在第一杂质区和第二杂质区之间的半导体衬底上形成的数据存储型堆叠。数据存储型堆叠包括依次形成的隧道氧化层、用于存储数据的存储节点层、阻挡氧化层和电极层。存储节点层的介电常数高于隧道氧化层的介电常数和阻挡氧化层的介电常数,并且存储节点层的能带差低于隧道氧化层的能带差和阻挡氧化层的能带差,隧道氧化层和阻挡氧化层是高介电绝缘层。
Description
技术领域
本发明涉及半导体存储器件,更特别地涉及包含高介电层的硅氧化物氮化物氧化物半导体(silicon oxide nitride oxide semiconductor)(SONOS)型存储器件。
背景技术
半导体存储器件中存储数据的容量与每单位面积的存储单元数量(即集成密度)成比例。半导体存储器件包含许多彼此连接的存储单元。
在半导体存储器中,例如,DRAM,每个存储单元通常包含单个晶体管和单个电容器。因此,为了增加半导体存储器的集成密度,应该减小晶体管覆盖的面积和/或电容器覆盖的面积。
传统的低集成半导体存储器件在光刻和刻蚀过程中具有足够的工艺裕度(margin)。因此,可以仅通过降低如上所述的晶体管面积和/或电容面积,来增加半导体存储器的集成密度。
然而,随着半导体技术和相关电子工业的发展,强烈需要高集成半导体器件,但是传统的方法不能满足需要。
同时,半导体存储器的集成密度与应用于半导体存储器生产的设计规则密切相关。从而,为了改善半导体存储器的集成度,严格的设计规则应该应用于其生产过程。因此,光刻和刻蚀过程需要的工艺裕度变得极低。换言之,生产半导体存储器时使用的光刻和刻蚀过程需要比以前开发的工艺更精细的工艺裕度。
生产半导体存储器时,如果光刻和刻蚀过程需要的工艺裕度较低,则产率也降低。因此,需要一种增加半导体存储器集成密度的同时防止产率降低的新方法。
因此,已经开发了包含数据存储介质例如GMR或TMR的半导体存储器,其配置在晶体管上并执行不同于其它传统电容的数据存储功能。
SONOS存储器是新开发的存储器件。图1是传统的SONOS存储器的剖面图。
参考图1,传统的SONOS存储器包括P型半导体衬底10(以下,称为半导体衬底)、源区12、漏区14和沟道区16。源区12和漏区14用n-型杂质离子掺杂。沟道区16配置在源区12和漏区14之间。在半导体衬底10的沟道区16上形成栅叠加30。栅叠加30包括依次堆叠的隧道氧化层18、氮化硅(Si3N4)层20、阻挡氧化层22、和栅电极24。隧道氧化层18与源和漏区12和14接触。氮化硅层20具有预定密度的陷阱点(trap site)。从而,当预定电压施加于栅电极24时,已经通过隧道氧化层18的电子俘获在氮化硅层20中的陷阱点。隧道氧化层18和阻挡氧化层22可以由二氧化硅形成。
阻挡氧化层22防止在陷阱点俘获电子时电子移动到栅电极24。
在这种传统存储器件中,阀值电压随电子是否俘获在氮化硅层20的陷阱点中而变化。通过利用该特征,传统的SONOS存储器可以储存并读出数据。
然而,该传统SONOS存储器不仅需要很长时间擦除数据,而且具有较短的保留时间,即,它不能长时间保有存储数据。
此外,当隧道氧化层和阻挡氧化层由二氧化硅组成时,SONOS存储器需要约10V的高驱动电压,从而妨碍存储器的高集成度。
发明内容
本发明提供了一种硅氧化物氮化物氧化物半导体(SONOS)型存储器,其不需要高驱动电压,同时通常保留存储数据相对较长的时间。
根据本发明的一个方面,提供了一种SONOS型存储器,其包括半导体衬底;第一杂质区和第二杂质区;和数据存储型堆叠。该第一杂质区和第二杂质区配置在半导体衬底中,用预定导电性的杂质离子掺杂,并且彼此分开预定的距离。在这里,沟道区配置在第一杂质区和第二杂质区之间。而且,在第一杂质区和第二杂质区之间的半导体衬底上形成数据存储型堆叠。
数据存储型堆叠包括依次形成的隧道氧化层、存储数据的存储节点层(memory node layer)、阻挡氧化层和电极层。
存储节点层的介电常数高于隧道氧化层和阻挡氧化层的介电常数,存储节点层的能带差(band offset)低于隧道氧化层和阻挡氧化层的能带差。
隧道氧化层和阻挡氧化层是高介电绝缘层。
隧道氧化层可以由具有比二氧化硅(SiO2)介电常数高的材料形成的。隧道氧化层可以由氧化铝(Al2O3)形成。
存储节点层可以选自MO层、MON层和MSiON层(M是金属)之一。
M可以是Hf、Zr、Ta、Ti或镧系元素(Ln),Ln可以是La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb或Lu。
存储节点层可以由HfO2形成。阻挡氧化层可以由Al2O3形成。
本发明的SONOS类型存储器可以极大地降低编程时间和擦除时间,从而改善数据处理速度。此外,因为存储器的驱动电压可以减少到约6V,存储器可以是高度集成的。
附图说明
通过参考相关附图详细描写示范性具体实施方式,本发明的上述特征和优点将变得更加显而易见。
图1是传统的硅氧化物氮化物氧化物半导体(SONOS)存储器的剖面图;
图2是根据本发明一个具体实施方式的SONOS型存储器的剖面图;
图3图解说明了相对于某些材料介电常数的带隙;
图4图解说明了与图2中显示的存储器的编程时间和擦除时间相应的平带电压VFB变化;
图5图解说明了图2显示的存储器中数据的保留时间;和
图6图解说明了图2中显示的存储器和传统存储器的存储窗的相对速率。
具体实施方式
现在将参考显示本发明示范性具体实施方式的附图更完全地描述本发明。为了清楚放大了附图中层和区域的厚度。
图2是根据本发明一个具体实施方式的硅氧化物氮化物氧化物半导体(SONOS)型存储器的剖面图。
参考图2,SONOS型存储器包括衬底40,例如P型半导体衬底,和在衬底40内形成的第一杂质区42和第二杂质区44。第一和第二杂质区42和44用预定导电性的杂质离子例如n-型杂质离子掺杂至预定深度。第一和第二杂质区42和44彼此分开预定距离,在第一和第二杂质区42和44之间形成用预定导电性的杂质离子掺杂的沟道区46。
在下文中,第一杂质区42和第二杂质区44分别称为源区和漏区。
在半导体衬底40上部源和漏区42和44之间,即在沟道区46上形成数据存储型栅堆叠60(在下文中称为栅堆叠)。栅堆叠60包括依次堆叠的隧道氧化层48、存储节点层50、阻挡氧化层52和电极层54。
隧道氧化层48接触沟道区46的整个表面,隧道氧化层48的外缘分别接触源区42和漏区44。隧道氧化层48由具有介电常数高于构成传统SONOS型存储器隧道氧化层的二氧化硅(SiO2)的材料形成,例如,隧道氧化层48可以由氧化铝(Al2O3)形成。此外,因为隧道氧化层48确定晶体管的特征,隧道氧化层48可以由构成栅绝缘层高介电材料形成。也就是说,之后描述的图3显示的介电材料Al2O3或MgO可以形成介电常数高于SiO2的隧道氧化层48。隧道氧化层48可以形成至厚度约1.5-5nm。
当适当电压施加至电极层54时,通过隧道氧化层48的电子被俘获在存储节点层50中。当电子俘获在存储节点层50中时,存储数据“1”。此外,当电子没有俘获在存储节点层50中时,存储数据“0”。因为存储节点层50包括在栅堆叠60中,该栅堆叠60可以适当地称为数据存储型。
如上所述,存储节点层50用作电子俘获层。因此,存储节点层50的陷阱点密度优选尽可能高。此外,存储节点层50由比之后描述的隧道氧化层48和阻挡氧化层52高的介电常数和更低的能带差的材料形成。因此,存储节点层50是由具有比隧道氧化层48和阻挡氧化层52更高俘获密度的材料形成。这里,能带差是指价带和费米能级之间的差距。基于上述考虑,存储节点层50可以是金属氧化物(MO)层、N-基金属氮氧化物(MON)层、金属氮氧化硅(MSiON)层。在MO层、MON层和MSiON层中,M代表金属材料、例如Hf、Zr、Ta、Ti或镧系元素(Ln)。Ln是La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb或Lu。最优选,存储节点层50是HfO2层。存储节点层50可以形成至厚度约5-25nm。
阻挡氧化层52插入存储节点层50和电极层54之间以防止存储节点层50中俘获的电子移动至电极层54。类似隧道氧化层48,阻挡氧化层52可以由比存储节点层50具有更高介电常数和更高能带差的材料形成。例如,阻挡氧化层52可以由氧化铝(Al2O3)形成。阻挡氧化层52可以形成至厚度约5-25nm。
用作栅电极的电极层54可以是用导电杂质离子掺杂的多晶硅层。电极层54可以是另一个导电层,例如硅化钨层。
配置在源和漏区42和44之间的沟道区46根据施加至栅堆叠60的电极层54的电压而打开或关闭。换言之,可以通过施加适当电压至电极层54来转换沟道区46的状态。因此,源和漏区42和44和栅堆叠60构成了开关器件例如晶体管。此外,因为栅堆叠60包括如上所述的存储节点层50,开关器件具有数据存储功能。因此,源和漏区42和44和栅堆叠60构成多功能器件,其同时具有开关功能和存储功能。多功能器件在结构上相当于晶体管,但是由于附加的数据存储功能,可以称为数据存储型或存储型晶体管。
图2中显示的SONOS型存储器的运转如下所述。通过电极层54施加第一预定栅电压Vg至栅堆叠60,并施加第一预定漏电压Vd至漏区44,从而在存储节点层50中存储数据。通过施加第二预定栅电压Vg′(Vg′<Vg)至栅堆叠60,施加第二预定漏电压Vd′(Vd′<Vd)至漏区44,并测定源和漏区42和44之间的电流大小来读出存储数据。
图3图解说明了相对于某些材料的介电常数的带隙;
参考图3,通常具有高介电常数的材料具有低带隙。隧道氧化层(图2的48)和阻挡氧化层(图2的52)可以由具有比SiO2介电常数高的材料例如氧化铝形成。存储节点层(图2的50)可以由具有比构成隧道氧化层48和阻挡氧化层52的氧化铝介电常数高的氧化物形成(例如HfO2)。
图4图解说明了与图2中显示的存储器的编程时间和擦除时间相应的平带电压VFB的变化;
本发明SONOS型存储器中,隧道氧化层48、存储节点层50和阻挡氧化层52是分别由Al2O3、HfO2和Al2O3形成的。为了测量与编程时间和擦除时间相应的平带电压,施加6V的编程电压和-6V的擦除电压至存储器。
参考图4,当编程时间和擦除时间都是1ms时,得到足以满足编程和擦除的约2V的存储窗。也就是说,可以在较短的时间内充分编程和擦除数据。
图5图解说明了图2显示的存储器中数据的保留时间。
参考图5,通过从较短时间段的结果外推,当对本发明存储器施加6V的编程电压和-6V的擦除电压,并且在用于得到图4显示结果的相同条件下编程和擦除时间保持在1ms时,甚至在10年后,平带电压的差值是1.4V。也就是说,本发明SONOS型存储器具有良好的存储特性。
图6图解说明了图2中显示的存储器和传统存储器的存储窗的相对速率。参考图6,ONO是指传统的包括SiO2-Si3N4-SiO2的SONOS型存储器,OHA是指包括SiO2-HfO2-Al2O3的SONOS型存储器,AHA是指包括Al2O3-HfO2-Al2O3的SONOS型存储器。
参考图6,当假定本发明AHA存储器的存储窗是100%时,其它存储器的存储窗小于50%。也就是说,本发明存储器具有比传统存储器更好的存储特性。
尽管本发明的具体实施方式中仅描述了AHA型,但本发明并不限于此。本发明的SONOS型存储器可以包括其能带图具有优良结构的三个高介电绝缘层,例如HfO2-TiO2-HfO2或ZrO2-SrTiO2-ZrO2。
如至今说明的,本发明SONOS型存储器包括由比SiO2介电常数高的Al2O3形成的隧道氧化层和阻挡氧化层,以及由比Al2O3介电常数高的HfO2形成的存储节点层。因此,如图4中可以看到的,可以甚至在低驱动电压(例如6V)下,同时缩短编程时间和擦除时间,从而增加数据处理速度。而且,由图5中可见的,本发明存储器可以具有较长的保留时间。因此,本发明可以有助于改善存储器件的集成密度。
虽然参考示范性具体实施方式已经详细显示和描述了本发明,在不脱离所附权利要求定义的本发明精神和范围情况下的多种形式和细节的变化是本领域普通技术人员可以想到的。
Claims (7)
1.一种硅氧化物氮化物氧化物半导体(SONOS)型存储器件,其包括:
半导体衬底;
配置在半导体衬底中的第一杂质区和第二杂质区,第一杂质区和第二杂质区用预定导电性的杂质离子掺杂,并彼此分开预定距离,其中沟道区配置在第一杂质区和第二杂质区之间;和
在第一杂质区和第二杂质区之间的半导体衬底上形成数据存储型堆叠,
其中数据存储型堆叠包括依次形成的隧道氧化层、用于存储数据的存储节点层、阻挡氧化层和电极层,
存储节点层的介电常数高于隧道氧化层的介电常数和阻挡氧化层的介电常数,存储节点层的能带差低于隧道氧化层的能带差和阻挡氧化层的能带差,
并且隧道氧化层和阻挡氧化层是高介电绝缘层。
2.权利要求1的器件,其中隧道氧化层是由介电常数高于二氧化硅(SiO2)的材料形成的。
3.权利要求2的器件,其中隧道氧化层是由氧化铝(Al2O3)形成的。
4.权利要求1-3中任何一项的器件,其中存储节点层选自MO层、MON层和MSiON层(M是金属)。
5.权利要求4的器件,其中M是选自Hf、Zr、Ta、Ti和镧系元素(Ln)的金属,Ln是选自La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb和Lu的金属。
6.权利要求3的器件,其中存储节点层是由HfO2形成的。
7.权利要求6的器件,其中阻挡氧化层是由Al2O3形成的。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR17998/2004 | 2004-03-17 | ||
KR1020040017998A KR100594266B1 (ko) | 2004-03-17 | 2004-03-17 | 소노스 타입 메모리 소자 |
KR17998/04 | 2004-03-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1670958A true CN1670958A (zh) | 2005-09-21 |
CN100502009C CN100502009C (zh) | 2009-06-17 |
Family
ID=34985326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100036659A Expired - Fee Related CN100502009C (zh) | 2004-03-17 | 2005-01-07 | 硅氧化物氮化物氧化物半导体型存储器件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7053448B2 (zh) |
JP (1) | JP4733398B2 (zh) |
KR (1) | KR100594266B1 (zh) |
CN (1) | CN100502009C (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101276844B (zh) * | 2007-03-27 | 2010-06-16 | 株式会社东芝 | 非易失性半导体存储器的存储单元 |
US8044454B2 (en) | 2006-07-05 | 2011-10-25 | Hynix Semiconductor Inc. | Non-volatile memory device |
CN102569088A (zh) * | 2010-12-30 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件结构和制作该半导体器件结构的方法 |
CN103367408A (zh) * | 2013-07-04 | 2013-10-23 | 西安电子科技大学 | 基于硅衬底高介电常数的栅介质材料及其制备方法 |
CN104425576A (zh) * | 2013-09-05 | 2015-03-18 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1487013A3 (en) * | 2003-06-10 | 2006-07-19 | Samsung Electronics Co., Ltd. | SONOS memory device and method of manufacturing the same |
KR100973281B1 (ko) | 2003-06-10 | 2010-07-30 | 삼성전자주식회사 | 소노스 메모리 소자 및 그 제조 방법 |
EP1649501B1 (en) * | 2003-07-30 | 2007-01-03 | Infineon Technologies AG | High-k dielectric film, method of forming the same and related semiconductor device |
US7602009B2 (en) * | 2005-06-16 | 2009-10-13 | Micron Technology, Inc. | Erasable non-volatile memory device using hole trapping in high-K dielectrics |
US20070063252A1 (en) * | 2005-09-16 | 2007-03-22 | Yuan Diana D | Non-volatile memory and SRAM based on resonant tunneling devices |
KR20070053071A (ko) * | 2005-11-19 | 2007-05-23 | 삼성전자주식회사 | 다층의 터널링층을 포함한 비휘발성 메모리 소자 |
JP4965878B2 (ja) * | 2006-03-24 | 2012-07-04 | 株式会社東芝 | 不揮発性半導体メモリ装置 |
US20080017936A1 (en) * | 2006-06-29 | 2008-01-24 | International Business Machines Corporation | Semiconductor device structures (gate stacks) with charge compositions |
KR100759845B1 (ko) * | 2006-09-11 | 2007-09-18 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 이의 제조 방법 |
KR100755410B1 (ko) * | 2006-09-22 | 2007-09-04 | 삼성전자주식회사 | 게이트 구조물 및 이를 형성하는 방법, 비휘발성 메모리장치 및 이의 제조 방법 |
KR100824152B1 (ko) * | 2006-09-29 | 2008-04-21 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
US20080174936A1 (en) * | 2007-01-19 | 2008-07-24 | Western Lights Semiconductor Corp. | Apparatus and Method to Store Electrical Energy |
JP5039396B2 (ja) * | 2007-02-19 | 2012-10-03 | ローム株式会社 | 半導体装置の製造方法 |
KR100877100B1 (ko) * | 2007-04-16 | 2009-01-09 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자 제조 방법 |
US9299568B2 (en) | 2007-05-25 | 2016-03-29 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
US8063434B1 (en) | 2007-05-25 | 2011-11-22 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US8940645B2 (en) | 2007-05-25 | 2015-01-27 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US8643124B2 (en) | 2007-05-25 | 2014-02-04 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
KR100994995B1 (ko) | 2007-08-07 | 2010-11-18 | 삼성전자주식회사 | DySc03 막을 포함하는 반도체 박막의 적층 구조 및 그 형성방법 |
JP2009049300A (ja) * | 2007-08-22 | 2009-03-05 | Toshiba Corp | 半導体記憶装置の製造方法 |
US7662693B2 (en) | 2007-09-26 | 2010-02-16 | Micron Technology, Inc. | Lanthanide dielectric with controlled interfaces |
US20090152621A1 (en) * | 2007-12-12 | 2009-06-18 | Igor Polishchuk | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
US9431549B2 (en) | 2007-12-12 | 2016-08-30 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
JP2009152498A (ja) * | 2007-12-21 | 2009-07-09 | Toshiba Corp | 不揮発性半導体メモリ |
JP5208538B2 (ja) | 2008-02-21 | 2013-06-12 | 株式会社東芝 | 半導体記憶素子 |
JP5210675B2 (ja) | 2008-03-19 | 2013-06-12 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US8471328B2 (en) | 2010-07-26 | 2013-06-25 | United Microelectronics Corp. | Non-volatile memory and manufacturing method thereof |
US8570809B2 (en) | 2011-12-02 | 2013-10-29 | Cypress Semiconductor Corp. | Flash memory devices and systems |
US8685813B2 (en) | 2012-02-15 | 2014-04-01 | Cypress Semiconductor Corporation | Method of integrating a charge-trapping gate stack into a CMOS flow |
US10720444B2 (en) | 2018-08-20 | 2020-07-21 | Sandisk Technologies Llc | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same |
CN114175252A (zh) * | 2019-07-19 | 2022-03-11 | 恩特格里斯公司 | 具有减少的热预算的三维nand存储器 |
US11670715B2 (en) * | 2021-08-27 | 2023-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices with ferroelectric layer and methods of manufacturing thereof |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5834978A (ja) * | 1981-08-26 | 1983-03-01 | Matsushita Electronics Corp | 半導体記憶装置 |
MXPA03001223A (es) * | 2000-08-11 | 2003-09-22 | Infineon Technologies Ag | Celda de memoria, dispositivo de celda de memoria y metodo de fabricaccion del mismo. |
US6858899B2 (en) * | 2002-10-15 | 2005-02-22 | Matrix Semiconductor, Inc. | Thin film transistor with metal oxide layer and method of making same |
JP2004214506A (ja) * | 2003-01-07 | 2004-07-29 | Sony Corp | 不揮発性半導体メモリ装置の動作方法 |
KR100601914B1 (ko) | 2003-12-31 | 2006-07-14 | 동부일렉트로닉스 주식회사 | 반도체 소자 |
JP2005294791A (ja) * | 2004-03-09 | 2005-10-20 | Nec Corp | 不揮発性メモリ及び不揮発性メモリの製造方法 |
-
2004
- 2004-03-17 KR KR1020040017998A patent/KR100594266B1/ko not_active IP Right Cessation
-
2005
- 2005-01-07 CN CNB2005100036659A patent/CN100502009C/zh not_active Expired - Fee Related
- 2005-01-26 JP JP2005018224A patent/JP4733398B2/ja not_active Expired - Fee Related
- 2005-03-03 US US11/070,090 patent/US7053448B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8044454B2 (en) | 2006-07-05 | 2011-10-25 | Hynix Semiconductor Inc. | Non-volatile memory device |
CN101276844B (zh) * | 2007-03-27 | 2010-06-16 | 株式会社东芝 | 非易失性半导体存储器的存储单元 |
CN102569088A (zh) * | 2010-12-30 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件结构和制作该半导体器件结构的方法 |
CN102569088B (zh) * | 2010-12-30 | 2014-06-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件结构和制作该半导体器件结构的方法 |
CN103367408A (zh) * | 2013-07-04 | 2013-10-23 | 西安电子科技大学 | 基于硅衬底高介电常数的栅介质材料及其制备方法 |
CN103367408B (zh) * | 2013-07-04 | 2016-03-02 | 西安电子科技大学 | 基于硅衬底高介电常数的栅介质材料及其制备方法 |
CN104425576A (zh) * | 2013-09-05 | 2015-03-18 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
CN104425576B (zh) * | 2013-09-05 | 2019-04-05 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2005268756A (ja) | 2005-09-29 |
CN100502009C (zh) | 2009-06-17 |
KR20050092880A (ko) | 2005-09-23 |
JP4733398B2 (ja) | 2011-07-27 |
US7053448B2 (en) | 2006-05-30 |
KR100594266B1 (ko) | 2006-06-30 |
US20050205920A1 (en) | 2005-09-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1670958A (zh) | 硅氧化物氮化物氧化物半导体型存储器件 | |
US6858899B2 (en) | Thin film transistor with metal oxide layer and method of making same | |
US7737488B2 (en) | Blocking dielectric engineered charge trapping memory cell with high speed erase | |
TWI621215B (zh) | 快閃記憶體結構及其製造方法 | |
CN1691333A (zh) | 具有介电多层结构的存储器件及其制造方法 | |
KR100812933B1 (ko) | Sonos 구조를 갖는 반도체 메모리 소자 및 그것의제조 방법 | |
JP2006114905A (ja) | 不揮発性の半導体メモリ素子 | |
CN1841683A (zh) | 制造存储器件的方法 | |
US20140159137A1 (en) | Gate structure in non-volatile memory device | |
CN1761073A (zh) | 包括多层隧道势垒的非易失存储器件及其制造方法 | |
CN1571161A (zh) | 非易失性半导体存储器件及其制造方法 | |
CN1656596A (zh) | 以减少远处散射的栅极氧化制造高性能金属氧化物半导体晶体管的方法 | |
CN1883046A (zh) | 电荷捕获存储器件以及用于操作和制造该单元的方法 | |
US20210005733A1 (en) | Storage memory device | |
US20050205923A1 (en) | Non-volatile memory device having an asymmetrical gate dielectric layer and method of manufacturing the same | |
US20080185633A1 (en) | Charge trap memory device with blocking insulating layer having higher-dielectric constant and larger energy band-gap and method of manufacturing the same | |
US8975687B2 (en) | Nonvolatile memory array with continuous charge storage dielectric stack | |
CN1855512A (zh) | 非易失性存储器件及其制造方法 | |
US7294547B1 (en) | SONOS memory cell having a graded high-K dielectric | |
CN1638130A (zh) | 半导体存储器及其制造方法 | |
CN1433577A (zh) | 集成在半导体上的存储单元结构 | |
US7994562B2 (en) | Memory apparatus | |
US20140217492A1 (en) | Charge-trap type flash memory device having low-high-low energy band structure as trapping layer | |
CN1157793C (zh) | 嵌入式快闪存储器及其操作方法 | |
CN100347833C (zh) | 在一个加工步骤中形成不同厚度的高质量氧化物层的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090617 Termination date: 20140107 |