CN1582499A - 高k介电薄膜及其制造方法 - Google Patents

高k介电薄膜及其制造方法 Download PDF

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CN1582499A
CN1582499A CNA018229344A CN01822934A CN1582499A CN 1582499 A CN1582499 A CN 1582499A CN A018229344 A CNA018229344 A CN A018229344A CN 01822934 A CN01822934 A CN 01822934A CN 1582499 A CN1582499 A CN 1582499A
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dielectric layer
semiconductor structure
interbed
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aluminium
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CN100407439C (zh
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维迪亚S.考希克
比奇-延·源
斯里尼瓦斯V·皮耶塔姆巴拉姆
詹姆斯·肯尼恩·Ⅲ·谢恩
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NXP USA Inc
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Abstract

介电层包括镧、铝和氧，并形成在两个导体之间或导体和衬底之间。在一个实施例中，介电层对镧或铝进行分级。在另一实施例中，在导体或衬底与介电层间形成绝缘层。介电层可通过原子层化学汽相淀积、物理汽相淀积、有机金属化学汽相淀积或脉冲激光淀积形成。

Description

高K介电薄膜及其制造方法
技术领域
本发明涉及用在制造集成电路中的设备及用于制造集成电路的方法，更具体地说，涉及用在制造集成电路中的高K电介质。
背景技术
到目前为止，二氧化硅已经是用在制造集成电路中的最通用和最有效的绝缘体。这具有非常高的集成度，以及特别地，能用非常低的缺陷密度制造。结果是，在低泄漏中二氧化硅能够工作地非常有效。关于栅极电介质，该电介质所需的特征之一是将上覆(overlying)栅极耦合到下面的(underlying)沟道以使该沟道对应用于该栅极上的激源(stimulus)起作用。在这点上，需要那个电介质具有高的、通常被称为K的介电常数。
当前，在开发具有高于二氧化硅的介电常数的高K电介质方面正在做许多工作。二氧化硅具有多个优点，而其中的一个优点是使它成为高效绝缘体的高带隙。因此，已经发现针对高K目的而开发的许多材料都具有问题，因为它们不具有足够高的带隙或者因为它们难以产生足够的完整性来防止通过该电介质发生电流泄漏。
高K电介质所需的一个特征在于它是非晶(amorphous)的。在其整个使用寿命，包括制造期间和随后的使其成为完整的集成电路部分的功能操作期间，它都必须保持非晶形。许多高K电介质在淀积时都具有足够高的K以及足够的完整性，但经过随后的处理步骤以及与此有关的加热，结果是使这些薄膜结晶。如此结晶的这些薄膜并不是在它们的整个长度和宽度完全结晶，而是在形成结晶结构间具有被称为晶界(grain boundary)的区域。这些晶界是泄漏和其它影响电性能的问题的区域。
可以用单晶薄膜来替代非晶形。理论上，通常将这些薄膜制成单晶体。对此存在几个问题。一个是像将其实际上完全形成的形成过程期间一样，将该薄膜的晶体结构与下面半导体(通常是硅)的晶体结构匹配。单晶层的外延层是在本行业中公知的。可将硅制成外延的。与其它淀积过程相比，这些外延过程通常相对较慢。一种能以单晶形式放下非常小的薄膜的技术是分子束外延技术。这种方法的问题在于它太慢，以致与诸如CVD的传统淀积过程相比，生产量太低，也即每时间周期内生产的晶片数量的太少。因此，通常不将分子束外延(MBE)视为可制造技术。即使使用MBE技术，仍然很难确保缺陷游离薄膜。为实现此，压力必须极其低而且过程要非常慢。一个非常薄的层，即厚度为10至30埃的层，能在MBE机上轻易地花费掉2个小时。
在开发新的高K电介质的过程中，还有另外一个潜在问题：具有的介电常数太高。如果介电常数太高，存在一种被称为弥散场效应的效应，能逆向地影响晶体管的性能。这就必须利用栅极和源/漏极间的过耦合。因此，所需开发的材料的介电常数通常在20到40之间的范围。该范围可根据该技术的进一步开发而稍微改变。
所需高K电介质的另一方面是根据其等效于二氧化硅的一定厚度的等效电容。二氧化硅已经得到了非常广泛和有效的使用，以致它已经成为标准，并且该行业通常根据其与二氧化硅的关系来描述某一特征。在这种情况下，典型所需的二氧化硅等效于5到15埃之间，但通过5到15埃的二氧化硅，其具有泄漏、可靠性和增长率的问题。因此，当薄膜那么小时，在制造它及使用它中会有困难。所需耦合是具有这样的电介质：该电介质具有二氧化硅的5至15埃的等效厚度，但实际厚度更大。通常视为所需的实际最小厚度是约25埃。因此，需要具有在所需范围内的介电常数、用高完整性制成的能力、在所需范围内的厚度以及在制造过程中制造的能力的介电薄膜。
附图的简单描述
图1是根据本发明的第一实施例的集成电路一部分的横截面；
图2是根据本发明的第二实施例的集成电路一部分的横截面；
图3是根据本发明的第三实施例的集成电路一部分的横截面；
图4是根据本发明的第四实施例的集成电路一部分的横截面；
图5是根据本发明的第五实施例的集成电路一部分的横截面；
图6是根据本发明的第六实施例的集成电路一部分的横截面。
发明描述
包括镧、铝和氧化物在内的高K介电薄膜提供出色的高K材料。它组合了具有所需介电常数范围、能够在高温时保持非晶能力等优点，并提供低泄漏。
图1所示的是具有半导体材料的衬底12、介电薄膜14和导电薄膜16的集成电路的一部分10。衬底12在其至少一个表面上具有半导体区。未示出的基础部分可以也是半导体材料或者可以是典型用于SOI的绝缘材料。半导体材料的例子包括单晶硅、砷化镓、硅锗合金以及锗。在衬底12上为介电层14。在介电层14上是充当栅电极的导电薄膜16。介电层14操作为栅极绝缘体或栅极电介质。在靠近与介电薄膜14相接的表面的区域上所示的衬底12是晶体管的沟道。
栅极电介质14包括镧铝合金，它是由镧、铝和氧组成的化合物。当铝和镧的浓度相同时，书写为LaAlO3。最好使用原子层化学汽相淀积(ALCVD)形成栅极电介质14。可使用的其它方法包括物理汽相淀积、有机金属化学汽相淀积以及脉冲激光淀积。ALVCD方法允许精确控制包括厚度在内的层的形成，在这种情况下，厚度不小于约25埃并且最好在30至90埃的范围内。当前集成电路技术中的栅极导体16典型地是多晶硅，但也可以是其它导体，诸如钨、氮化钛、氮化钽或可用作栅极导体的任何导体。
通过ALVCD淀积的栅极电介质14也可用于确保在非晶状态下淀积薄膜。使用当前的ALCVD技术，典型的温度范围为200-400度，压力在0.1至10托之间，1.0托是对于ALCVD的通用选择。选择温度和压力以确保栅极电介质14的非晶状态。在ALCVD过程中，在一个周期的不同时间引入铝和镧，以及氧气源。每种材料在周期中具有其自己的点，在该点，由于与现有层反应的结果，将其引入并淀积，然后抽空并净化。随后，引入其它材料，与现有层反应并通过净化去除。然后，引入第三种材料从而反应和净化。因此，一个完成的周期是所有三种材料，但处于周期中的不同点和时间。也可以看出，可以是铝，然后是氧气、镧，然后氧气，铝，然后氧气等等。因此，每个其它步骤将是引入氧气源。因此，在一种意义上，每次材料的引入都是淀积层。在这种情况下，每个完整的周期由一层镧、一层铝以及两层氧这四个淀积层组成以便逐层淀积，但最终四层将视为两个金属氧化物层，一个铝/氧以及另一个为镧/氧。因此，这两层包含一个镧铝合金的单层。
该镧铝合金在优化介电系数和低泄漏的区域中提供许多好处。一些其它的材料具有可识别的缺陷。例如，氧化镧具有处在正确范围内的介电常数但它吸收水。对所需的集成电路的制造来说，吸引水是非常有害的。例如，氧化镧的吸水会导致结构完整性问题。它会变得软，将使其不能用于形成集成电路结构。例如，氧化铝存在具有两个低介电常数的问题。氧化铝的介电常数稍微高于氧化硅，但不足以使其用于连续定标。因此，存在一些单独的过程几何结构，对这些几何结构，可使用氧化铝，但由于尺寸变得更小，随后的生产将不能进行。
镧铝合金的另一好处在于可根据镧含量的范围改变介电常数。因此，可获得约在10和25之间的优化介电常数。甚至能获得稍微大些的系数，其中镧含量甚至大于铝含量，但这可能会导致与水吸收有关的问题。
即使在温度高达1,025度和可能甚至更高的情况下，镧铝合金也有利地保持非晶。1,025摄氏度是用于当前过程的典型的最高温度。已经发现镧铝合金承受最高温度并保持非晶，该最高温度将在对最先进的几何结构的许多典型处理所进行的集成电路的处理期间接收。期望最大处理温度下降一些，但最大温度将很可能保持相当高，因为活化源/漏极中的掺杂剂要求高温并且这种活化是被期望用于预测未来的。最大温度可下降到稍微低于1,025，但仍然期望至少在相当长的一段时间内高于900摄氏度。但是，并不是必然将发生显著的降温，在相当长的一段时间内，1,025将继续是有效的要求。因此，非晶镧铝合金在预期温度范围上提供了所需的高K特性以及高完整性。
能淀积非晶镧铝合金的有效高K介电薄膜的另一好处在于，其不仅在硅上，而且在砷化镓上也能非常有效。在有效实现砷化镓及其较高迁移率的优点中的一个问题在于，用在砷化镓中的栅极电介质很难与通过在高温生长氧化硅获得的硅的栅极电介质的完整性匹配。因此，在大多数应用中，已经证明硅优于砷化镓。现在通过使用ALCVD淀积的有效高K介电质，结果是：在硅、砷化镓或某些其它半导体材料上淀积，栅极电介质都可以具有高完整性，。该结果说明砷化镓将变成用于大多数集成电路的最优选择而不仅仅是当今半导体市场中的适合的选择。
图2所示的是包括衬底20、阻挡层电介质(barrier dielectric)22、高K电介质24以及半导体26的集成电路的一部分18。在这种情况下，高K介电质24与图1的薄膜14相像或类似之处在于它是镧铝合金。导体26类似于导体16，衬底20类似于图1中的衬底12。由于其所需特性，选择也可被称为间层(interfacial layer)的阻挡层电介质22作为绝缘体。例如，其可能是氧化铝、氧化硅或氮氧化硅。对于这种情况，氧化铝是特别好的选择，因为它具有良好的绝缘特性并且具有稍微高于氧化硅的介电常数。提供阻挡层电介质22可以确保高K电介质24与阻挡层电介质22的组合具有足够的绝缘特性来防止不希望的电流。例如，该组合将具有高带隙并且将具有足够高的介电常数。特别地，这使得高带隙材料直接与作为电子注入的电势源的衬底20相接触。如果选择用于衬底20的材料具有镧铝合金的问题，那么对阻挡层电介质22的另一种可能的使用是将其作为扩散阻挡层。
图3所示的为由衬底30、介电薄膜32以及导体34组成的集成电路的一部分28。在这种情况下，衬底30类似于衬底20和12，导体34类似于导体26和16。介电薄膜32代替了电介质14和电介质22与24的组合。在这种情况下，介电薄膜32具有镧的分级浓度。在介电薄膜32中，在与衬底30的接触面附近，该材料基本上是纯氧化铝。在移向导体34过程中，镧浓度持续增加，直到在接触面附近以及在与导体34的接触面处的介电薄膜32中，铝和镧达到1比1的比率为止。这种方法的好处在于在几乎紧挨衬底30处提供所需高带隙从而避免氧化铝和镧铝合金间的任何突变接触面。也可通过控制浓度增长的速率来调整最终的介电常数，即在与导体34的接触面之前，能很好地实现铝和镧间1比1的比率。用于分级的另一种替代方案是继续超过1比1的比率以使镧的浓度超过铝的浓度。
在使用ALCVD的情况下，淀积的初相将不包括镧。第一层将仅为铝和氧，从而可继续所需的多层并且镧可以以一个增长的速率来代替铝，直到镧和铝间达到1比1的比率为止。实际上，可期望获得高于铝浓度的镧浓度。风险在于：如果镧太多，而在提供较高介电常数中的较高镧浓度的好处在于可提供实际上期望镧多于铝的情况，那么这将会降低薄膜的质量。在这种情况下，在最接近导体34的接触面，在浓度方面，镧将高于铝。
图4所示的为由衬底34、阻挡层电介质36、高K电介质38、阻挡层电介质40和导体42组成的集成电路的一部分32。在这种情况下，衬底34类似于衬底12、20和30。阻挡层电介质36类似于阻挡层22。高K电介质38类似于高K电介质14和24。导体24类似于导体16、26和34。阻挡层40在高K电介质38和导体42间提供阻挡。阻挡层40用于导体42具有与高K电介质38兼容问题的情况。同样最有可能在氧化铝、氧化硅以及氮氧化硅中选择阻挡层40。阻挡层电介质40的目的将是在导体42和高K电介质38间提供扩散阻挡。当然，将期望阻挡层40具有高介电常数，但其目的是防止导体42和高K电介质38间的问题。最优选择很可能是氧化铝，因为它具有高于氧化硅的介电常数。
图5所示是由导体46、高K电介质48以及导体50组成的集成电路的一部分44。在这种情况下，高K电介质适合处于两个导体之间。这主要出现在导体46是用于存储电荷的浮栅的情况中。这也可发生在46和50由用于存储电荷的电容偏板组成的情况中。一个这种例子是动态随机存取存储器的存储单元。在这种情况下，也期望高K电介质48具有高介电常数以及具有所需的低泄漏特性。
如图5所示，高K电介质48是具有分级浓度的镧铝合金。在中间最大化镧的浓度，而在与导体46的接触面处以及在导体50的接触面处为纯的或几乎纯的氧化铝。这在与导体46的接触面以及与导体50的接触面处提供了相对高的介电常数以及高带隙，以便它成为高K电介质和良好的绝缘体。通过给高K电介质48分级，避免了绝缘体类型间的急剧接触面。材料类型间的急剧过渡有助于截留电荷的位置。通过浓度分级，避免了急剧接触面。在晶体管的情况下，最重要的是在仅仅挨着衬底的位置要具有高带隙，因为在该处可能注入电荷，而在部分44的情况中，可从导体50或导体46注入电荷。因此，期望在与导体50和导体46的接触面处具有高带隙。
图6所示为由导体54、阻挡层电介质56、高K电介质58、阻挡层电介质60以及导体62组成的集成电路的一部分52。其类似于图5的结构。导体54类似于导体46，导体62类似于导体50，层56、58和60的组合类似于图5中的高K电介质48。在图6的情况中，同时操作介电层56和60以提供高带隙以及作为导体62和54与高K电介质58间的扩散阻挡层。因此，增加阻挡层56和60对于足够的绝缘质量和向高K电介质58提供扩散阻挡层来说均是必要的。导体54和62可具有不同特性。一种可是多晶硅。另一种可是金属，在其中情况下，阻挡层电介质的类型可期望是不同的。高K电介质58包括镧铝合金，具有用于图1-5的衬底的薄膜的镧铝合金所述的好处。
在两个导体不同于晶体管的形成的情况下，需要阻挡层的可能性增加了，因为实际上，在某些情况下，期望在导体2和54间出现注入。因此，需要阻挡层56和60或如图5中的分级的可能性(以使当不期望这种注入发生时就不会发生)将很可能是实际上发生的情况。因此，需要阻挡层56和60或图5所示的分级的可能性大于通过注入存储电荷的情况。同样，在完全充当电容器的情况下，仍然更有可能需要阻挡层56和60。电容器的主要目的是存储电荷以使在导体的接触面处具有高带隙的重要性甚至将比用于晶体管更重要。
尽管在不同的实施例中已经描述了该发明，但是也可以有可用在组合中的其它实施例以及其它材料，它们将提供与本发明有关的好处或其中的一些好处。除所提及的那些材料之外，也可使用其它材料。此外，也可增加材料到镧铝合金中，除由所述的组合中的镧铝合金和不同浓度提供的好处之外，还可提供其它的好处。因此，权利要求书限定本发明的范围。

Claims (26)

1、一种半导体结构，其包括：
半导体衬底；
介电层，其包括在所述半导体衬底上的镧、铝和氧；和
在所述介电层上的电极层。
2、如权利要求1所述的半导体结构，其进一步包括在所述半导体衬底和所述介电层之间的间层。
3、如权利要求2所述的半导体结构，其中，所述间层包括从硅、氮、氧和铝组成的组中选择的元素。
4、如权利要求2所述的半导体结构，其进一步包括在所述介电层和所述电极层之间的间层。
5、如权利要求4所述的半导体结构，其中，所述间层包括从由硅、氮、氧和铝组成的组中选择的元素。
6、如权利要求1所述的半导体结构，其中，所述介电层是镧铝合金。
7、如权利要求1所述的半导体结构，其中，所述介电层是非晶的。
8、如权利要求1所述的半导体结构，其中，所述半导体衬底是从单晶硅、砷化镓、绝缘体上外延硅、硅锗以及锗组成的组中选择的。
9、如权利要求1所述的半导体结构，其中，所述电极层是栅电极。
10、如权利要求1所述的半导体结构，其中，所述介电层的一个元素是从0到高于0的一个预定量分级的。
11、如权利要求10所述的半导体结构，其中，所述预定量是化学计量。
12、一种半导体结构，其包括：
第一导电层；
介电层，其包括在所述第一导电层上的镧、铝和氧；和
在所述介电层上的第二导电层。
13、如权利要求12所述的半导体结构，其中，所述第二导电层是浮栅。
14、如权利要求12所述的半导体结构，其中，所述介电层是镧铝合金。
15、如权利要求12所述的半导体结构，其中，所述介电层是非晶的。
16、如权利要求12所述的半导体结构，其进一步包括：
第一间层，位于所述第一导电层和所述介电层之间；和
第二间层，位于所述介电层和所述第二导电层之间。
17、如权利要求16所述的半导体结构，其中，所述第一间层包括从由硅、氮、氧和铝组成的组中选择的元素。
18、如权利要求16所述的半导体结构，其中，所述第二间层包括从由硅、氮、氧和铝组成的组中选择的元素。
19、如权利要求16所述的半导体结构，其中，所述第一间层和所述第二间层为相同的材料。
20、如权利要求12所述的半导体结构，其中，所述介电层从所述第一间层和所述第二间层都从0到一个预定量分级。
21、如权利要求20所述的半导体结构，其中，所述预定量是化学计量。
22、一种用于形成半导体结构的方法，其包括：
在半导体衬底上形成由镧、铝以及氧组成的介电层；和
在所述介电层上形成电极层。
23、如权利要求22所述的方法，其中，所述介电层是通过原子层化学汽相淀积、物理汽相淀积、有机金属化学汽相淀积或脉冲激光淀积形成的。
24、如权利要求22所述的方法，其进一步包括在所述半导体衬底和所述介电层之间形成间层。
25、如权利要求22所述的方法，其进一步包括在所述介电层上，在所述介电层和电极层之间形成间层。
26、一种半导体装置，包括：
从具有半导体表面和导电层的衬底中选择的第一材料；
第二材料，所述第二材料是导电的层；
第三材料，位于所述第一和第二材料之间，并包括镧、铝和氧，其中，所述第二材料是非晶的。
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