US20090039414A1 - Charge trapping memory cell with high speed erase - Google Patents

Charge trapping memory cell with high speed erase Download PDF

Info

Publication number
US20090039414A1
US20090039414A1 US11/845,276 US84527607A US2009039414A1 US 20090039414 A1 US20090039414 A1 US 20090039414A1 US 84527607 A US84527607 A US 84527607A US 2009039414 A1 US2009039414 A1 US 2009039414A1
Authority
US
United States
Prior art keywords
dielectric layer
layer
memory
tunneling
less
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/845,276
Inventor
Hang Ting Lue
Sheng-Chih Lai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US95482007P priority Critical
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Priority to US11/845,276 priority patent/US20090039414A1/en
Assigned to MACRONIX INTERNATIONAL CO., LTD. reassignment MACRONIX INTERNATIONAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAI, SHENG-CHIH, LUE, HANG-TING
Priority claimed from TW97100251A external-priority patent/TWI374448B/en
Priority claimed from EP08152406A external-priority patent/EP2026384A3/en
Publication of US20090039414A1 publication Critical patent/US20090039414A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28282Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268 comprising a charge trapping insulator
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • The benefit of U.S. Provisional Patent Application No. 60/955,391, filed on 13 Aug. 2007, is hereby claimed.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to flash memory technology, and more particularly to scalable charge trapping memory technology adaptable for high speed erase and program operations.
  • 2. Description of Related Art
  • Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference like that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
  • The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunnel dielectric layer, the charge storage layer, and a blocking dielectric layer. According to the early conventional designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S). The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping. In order to achieve practical operational speeds for the erase operation, the tunneling dielectric layer must be quite thin (less than 30 Å). However at that thickness, the endurance and charge retention characteristics of the memory cell are poor relative to traditional floating gate technology. Also, with relatively thick tunneling dielectric layers, the electric field required for the erase operation also cause electron injection from the gate through the blocking dielectric layer. This electron injection causes an erase saturation condition in which the charge level in the charge trapping device converges on an equilibrium level. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al. However, if the erase saturation level is too high, the cell cannot be erased at all, or the threshold margin between the programmed and erased states becomes too small for many applications.
  • On one hand, technology has been investigated to improve the ability of the blocking dielectric layer to reduce electron injection from the gate for the high electric fields needed for erase. See, U.S. Pat. No. 6,912,163, entitled “Memory Device Having High Work Function Gate and Method of Erasing Same,” Invented by Zheng et al., issued 28 Jun. 2005; and U.S. Pat. No. 7,164,603, entitled “Operation Scheme with High Work Function Gate and Charge Balancing for Charge Trapping Non-Volatile Memory”, invented by Shih et al., Shin et al., “A Highly Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,” IEDM, 2003 (MANOS); and Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs”, IEEE 2005. In the just-cited references, the second Shin et al. article describes a SONOS type memory cell in which the gate is implemented using tantalum nitride and the blocking dielectric layer is implemented using aluminum oxide (referred to as the TANOS device), which maintains a relatively thick tunneling dielectric layer at about 4 nm. The relatively high work function of tantalum nitride inhibits electron injection through the gate, and the high dielectric constant of aluminum oxide reduces the magnitude of the electric field through the blocking dielectric layer relative to the electric field for the tunneling dielectric layer. Shin et al. report a trade-off between the breakdown voltage of the memory cell, the thickness of the aluminum oxide layer and the thickness of the tunneling dielectric layer. With a 4 nm thick silicon dioxide tunneling dielectric in a TANOS device, relatively high erase voltages are proposed in order to achieve erase speeds. An increase in erase speeds would require increasing the voltages applied or decreasing the thickness of the tunneling dielectric layer. Increasing the voltage applied for erase is limited by the breakdown voltage. Decreasing the thickness of the tunneling dielectric layer is limited by issues of charge retention and erase saturation, as mentioned above.
  • On the other hand, technology has been investigated to improve the performance of the tunneling dielectric layer for erase at lower electric fields. See, U.S. Patent Application Publication No. US 2006/0198189 A1, “Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operating Cells and Arrays,” Invented by Lue et al., publication date Sep. 7, 2006 (describing a “BE-SONOS device”); Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability”, IEEE, December 2005; Wang et al., “Reliability and Processing Effects of the Bandgap Engineered SONOS (BE-SONOS) Flash Memory”, IEEE, May 2007. See also, U.S. Patent Application Publication No. 2006/0261401 A1, entitled “Novel Low Power Non-Volatile Memory and Gate Stack”, by Bhattacharyya, published 23 Nov. 2006.
  • BE-SONOS technology has been proven to provide excellent performance, overcoming many of the erase speed, endurance and charge retention issues of prior art SONOS type memory. However, the problem of the erase saturation continues to limit operational parameters of the device. Furthermore, as the device sizes shrink, it is expected that erase saturation problems will intensify. Accordingly, is desirable to provide a new memory technology which overcomes the erase saturation issues of prior art technologies, and that can be applied in very small memory devices.
  • SUMMARY OF THE INVENTION
  • A band gap engineered, charge trapping memory cell is described including a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant κ, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. The engineered tunneling dielectric includes a combination of materials having negligible charge trapping efficiency, and band offset characteristics. The band offset characteristics include a relatively large hole tunneling barrier height in a thin region at the interface with the semiconductor body, and an increase in valence band energy level so that the hole tunneling barrier height at a first offset less than 2 nm for example from the channel surface, from the interface is relatively low. The band offset characteristics also include an increase in conduction band energy by providing a thin layer of relatively high electron tunneling barrier height at a second offset more than 2 nm from the channel surface, separating the material with a relatively lower hole tunneling barrier height from the charge trapping layer. Very fast erase speed is obtained using the memory cell described herein, without erase saturation, providing a memory window and operating speed much greater than possible in prior art technologies.
  • The valence band energy level at the first offset is such that an electric field sufficient to induce hole tunneling through the thin region between the interface with the semiconductor body and the offset, is also sufficient to raise the valence band energy level after the offset to a level that effectively eliminates the hole tunneling barrier in the engineered tunneling dielectric after the offset. This structure enables electric field assisted hole tunneling at high speeds while effectively preventing charge leakage through the engineered tunneling dielectric in the absence of electric fields or in the presence of smaller electric fields induced for the purpose of other operations, such as reading data from the cell or programming adjacent cells.
  • In a representative device, the engineered tunneling dielectric layer consists of an ultrathin silicon oxide layer O1 (e.g. <=15 Å), an ultrathin silicon nitride layer N1 (e.g. <=30 Å) and an ultrathin silicon oxide layer O2 (e.g. <=30 Å), which results in an increase in the valence band energy level of about 2.6 eV at an offset 15 Å or less, from the interface with the semiconductor body. The O2 layer separates the N1 layer from the charge trapping layer, at a second offset (e.g. about 35 to 45 A from the interface), by a region of lower valence band energy level (higher hole tunneling barrier). The electric field sufficient to induce hole tunneling between the interface and the first offset also raises the valence band energy level after the second offset to a level that effectively eliminates the hole tunneling barrier, because the second offset is at a greater distance from the interface. Therefore, the O2 layer does not significantly interfere with the electric field assisted hole tunneling, while improving the ability of the engineered tunneling dielectric to block leakage during low fields.
  • The blocking dielectric structure in a representative memory device, consists of aluminum oxide which has a dielectric constant (K about 7 or 8) about twice that of silicon dioxide. Therefore, the electric field intensity in the blocking dielectric structure is relatively low compared to that in the tunneling dielectric layer.
  • The present technology combines techniques for reducing the electric field in the blocking dielectric layer relative to the tunneling dielectric layer, with techniques for reducing the magnitude of the electric field required for erase to achieve high speed erase operations without saturation, enabling a large memory window compared to prior devices. Also, charge retention and endurance characteristics of the memory cell are very good.
  • A charge trapping memory is described based on this technology that includes an array of memory cells. The memory cells include a semiconductor body having a channel with a channel surface and source and drain terminals adjacent the channel. The tunneling dielectric layer lies on the channel surface, and is characterized by negligible charge trapping efficiency and band offset technology. A charge trapping dielectric layer lies on the tunneling dielectric layer. A blocking dielectric layer lies on the charge trapping layer. The blocking dielectric layer comprises a material having a dielectric constant κ greater than 3.9, and preferably comprises aluminum oxide or other material having a dielectric constant κ of about 7 or higher. The gate lies on the blocking dielectric layer. The gate comprises a metal or other conductive material on the blocking dielectric layer. Embodiments of the technology can employ a material for the gate such as platinum, which has a relatively high work function, i.e. greater than 4.5 eV.
  • Circuitry is coupled to the array of memory cells to apply bias voltages to selected memory cells for read, program and erase operations.
  • In the technology described herein, the bias voltages across the gate and substrate of the device are 20 V or less, well below breakdown voltages for erase operations, and demonstrate threshold shifts supporting a memory window of as much as 7 V or more. In addition, for the device described herein, the bias voltages applied during erase operations induce an electric field less than 14 MV/cm across the dielectric tunneling layer, and accomplish a threshold shift of greater than 5 V in less than 10 ms, without erase saturation. Circuitry can be implemented in combination with the charge trapping memory cell described herein to accomplish a negative threshold shift of greater than 5 V in less than 1 ms without erase saturation. Erase speeds of less than 10 ms can be accomplished using bias voltages less than 15 V, enabling the implementation of very small scale devices that have relatively low breakdown voltages.
  • The bias voltages applied during program operations likewise are capable of very fast program operations by electron tunneling through the tunneling dielectric layer, accomplishing in some embodiments a positive threshold shift of greater than 5 V, and as much as 7 V, in less than 1 ms, and in other embodiments in less than 0.1 ms.
  • The memory cell described herein can provide flash technology with a relatively large memory window (greater than 7 V) with excellent data retention. Also, the memory cell described herein should be scalable to 50 nm manufacturing nodes, to 40 nm nodes and below.
  • Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description in the claims which follow.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a simplified diagram of an embodiment of a memory cell according to the present invention.
  • FIG. 2 is a band diagram for a tunneling dielectric layer including band offset technology at a low electric fields.
  • FIG. 3 is a band diagram for a tunneling dielectric layer including band offset technology at high electric fields.
  • FIG. 4 illustrates the electric field intensities during an erase operation for an embodiment of a memory cell according to the present invention.
  • FIG. 5 is a schematic diagram of a NAND-type memory array employing memory cells according to the present invention.
  • FIG. 6 is a simplified cross-sectional view of memory cells according to the present invention in a NAND configuration, taken perpendicular to word lines.
  • FIG. 7 is a simplified cross-sectional view of memory cells according to the present invention in a NAND configuration, taken through a word line.
  • FIG. 8 is a block diagram of an integrated circuit memory employing memory cells and bias circuitry according to embodiments of the present invention.
  • FIG. 9 is a graph of flat band voltage versus erase bias time showing erase curves for various erase bias voltages for an embodiment of a memory cell according to the present invention.
  • FIG. 10 is a graph of flat band voltage versus erase bias time comparing erase curves of other charge trapping cell structures with an erase curve of a memory cell according to the present invention.
  • FIG. 11 is a plot of current density versus electric field in the tunneling dielectric layer using transient analysis for various bias voltages, comparing other charge trapping cell structures with a memory cell according to the present invention.
  • FIG. 12 is a plot of the erase curves of a memory cell according to the present invention with various band offset distances in the tunneling dielectric layer.
  • FIG. 13 is a plot showing program characteristics with various program biases for an embodiment of a memory cell according to the present invention.
  • FIG. 14 is a graph showing erase curves for four representative devices having different gate materials.
  • FIG. 15 is a graph showing transient electric fields in the tunnel layers and blocking layer for three devices described herein.
  • DETAILED DESCRIPTION
  • A detailed description of embodiments of the present invention is provided with reference to the FIGS. 1-15.
  • FIG. 1 is a simplified diagram of a charge trapping memory cell employing a high κ blocking dielectric layer and a band gap engineered dielectric tunneling layer. The memory cell includes a channel 10 in a semiconductor body, and a source 11 and a drain 12 adjacent channel.
  • A gate 18 in this embodiment comprises platinum having a work function of about 8 electron volts eV. Preferred embodiments employ metals or metal compounds for the gate 18, such as platinum, tantalum nitride, aluminum or other metal or metal compound gate materials. It is preferable to use materials having work functions higher than 4.5 eV. A variety of high work function materials suitable for use as a gate terminal are described in U.S. Pat. No. 6,912,163, referred to above. Such materials are typically deposited using sputtering and physical vapor deposition technologies, and can be patterned using reactive ion etching.
  • Embodiments of the memory cell can also employ other metals, such as aluminum, having a work function of about 4.3 eV, as explained in more detail below.
  • In the embodiment illustrated in FIG. 1, the dielectric tunneling layer comprises a composite of materials, including a first layer 13, referred to as a hole tunneling layer, of silicon dioxide on the surface 10 a of the channel 10 formed for example using in-situ steam generation ISSG with optional nitridation by either a post deposition NO anneal or by addition of NO to the ambient during deposition. The thickness of the first layer 13 of silicon dioxide is within the range of about 10 Å to 20 Å, and preferably 15 Å or less.
  • A layer 14, referred to as a band offset layer, of silicon nitride lies on the first layer 13 of silicon oxide formed for example using low-pressure chemical vapor deposition LPCVD, using for example dichlorosilane DCS and NH3 precursors at 680 degrees C. In alternative processes, the band offset layer comprises silicon oxynitride, made using a similar process with an N2O precursor. The thickness of the layer 14 of silicon nitride is within the range of about 10 Å to 30 Å, and preferably 25 Å or less.
  • A second layer 15 of silicon dioxide, referred to as an isolation layer, lies on the layer 14 of silicon nitride formed for example using LPCVD high temperature oxide HTO deposition. The thickness of the second layer 15 of silicon dioxide is less than 30 Å, and preferably 25 Å or less. The structure of the dielectric tunneling layer is described in more detail below with reference to FIGS. 2 and 3.
  • A charge trapping layer 16 in this embodiment comprises silicon nitride having a thickness within the range of about 50 Å to 100 Å, including for example about 70 Å in this embodiment formed for example using LPCVD. Other charge trapping materials and structures may be employed, including for example silicon oxynitride (SixOyNz), silicon-rich nitride, silicon-rich oxide, trapping layers including embedded nano-particles and so on.
  • The blocking dielectric layer 17 in this embodiment comprises aluminum oxide (Al2O3), having a dielectric constant κ of about 8 or more. The layer 17 of aluminum oxide is greater than the thickness of the layer 17 of silicon nitride, including for example at least twice as thick. In illustrated example, the layer 17 of aluminum oxide is within the range of about 50 Å to 150 Å, and for example about 150 Å in the embodiments described herein, formed by atomic vapor deposition AVD with a post deposition rapid thermal anneal at 900° C. for about 60 seconds to strengthen the film. In other embodiments, high κ dielectric material such as hafnium oxide (HfO2) having a κ of about 10, titanium oxide (TiO2) having a κ of about 60, praseodymium oxide (Pr2O3) having a κ of about 30 may be used. Oxides of zirconium Zr and lanthanum La may used as well. In some embodiments, oxides of more than one metal may be used, including for example, oxides of hafnium and aluminum, oxides or zirconium and aluminum, and oxides of hafnium, aluminum and zirconium.
  • In a representative embodiment, the first layer 13 is 13 Å of silicon dioxide; the band offset layer 14 is 20 Å of silicon nitride; the isolation layer 15 is 25 Å of silicon dioxide; the charge trapping layer 16 is 70 Å of silicon nitride; and the blocking dielectric layer 17 is 150 Å of aluminum oxide.
  • FIG. 2 is a diagram of the energy levels of the conduction and valence bands of the dielectric tunneling structure the including the stack of layers 13-15 of FIG. 1 under a low electric field, showing a “U-shaped” conduction band and an “inverted U-shaped” valence band. From the right side, the band gap for the semiconductor body is shown in region 30, the valence and conduction bands for the hole tunneling layer are shown in region 31, the band gap for the offset layer is shown in region 32, the valence and conduction bands for the isolation layer are shown in region 33 and the valence and conduction bands for the charge trapping layer are shown in region 34. Electrons, represented by the circles with the negative sign, trapped within the charge trapping region 34 are unable to tunnel to the conduction band in the channel, because the conduction band of the tunneling dielectric layer in all three regions 31, 32, 33 remains high relative to the energy level of the trap. The likelihood of electron tunneling correlates with the area under the “U-shaped” conduction band in the tunneling dielectric layer and above a horizontal line at the energy level of the trap to the channel. Thus, electron tunneling is very unlikely at low field conditions. Likewise, holes in the valence band of the channel in region 30 are blocked by the full thickness of regions 31, 32 and 33 from tunneling to the charge trapping layer 34, and the high hole tunneling barrier height at the channel interface. The likelihood of hole tunneling correlates with the area over the “inverted U-shaped” valence band in the tunneling dielectric layer and below a horizontal line at the energy level of the channel to the charge trapping layer. Thus, hole tunneling is very unlikely at low field conditions. For the representative embodiment, in which the hole tunneling layer comprises silicon dioxide, a hole tunneling barrier height of about 4.5 eV prevents hole tunneling. The valence band in the silicon nitride remains 1.9 eV below that of the valence band in the channel. Therefore, the valence band in all three layers 31, 32, 33 the tunneling dielectric structure remain significantly below the valence band in the channel 30. The tunneling layer described herein therefore is characterized by band offset characteristics, include a relatively large hole tunneling barrier height in a thin region (layer 31) at the interface with the semiconductor body, and an increase 37 in valence band energy level at a first offset less than 2 nm from the channel surface. The band offset characteristics also include a decrease 38 in valence band energy level at a second offset from the channel by providing a thin layer 33 of relatively high tunneling barrier height material, resulting in the inverted U-shaped valence band shape. Likewise, the conduction band has a U-shape caused by the same selection of materials.
  • FIG. 3 shows the band diagram for the dielectric tunneling structure under conditions of an electric field of about −12 MV/cm in the tunneling layer 31, for the purposes of inducing hole tunneling (in FIG. 3, the O1 layer is about 15 Å thick). Under the electric field the valence band slopes upward from the channel surface. Therefore, at an offset distance from the channel surface the valence band in the tunneling dielectric structure increases in band energy level substantially, and in the illustration rises above the band energy in the valence band in the channel region. Therefore, the hole tunneling probability is increased substantially as the area (shaded in FIG. 3) between the level of the valence band in the channel and above sloped, inverted U-shaped valence band in the tunneling stack is reduced. The band offset effectively eliminates the blocking function of the offset layer in region 32 and isolation layer in region 33 from the tunneling dielectric during high electric field allowing a large hole tunneling current under relatively small electric fields (e.g. E<14 MV/cm).
  • The isolation layer 33 isolates the offset layer 32 from a charge trapping layer 34. This increases the effective blocking capability during low electric field for both electrons and holes, improving charge retention.
  • The offset layer 32 in this embodiment must be thin enough that it has negligible charge trapping efficiency. Also, the offset layer is a dielectric, and not conductive. Thus, for an embodiment employing silicon nitride, the offset layer should be less than 30 Å thick, and more preferably about 25 Å or less.
  • The hole tunneling layer 31, for an embodiment employing silicon dioxide, should be less than 20 Å thick, and more preferably less than 15 Å thick. For example, in a preferred embodiment, the hole tunneling layer 31 is silicon dioxide about 13 Å thick, and exposed to a nitridation process as mentioned above resulting in an ultrathin silicon oxynitride.
  • The tunneling dielectric layer can be implemented in embodiments of the present invention using a composite of silicon oxide, silicon oxynitride and silicon nitride without precise transitions between the layers, so long as the composite results in the required inverted U-shape valence band, having a change in valence band energy level at the offset distance from the channel surface needed for efficient hole tunneling. Also, other combinations of materials could be used to provide band offset technology.
  • The description of the dielectric tunneling layer focuses on “hole tunneling” rather than electron tunneling because the technology has solved the problems associated with the need to rely on hole tunneling in SONOS type memory. For example, a tunnel dielectric consisting of silicon dioxide which is thin enough to support hole tunneling at practical speeds, will be too thin to block leakage by electron tunneling. The effects of the engineering however, also improve performance of electron tunneling. So, both programming by electron tunneling and erasing by hole tunneling are substantially improved using band gap engineering.
  • FIG. 4 is a schematic illustration of the gate stack for a charge trapping memory cell like that FIG. 1, showing electric field dynamics during an erase process. The gate stack includes a hole tunneling layer 43, a band offset layer 44, and an isolation layer 45 which in combination act as the dielectric tunneling layer for the device. A charge trapping layer 46 is shown on the tunneling dielectric layer. A blocking dielectric layer 47 consisting of a high κ insulator such as aluminum oxide separates the charge trapping layer 46 from the metal gate 48. During an erase process, the electric field is induced by bias voltages VG and VW applied at the gate and channel of the memory cell, and results in an electric field ETUN 50 through the dielectric tunneling layer 43, 44, 45 and an electric field EB 51 through the blocking layer 47. The magnitude of the electric field ETUN 50 through the dielectric tunneling layer is sufficient to induce hole tunneling current 52 into the trapping layer 46. The magnitude of the electric field EB 51 through the blocking dielectric layer 47 is reduced relative to that through the silicon dioxide in the tunneling dielectric layer because of the high dielectric constant. Therefore, because of the electron affinity of the metal gate 46, the relatively lower electric field EB 51 and the thickness of the blocking dielectric layer 47, electron tunneling current 53 is effectively blocked, allowing large memory windows without erase saturation effects.
  • Memory cells implemented as described above can be arranged in a NAND-type array as shown in FIG. 5. The array includes a plurality of bit lines BL-1, BL-2, BL-3, BL-4, . . . , and a plurality of word lines WL-1, WL-2, . . . , WL-N−1, WL-N. Groups of N memory cells are connected in series between a block select transistor coupled to a corresponding bit line and a source select transistor coupled to a source line. A block select word line BST is coupled to a row of block select transistors and a source select word line SST is coupled to a row of source line connect transistors. Thus, for example, for a representative bit line, BL-2, in the figure, a block select transistor 60 connects a series of memory cells 61-1 through 61-N to the bit line BL-2 in response to the signal BST on the block select word line. The last memory cell 61-N in the series is connected to source select transistor 62 which couples the series to the source line SL in response to the signal SST on a source select word line.
  • In the alternative, the memory cells can be arranged NOR-type or virtual ground-type arrays often applied in flash memory devices.
  • Programming may be accomplished in the NAND array by applying incremental stepped pulse programming ISPP or other processes for inducing Fowler Norheim tunneling. ISPP involves applying a stepped programming voltage, starting at a gate bias of for example about plus 17 V, and incrementing the voltage for each programming step by about 0.2 V. Each pulse can have a constant pulse width of about 10 μs for example. In variations of the technique, the pulse width and the increment applied for each succeeding pulse can be varied to meet the needs of the particular implementation. The memory cells of this type have demonstrated relatively linear programming characteristics, and very large memory windows compared to the prior art, making them particularly well-suited to storing multiple bits per cell with multilevel programming technologies. In alternative embodiments, the so-called voltage pulse self-boosting technique is applied for programming. Other biasing arrangements can be applied as well, selected for compatibility with array characteristics.
  • Other programming bias techniques can be applied. For NOR array structures, various biasing arrangements for inducing hot electron tunneling or FN tunneling may be applied as well as other techniques known in the art.
  • FIGS. 6 and 7 show cross-sectional views of a representative memory cell structure as described herein implemented in a NAND-type array, taken across the word lines and along the word line respectively. FIG. 6 shows a semiconductor body 70 including channel regions 74, 75 and source/drain terminals 71, 72, 73 contacting the channel regions. The channel length between the source and drain terminals is preferably less than 50 nm, and in preferred embodiments 30 nm or less. The composite dielectric tunneling layer 76, the charge trapping layer 77, the blocking dielectric layer 78 and the metal gate word line layer 79 are arranged in stacks 80 and 81 over the channel regions 74 and 75 of respectively.
  • FIG. 7 shows the structure of FIG. 6 taken in cross section along a word line which includes the same stack with the same reference numerals as described with reference to FIG. 6. Column of series connected cells are separated by shallow trench isolation STI structures 82, 83, 84. In the illustration, the surfaces of the channel 74, and of the adjacent channel 74A, are planar. Implementations of the device may include recessed (concave) channel surfaces in this cross-section, or extended (convex) channel surfaces, depending on the manufacturing techniques and the desired product. The tunneling dielectric layer 76 and the rest of the stack 77, 78, 79 overlie the channel surfaces, whether planar, concave or convex, in a conformal manner. The channel width between the STI structures 80, 82 is preferably less than 50 nm, and more preferably as small as the STI techniques allow.
  • FIG. 8 is a simplified block diagram of an integrated circuit employing MA-BE-SONOS memory cells as described herein having a metal gate, an aluminum oxide or other high κ dielectric blocking layer, and a band gap engineered tunneling dielectric layer. The integrated circuit 810 includes a memory array 812 implemented using MA-BE-SONOS memory cells as described herein on a semiconductor substrate. A word line (or row) and block select decoder 814 is coupled to, and in electrical communication with, a plurality 816 of word lines and block select lines, and arranged along rows in the memory array 812. A bit line (column) decoder and drivers 818 are coupled to and in electrical communication with a plurality of bit lines 820 arranged along columns in the memory array 812 for reading data from, and writing data to, the memory cells in the memory array 812. Addresses are supplied on bus 822 to the word line decoder and drivers 814 and to the bit line decoder 818. Sense amplifiers and data-in structures in block 824, including current sources for the read, program and erase modes, are coupled to the bit line decoder 818 via data the bus 826. Data is supplied via the data-in line 828 from input/output ports on the integrated circuit 810 or from other data sources internal or external to the integrated circuit 810, to the data-in structures in block 824. In the illustrated embodiment, other circuitry 830 is included on the integrated circuit 810, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory cell array. Data is supplied via the data-out line 832 from the sense amplifiers in block 824 to input/output ports on the integrated circuit 810, or to other data destinations internal or external to the integrated circuit 810.
  • The array 812 can be a NAND array, an AND array or a NOR array, depending on the particular application. The very large memory window available supports storing multiple bits per cell, and thus multiple bit sense amplifiers can be included on the device.
  • A controller implemented in this example, using bias arrangement state machine 834, controls the application of bias arrangement supply voltages and current sources 836, such as read, program, erase, erase verify, program verify voltages or currents for the word lines and bit lines, and controls the word line/source line operation using an access control process. The controller 834 can be implemented using special purpose logic circuitry as known in the art. In alternative embodiments, the controller 834 comprises a general purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller 834.
  • FIG. 9 is a graph of flat band voltage versus erase bias time showing erase curves for various erase bias voltages for an embodiment of a memory cell (referred to as a MA BE-SONOS cell herein) in which the gate comprises platinum, the blocking dielectric layer comprises 180 Å of aluminum oxide, the charge trapping layer comprises 70 Å of silicon nitride, and the tunneling dielectric layer comprises 15 Å, 20 Å and 25 Årespectively of silicon dioxide, silicon nitride and silicon dioxide formed on a silicon substrate. The channel is grounded in these examples, so that the gate voltage VG represents the bias voltage across the stack. The plot shows the erase speed for VG ranging from minus 10 to minus 20 V in 2 V increments. Very high erase speeds are obtained using the structure. For bias voltages less than 20 V, hole tunneling current is sufficient to cause a reduction a threshold voltage for selected cell of more than 4 V less than 5 ms. For bias voltages less than 16 V, hold tunneling current sufficient to cause a reduction in threshold voltage and a selected so of more than 4 V less than 10 ms. Threshold shifts of as much as 7 V are readily achieved. Also, it can be seen, an erase time of less than 10 ms can be achieved for a gate voltage of about 15 V, showing that the technology is applicable to devices having relatively low breakdown voltages, such as very small devices, and nonetheless operable at relatively high speeds needed for NAND flash applications. These performance measurements demonstrate that this technology is scalable to devices having gate lengths on the order of 50 nm or lower, using maximum gate voltages on the order of 15 V.
  • FIG. 10 is a graph of flat band voltage versus erase bias time comparing erase curves of a tested MANOS cell having a platinum gate, a 180 Å aluminum oxide blocking dielectric layer, a 70 Å silicon nitride trapping layer, and a 45 Å silicon dioxide tunneling layer; and BE-SONOS cell with a p+-polysilicon gate, a 90 Å silicon dioxide blocking dielectric layer, a 70 Å silicon nitride trapping layer, and an ONO tunneling dielectric layer having a 25 Å isolation layer, a 20 Å offset layer and a 15 Å hole tunneling layer; and a MA BE-SONOS cell sample as described above. The three samples have similar equivalent oxide thicknesses EOT of about 180 Å. Under the same bias voltage of negative 18 V, the MA BE-SONOS sample shows superior erase speed over the other devices, readily achieving a 4 V drop and threshold voltage in about 1 ms, as compared to about 10 ms for BE-SONOS and over 100 ms for the MANOS sample. The tested cells have more than an order of magnitude faster erase speed than the prior art MANOS and BE-SONOS technologies.
  • FIG. 11 is a plot of current density J (A/cm2) versus electric field ETUN (MV/cm) in the tunneling dielectric layer using transient analysis for various bias voltages, comparing the MANOS, BE-SONOS and MA BE-SONOS cell samples described above. As can be seen, for an electric field ETUN less than 14 MV/cm the current density for hole tunneling for both the MA-BE-SONOS and the BE-SONOS samples are much high than that of the MANOS sample. For the MA BE-SONOS sample, no erase saturation is encountered, so that they can be continuously erased to a flat band voltage of less than −5 V. Practical devices can be operated readily with electric fields ETUN smaller than 14 MV/cm for inducing hole tunneling current, including electric fields ETUN as small as 10 or 11 MV/cm.
  • FIG. 12 is a plot of the erase curves for the MA-BE-SONOS sample with various band offset distances as determined by the thickness of the hole tunneling layer in the tunneling dielectric layer. As can be seen, the erase speed dramatically improves the for a hole tunneling layer comprising silicon dioxide less than about 20 Å thick, and continues to improve below 18 Å. Embodiments of BE-SONOS show continued erase speed improvements with reduction of the thickness of the hole tunneling layer comprising silicon dioxide to about 15 Å or less.
  • FIG. 13 is a plot showing program characteristics with program biases from 17 to 20 V for the MA-BE-SONOS sample. As can be seen, the program time is quite fast at relatively low bias voltages. Furthermore, a threshold shift of over 7 V can be achieved in program times on the order of 1 ms or less. When considered with the data shown in FIG. 9, it can be seen that the memory cell according to the present invention can be operated with memory windows of 7 V with high speed, and high density. With such a large memory window, the device is readily adaptable to multiple bit per cell implementations.
  • FIG. 14 is a graph of flat band voltage versus time with a gate potential at −20 V for four the separate devices, including a MANOS device having a platinum gate as described above, a BE-SONOS device having a P+ polysilicon gate as described above, a MA BE-SONOS device as described above having an aluminum gate (relatively low work function metal), and a MA BE-SONOS device as described above having a platinum gate (relatively high work function metal). As can be seen, the platinum gate MA BE-SONOS device has a threshold voltage swing of over 8 V in about 10 ms, and does not demonstrate erase saturation. The aluminum gate MA BE-SONOS device also has a very large threshold swing, but begins to show erase saturation at a flat band voltage of about −4 V. The BE-SONOS device having a P+ polysilicon gate as a very high erase speed, but suffers erase saturation at about −1 V after an erase pulse of about 1 ms. The platinum gate MANOS device does not demonstrate erase saturation, but does not reach a flat band voltage of −1 V until after an erase pulse of 50 ms or more.
  • FIG. 15 shows transient electric fields for a −20 V gate bias, in the tunnel layers (O1/N1/02) and blocking layer for a BE-SONOS device having a P+ polysilicon gate as described above, a MA BE-SONOS device as described above having an aluminum gate, and a MA BE-SONOS device as described above having a platinum gate. The draft shows the dramatic difference in the electric field in the blocking layer between the BE-SONOS device having a silicon dioxide blocking layer (starting at about 9 MV/cm) and the MA-BE-SONOS devices with an aluminum oxide blocking layer (starting at about 4.5 MV/cm). The graph also shows that the electric field in the tunneling layer remains below about 14 MV/cm, even with very high speed erase bias conditions.
  • The examples described above are implemented using n-channel devices, in which the source and drain terminals are doped with n-type impurities. The technology can be implemented using p-channel devices as well, in which the source and drain terminals are doped with p-type impurities.
  • The examples described above are implemented using devices with flat or planar channel surfaces. The technology can be implemented using non-planar structures, including cylindrical channel surfaces, fin shaped channels, recessed channels and so on.
  • The examples described above the charge storage stack is implemented so that the tunneling layer is on the channel surface and the blocking dielectric layer is adjacent the gate. In alternatives, the charge storage stack may be reversed, so that the tunneling layer is adjacent the gate terminal and the blocking dielectric is on the channel surface.
  • While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

Claims (24)

1. A charge trapping memory, comprising:
an array of memory cells, respective memory cells in the array including
a semiconductor body including channel having a channel surface, and source and drain terminals adjacent the channel;
a tunneling dielectric layer on the channel surface, the tunneling dielectric layer a combination of materials having negligible charge trapping efficiency, and arranged to establish a relatively large hole tunneling barrier height in near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface;
a charge trapping dielectric layer on the tunnel dielectric layer;
a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising a material having a dielectric constant K of 7 or more; and
a gate on the blocking dielectric layer, the gate comprising a metal or metal compound on the blocking dielectric layer.
2. The memory of claim 1, including
circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce an electric field of less than 14 MV/cm to cause hole tunneling through the tunneling dielectric layer.
3. The memory of claim 1, wherein the blocking dielectric layer comprises aluminum oxide.
4. The memory of claim 1, wherein the gate comprises platinum.
5. The memory of claim 1, wherein the gate comprises aluminum.
6. The memory of claim 1, wherein the gate comprises tantalum nitride.
7. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness less than 20 Å, a low barrier height layer on the first silicon oxide layer, having a hole tunneling barrier height less than 3 eV, and an isolation layer isolating the low barrier height layer from the charge trapping dielectric layer.
8. The memory of claim 7, wherein the thickness of the first silicon oxide layer is 15 Å or less.
9. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 20 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less.
10. The memory of claim 1, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less.
11. The memory of claim 1, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel, and a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less.
12. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less;
the charge trapping dielectric layer comprises silicon nitride having a thickness of 50 Å or more; and
the blocking dielectric layer comprises aluminum oxide having a thickness of 150 Å or more.
13. The memory of claim 1, wherein said bias voltage for inducing hole tunneling is less than 16 Volts, and the hole tunneling current is sufficient to cause reduction in threshold voltage in a selected cell of more than 4 Volts in less than 10 milliseconds.
14. The memory of claim 1, wherein said bias voltage for inducing hole tunneling is less than 20 Volts, and the hole tunneling current is sufficient to cause reduction in threshold voltage in a selected cell of more than 4 Volts in less than 5 milliseconds.
15. The memory of claim 1, wherein the effective oxide thickness EOT of the blocking dielectric layer, the charge trapping dielectric layer and the tunneling dielectric layer is less than 200 Å.
16. A charge trapping memory, comprising:
an array of memory cells, respective memory cells in the array including
a semiconductor body including channel having a channel surface, and source and drain terminals adjacent the channel;
a tunneling dielectric layer on the channel surface, the tunneling dielectric layer a combination of materials having negligible charge trapping efficiency, and arranged to establish a relatively large hole tunneling barrier height in near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface;
a charge trapping dielectric layer on the tunnel dielectric layer;
a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising aluminum oxide;
a gate on the blocking dielectric layer, the gate comprising aluminum.
17. The memory of claim 16, including
circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce hole tunneling through the tunneling dielectric layer.
18. The memory of claim 16, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less.
19. The memory of claim 16, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less.
20. The memory of claim 16, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel, and a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less.
21. A charge trapping memory, comprising:
an array of memory cells, respective memory cells in the array including
a semiconductor body including channel having a channel surface, and source and drain terminals adjacent the channel;
a tunneling dielectric layer on the channel surface, the tunneling dielectric layer a combination of materials having negligible charge trapping efficiency, and arranged to establish a relatively large hole tunneling barrier height in near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface;
a charge trapping dielectric layer on the tunnel dielectric layer;
a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising aluminum oxide;
a gate on the blocking dielectric layer, the gate comprising platinum;
circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce hole tunneling through the tunneling dielectric layer.
22. The memory of claim 21, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å or less.
23. The memory of claim 21, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel and having a thickness of 15 Å or less.
24. The memory of claim 21, wherein the tunneling dielectric layer comprises a stack of layers of dielectric material, including a first silicon oxide layer adjacent the channel, and a silicon nitride layer on the first silicon oxide layer having a thickness of 25 Å or less.
US11/845,276 2007-08-09 2007-08-27 Charge trapping memory cell with high speed erase Abandoned US20090039414A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US95482007P true 2007-08-09 2007-08-09
US11/845,276 US20090039414A1 (en) 2007-08-09 2007-08-27 Charge trapping memory cell with high speed erase

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/845,276 US20090039414A1 (en) 2007-08-09 2007-08-27 Charge trapping memory cell with high speed erase
TW97100251A TWI374448B (en) 2007-08-13 2008-01-03 Charge trapping memory cell with high speed erase
EP08152406A EP2026384A3 (en) 2007-08-13 2008-03-06 Charge trapping memory cell with high speed erase
KR1020080031481A KR100969611B1 (en) 2007-08-13 2008-04-04 Charge trapping memory cell with high speed erase
JP2008133678A JP5178318B2 (en) 2007-08-13 2008-05-21 Fast erase type charge trapping memory cell

Publications (1)

Publication Number Publication Date
US20090039414A1 true US20090039414A1 (en) 2009-02-12

Family

ID=40345647

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/845,321 Active 2028-03-03 US7737488B2 (en) 2007-08-09 2007-08-27 Blocking dielectric engineered charge trapping memory cell with high speed erase
US11/845,276 Abandoned US20090039414A1 (en) 2007-08-09 2007-08-27 Charge trapping memory cell with high speed erase
US12/763,006 Active US8343840B2 (en) 2007-08-09 2010-04-19 Blocking dielectric engineered charge trapping memory cell with high speed erase

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/845,321 Active 2028-03-03 US7737488B2 (en) 2007-08-09 2007-08-27 Blocking dielectric engineered charge trapping memory cell with high speed erase

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/763,006 Active US8343840B2 (en) 2007-08-09 2010-04-19 Blocking dielectric engineered charge trapping memory cell with high speed erase

Country Status (3)

Country Link
US (3) US7737488B2 (en)
CN (1) CN101364602B (en)
TW (1) TWI376809B (en)

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2031643A2 (en) 2007-08-27 2009-03-04 Macronix International Co., Ltd. Blocking dielectric bandgap engineered SONOS/MONOS memory
US20090166717A1 (en) * 2007-12-28 2009-07-02 Jin-Hyo Jung Nonvolatile memory device and method for manufacturing the same
US20090242956A1 (en) * 2008-03-28 2009-10-01 Heng Jiunn B Tunnel dielectrics for semiconductor devices
US20090278195A1 (en) * 2008-05-09 2009-11-12 Toba Takayuki Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof
US20110003446A1 (en) * 2007-10-18 2011-01-06 Macronix International Co., Ltd. Semiconductor Device and Method for Manufacturing the Same
US20110101442A1 (en) * 2009-11-02 2011-05-05 Applied Materials, Inc. Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control
US20110101438A1 (en) * 2009-11-03 2011-05-05 Dong-Chul Yoo Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers
US8222688B1 (en) * 2009-04-24 2012-07-17 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US8488387B2 (en) 2011-05-02 2013-07-16 Macronix International Co., Ltd. Thermally assisted dielectric charge trapping flash
WO2013148112A1 (en) * 2012-03-27 2013-10-03 Cypress Semiconductor Corporation Sonos stack with split nitride memory layer
US8614478B2 (en) 2010-07-26 2013-12-24 Infineon Technologies Austria Ag Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor
WO2014008166A1 (en) * 2012-07-01 2014-01-09 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers
US8643124B2 (en) 2007-05-25 2014-02-04 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8685813B2 (en) 2012-02-15 2014-04-01 Cypress Semiconductor Corporation Method of integrating a charge-trapping gate stack into a CMOS flow
US8710578B2 (en) 2009-04-24 2014-04-29 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US8724393B2 (en) 2011-05-02 2014-05-13 Macronix International Co., Ltd. Thermally assisted flash memory with diode strapping
US20140131716A1 (en) * 2012-11-12 2014-05-15 National Applied Research Laboratories Memory device and method for fabricating the same
US8824212B2 (en) 2011-05-02 2014-09-02 Macronix International Co., Ltd. Thermally assisted flash memory with segmented word lines
US8859374B1 (en) 2007-05-25 2014-10-14 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US9001590B2 (en) 2011-05-02 2015-04-07 Macronix International Co., Ltd. Method for operating a semiconductor structure
US9093318B2 (en) 2007-05-25 2015-07-28 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US9171728B2 (en) 2010-07-26 2015-10-27 Infineon Technologies Austria Ag Method for forming a power semiconductor device
TWI508075B (en) * 2011-06-09 2015-11-11 Macronix Int Co Ltd Thermally assisted dielectric charge trapping flash
US9299568B2 (en) 2007-05-25 2016-03-29 Cypress Semiconductor Corporation SONOS ONO stack scaling
US9349877B1 (en) 2007-05-25 2016-05-24 Cypress Semiconductor Corporation Nitridation oxidation of tunneling layer for improved SONOS speed and retention
US9348748B2 (en) 2013-12-24 2016-05-24 Macronix International Co., Ltd. Heal leveling
US9355849B1 (en) 2007-05-25 2016-05-31 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
WO2016191156A1 (en) * 2015-05-26 2016-12-01 Sandisk Technologies Llc Memory cell with high-k charge trapping layer
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9721962B1 (en) 2013-09-27 2017-08-01 Cypress Semiconductor Corporation Integration of a memory transistor into high-k, metal gate CMOS process flow

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006041738A1 (en) * 2006-09-04 2008-03-06 Leibniz-Institut Für Neue Materialien Gemeinnützige Gmbh Composition for coating electrical conductors and method for preparing such a composition
US7910446B2 (en) * 2007-07-16 2011-03-22 Applied Materials, Inc. Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices
US7737488B2 (en) * 2007-08-09 2010-06-15 Macronix International Co., Ltd. Blocking dielectric engineered charge trapping memory cell with high speed erase
KR101411549B1 (en) * 2007-11-13 2014-06-25 삼성전자주식회사 Method of manufacturing semiconductor device
US7973357B2 (en) * 2007-12-20 2011-07-05 Samsung Electronics Co., Ltd. Non-volatile memory devices
JP5443873B2 (en) * 2008-07-28 2014-03-19 株式会社東芝 Semiconductor device and manufacturing method thereof
JP5459650B2 (en) * 2008-09-22 2014-04-02 株式会社東芝 Memory cell of the nonvolatile semiconductor memory device
JP2010103130A (en) * 2008-10-21 2010-05-06 Panasonic Corp Semiconductor device, and manufacturing method thereof
CN101859603B (en) 2009-04-07 2012-10-24 辉芒微电子(深圳)有限公司 Method and device for enhancing persistence of EEPROM
JP2010244641A (en) * 2009-04-08 2010-10-28 Renesas Electronics Corp Erase method of nonvolatile semiconductor memory device
US8861273B2 (en) * 2009-04-21 2014-10-14 Macronix International Co., Ltd. Bandgap engineered charge trapping memory in two-transistor nor architecture
JP2012009700A (en) * 2010-06-25 2012-01-12 Toshiba Corp Semiconductor storage device and manufacturing method of the same
CN102820301A (en) * 2011-06-09 2012-12-12 华东师范大学 TN (tunnel nitrate)-SONOS (silicon oxide nitrate oxide silicon) memory with composite nitrogen-based dielectric tunneling layer
US9318336B2 (en) 2011-10-27 2016-04-19 Globalfoundries U.S. 2 Llc Non-volatile memory structure employing high-k gate dielectric and metal gate
US20140217492A1 (en) * 2013-02-04 2014-08-07 National Tsing Hua University Charge-trap type flash memory device having low-high-low energy band structure as trapping layer
KR20140122585A (en) * 2013-04-10 2014-10-20 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR20150113634A (en) 2014-03-31 2015-10-08 삼성전자주식회사 Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same
CN105226027B (en) * 2015-09-06 2019-03-15 中国科学院微电子研究所 Semiconductor devices and its manufacturing method
US10049869B2 (en) * 2016-09-30 2018-08-14 Lam Research Corporation Composite dielectric interface layers for interconnect structures
US9899410B1 (en) 2016-12-13 2018-02-20 Sandisk Technologies Llc Charge storage region in non-volatile memory

Citations (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE31083E (en) * 1979-02-15 1982-11-16 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure
US4630086A (en) * 1982-09-24 1986-12-16 Hitachi, Ltd. Nonvolatile MNOS memory
US4959812A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND cell structure
US5138410A (en) * 1989-12-11 1992-08-11 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having tunnel insulating film structure
US5408115A (en) * 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device
US5412603A (en) * 1994-05-06 1995-05-02 Texas Instruments Incorporated Method and circuitry for programming floating-gate memory cell using a single low-voltage supply
US5424569A (en) * 1994-05-05 1995-06-13 Micron Technology, Inc. Array of non-volatile sonos memory cells
US5515324A (en) * 1993-09-17 1996-05-07 Kabushiki Kaisha Toshiba EEPROM having NAND type memory cell array
US5566120A (en) * 1995-10-19 1996-10-15 Sun Microsystems, Inc. Apparatus and method for controlling transistor current leakage
US5668029A (en) * 1996-05-06 1997-09-16 United Microelectronics Corporation Process for fabricating multi-level read-only memory device
US5825062A (en) * 1995-12-12 1998-10-20 Rohm Co., Ltd. Semiconductor device including a nonvolatile memory
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6194272B1 (en) * 1998-05-19 2001-02-27 Mosel Vitelic, Inc. Split gate flash cell with extremely small cell size
US6215148B1 (en) * 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6219276B1 (en) * 2000-02-25 2001-04-17 Advanced Micro Devices, Inc. Multilevel cell programming
US6218700B1 (en) * 1997-10-29 2001-04-17 Stmicroelectronics S.A. Remanent memory device
US20010012663A1 (en) * 1995-10-30 2001-08-09 Angelo Magri' Single feature size mos technology power device
US6297096B1 (en) * 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US6320786B1 (en) * 2000-12-22 2001-11-20 Macronix International Co., Ltd. Method of controlling multi-state NROM
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6356478B1 (en) * 2000-12-21 2002-03-12 Actel Corporation Flash based control for field programmable gate array
US6363013B1 (en) * 2000-08-29 2002-03-26 Macronix International Co., Ltd. Auto-stopped page soft-programming method with voltage limited component
US6396741B1 (en) * 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6436768B1 (en) * 2001-06-27 2002-08-20 Advanced Micro Devices, Inc. Source drain implant during ONO formation for improved isolation of SONOS devices
US6458642B1 (en) * 2001-10-29 2002-10-01 Macronix International Co., Ltd. Method of fabricating a sonos device
US6487114B2 (en) * 2001-02-28 2002-11-26 Macronix International Co., Ltd. Method of reading two-bit memories of NROM cell
US6512696B1 (en) * 2001-11-13 2003-01-28 Macronix International Co., Ltd. Method of programming and erasing a SNNNS type non-volatile memory cell
US6522585B2 (en) * 2001-05-25 2003-02-18 Sandisk Corporation Dual-cell soft programming for virtual-ground memory arrays
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
US6552386B1 (en) * 2002-09-30 2003-04-22 Silicon-Based Technology Corp. Scalable split-gate flash memory cell structure and its contactless flash memory arrays
US6566699B2 (en) * 1997-07-30 2003-05-20 Saifun Semiconductors Ltd. Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6587903B2 (en) * 1998-02-27 2003-07-01 Micron Technology, Inc. Soft programming for recovery of overerasure
US6614694B1 (en) * 2002-04-02 2003-09-02 Macronix International Co., Ltd. Erase scheme for non-volatile memory
US6617639B1 (en) * 2002-06-21 2003-09-09 Advanced Micro Devices, Inc. Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
US6643185B1 (en) * 2002-08-07 2003-11-04 Advanced Micro Devices, Inc. Method for repairing over-erasure of fast bits on floating gate memory devices
US6643181B2 (en) * 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US6645813B1 (en) * 2002-01-16 2003-11-11 Taiwan Semiconductor Manufacturing Company Flash EEPROM with function bit by bit erasing
US6646924B1 (en) * 2002-08-02 2003-11-11 Macronix International Co, Ltd. Non-volatile memory and operating method thereof
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US6657894B2 (en) * 2002-03-29 2003-12-02 Macronix International Co., Ltd, Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6670240B2 (en) * 2001-08-13 2003-12-30 Halo Lsi, Inc. Twin NAND device structure, array operations and fabrication method
US6670671B2 (en) * 2001-06-13 2003-12-30 Hitachi, Ltd. Nonvolatile semiconductor memory device and manufacturing method thereof
US6674138B1 (en) * 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US6677200B2 (en) * 2001-08-09 2004-01-13 Samsung Electronics Co., Ltd. Method of forming non-volatile memory having floating trap type device
US6690601B2 (en) * 2002-03-29 2004-02-10 Macronix International Co., Ltd. Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same
US20040041192A1 (en) * 2002-08-29 2004-03-04 Baker Frank Kelsey Dielectric storage memory cell having high permittivity top dielectric and method therefor
US6709928B1 (en) * 2001-07-31 2004-03-23 Cypress Semiconductor Corporation Semiconductor device having silicon-rich layer and method of manufacturing such a device
US6714457B1 (en) * 2001-09-19 2004-03-30 Aplus Flash Technology, Inc. Parallel channel programming scheme for MLC flash memory
US6720630B2 (en) * 2001-05-30 2004-04-13 International Business Machines Corporation Structure and method for MOSFET with metallic gate electrode
US6744105B1 (en) * 2003-03-05 2004-06-01 Advanced Micro Devices, Inc. Memory array having shallow bit line with silicide contact portion and method of formation
US6784480B2 (en) * 2002-02-12 2004-08-31 Micron Technology, Inc. Asymmetric band-gap engineered nonvolatile memory device
US6795357B1 (en) * 2002-10-30 2004-09-21 Advance Micro Devices, Inc. Method for reading a non-volatile memory cell
US6798012B1 (en) * 1999-12-10 2004-09-28 Yueh Yale Ma Dual-bit double-polysilicon source-side injection flash EEPROM cell
US6815805B2 (en) * 2000-04-06 2004-11-09 Micron Technology, Inc. Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source
US6829175B2 (en) * 2002-09-09 2004-12-07 Macronix International Co., Ltd. Erasing method for non-volatile memory
US20040251489A1 (en) * 2003-06-10 2004-12-16 Sang-Hun Jeon SONOS memory device and method of manufacturing the same
US6841813B2 (en) * 2001-08-13 2005-01-11 Matrix Semiconductor, Inc. TFT mask ROM and method for making same
US6856551B2 (en) * 2003-02-06 2005-02-15 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
US6858899B2 (en) * 2002-10-15 2005-02-22 Matrix Semiconductor, Inc. Thin film transistor with metal oxide layer and method of making same
US6858906B2 (en) * 2001-06-28 2005-02-22 Samsung Electronics Co., Ltd. Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
US6885044B2 (en) * 2003-07-30 2005-04-26 Promos Technologies, Inc. Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates
US6888750B2 (en) * 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US20050106811A1 (en) * 2003-11-17 2005-05-19 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US20060022252A1 (en) * 2004-07-30 2006-02-02 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of fabricating the same
US20060118858A1 (en) * 2004-10-08 2006-06-08 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory device with alternative metal gate material
EP1677311A1 (en) * 2005-01-03 2006-07-05 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US20060186462A1 (en) * 2005-02-21 2006-08-24 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of fabricating the same
US20060198189A1 (en) * 2005-01-03 2006-09-07 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US20060197145A1 (en) * 2005-03-04 2006-09-07 Saysamone Pittikoun Non-volatile memory and manufacturing method and operating method thereof
US20060234446A1 (en) * 2005-03-09 2006-10-19 Houng-Chi Wei Non-volatile memory and fabricating method thereof
US20070012988A1 (en) * 2005-07-14 2007-01-18 Micron Technology, Inc. High density NAND non-volatile memory device
US20070076477A1 (en) * 2005-10-05 2007-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US20070120179A1 (en) * 2005-08-19 2007-05-31 Park Hong-Bae SONOS type non-volatile memory devices having a laminate blocking insulation layer and methods of manufacturing the same
US20070134855A1 (en) * 2005-12-09 2007-06-14 Macronix International Co., Ltd. A stacked non-volatile memory device and methods for fabricating the same
US20070134876A1 (en) * 2005-12-09 2007-06-14 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US20070138539A1 (en) * 2005-12-15 2007-06-21 Macronix International Co., Ltd. Non-volatile memory device having a nitride-oxide dielectric layer
US7345920B2 (en) * 2004-09-09 2008-03-18 Macronix International Co., Ltd. Method and apparatus for sensing in charge trapping non-volatile memory
US7355662B2 (en) * 2000-01-20 2008-04-08 International Business Machines Corporation Liquid crystal display panel and device thereof
US20090039417A1 (en) * 2005-02-17 2009-02-12 National University Of Singapore Nonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon Dioxide

Family Cites Families (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448517A (en) 1987-06-29 1995-09-05 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
US5270969A (en) 1987-06-29 1993-12-14 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with nand cell structure
USRE35838E (en) 1987-12-28 1998-07-07 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND cell structure
US5355464A (en) 1991-02-11 1994-10-11 Intel Corporation Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory
JPH0582795A (en) 1991-08-22 1993-04-02 Rohm Co Ltd Semiconductor memory device
JPH0555596A (en) 1991-08-22 1993-03-05 Rohm Co Ltd The semiconductor nonvolatile memory device
US5278439A (en) 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5712180A (en) 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US5644533A (en) 1992-11-02 1997-07-01 Nvx Corporation Flash memory system, and methods of constructing and utilizing same
EP0700570B1 (en) 1993-05-28 2001-07-11 Macronix International Co., Ltd. Flash eprom with block erase flags for over-erase protection
DE4422791C2 (en) 1993-06-29 2001-11-29 Toshiba Kawasaki Kk Semiconductor devices with an inducing an inversion layer in a surface region of a semiconductor substrate conductive film
US5509134A (en) 1993-06-30 1996-04-16 Intel Corporation Method and apparatus for execution of operations in a flash memory array
US5485422A (en) 1994-06-02 1996-01-16 Intel Corporation Drain bias multiplexing for multiple bit flash cell
US5483486A (en) 1994-10-19 1996-01-09 Intel Corporation Charge pump circuit for providing multiple output voltages for flash memory
US5694356A (en) 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5602775A (en) 1995-03-15 1997-02-11 National Semiconductor Corporation Flash EEPROM Memory system for low voltage operation and method
JP2937805B2 (en) 1995-05-19 1999-08-23 モトローラ株式会社 Non-volatile memory and the program / erase / read process with a multi-bit corresponding cell of the two-layer floating gate structure
US5877054A (en) 1995-06-29 1999-03-02 Sharp Kabushiki Kaisha Method of making nonvolatile semiconductor memory
AU6185196A (en) 1995-07-03 1997-02-05 Elvira Gulerson Method of fabricating a fast programming flash e2prm cell
US6614070B1 (en) 1998-04-16 2003-09-02 Cypress Semiconductor Corporation Semiconductor non-volatile memory device having a NAND cell structure
US5745410A (en) 1995-11-17 1998-04-28 Macronix International Co., Ltd. Method and system for soft programming algorithm
US5768192A (en) 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US5835396A (en) 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
EP0843360A1 (en) 1996-11-15 1998-05-20 Hitachi Europe Limited Memory device
US5966603A (en) 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
JPH1140682A (en) 1997-07-18 1999-02-12 Sony Corp Non-volatile semiconductor memory and its manufacture
US6026026A (en) 1997-12-05 2000-02-15 Hyundai Electronics America, Inc. Self-convergence of post-erase threshold voltages in a flash memory cell using transient response
TW365686B (en) 1998-02-16 1999-08-01 Taiwan Semiconductor Mfg Co Ltd Method of manufacture of fabricating flash memory split-gate
US6469343B1 (en) 1998-04-02 2002-10-22 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US6074917A (en) 1998-06-16 2000-06-13 Advanced Micro Devices, Inc. LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devices
US6487547B1 (en) * 1999-01-29 2002-11-26 Oracle Corporation Database appliance comprising hardware and software bundle configured for specific database applications
US6548825B1 (en) 1999-06-04 2003-04-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device including barrier layer having dispersed particles
JP3971873B2 (en) 1999-09-10 2007-09-05 株式会社ルネサステクノロジ The semiconductor integrated circuit device and manufacturing method thereof
US6172907B1 (en) 1999-10-22 2001-01-09 Cypress Semiconductor Corporation Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same
DE19955602A1 (en) 1999-11-18 2001-05-31 Infineon Technologies Ag A non-volatile semiconductor memory cell as well as processes for their preparation
JP5792918B2 (en) 2000-08-14 2015-10-14 サンディスク・スリー・ディ・リミテッド・ライアビリティ・カンパニーSandisk 3D Llc High-density memory device
US6891262B2 (en) 2001-07-19 2005-05-10 Sony Corporation Semiconductor device and method of producing the same
US6731544B2 (en) 2001-05-14 2004-05-04 Nexflash Technologies, Inc. Method and apparatus for multiple byte or page mode programming of a flash memory array
KR20020092114A (en) 2001-06-02 2002-12-11 김대만 SONOS cell eliminating drain turn-on phenomenon and over- erase phenomenon, non-volatile memory device having SONOS cell and the method of processing non-volatile memory device SONOS cell
KR100395762B1 (en) 2001-07-31 2003-08-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
US6720614B2 (en) 2001-08-07 2004-04-13 Macronix International Co., Ltd. Operation method for programming and erasing a data in a P-channel sonos memory cell
US7135734B2 (en) 2001-08-30 2006-11-14 Micron Technology, Inc. Graded composition metal oxide tunnel barrier interpoly insulators
US7012297B2 (en) 2001-08-30 2006-03-14 Micron Technology, Inc. Scalable flash/NV structures and devices with extended endurance
US7476925B2 (en) 2001-08-30 2009-01-13 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
EP1300888B1 (en) 2001-10-08 2013-03-13 STMicroelectronics Srl Process for manufacturing a dual charge storage location memory cell
US6925007B2 (en) 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US20030089935A1 (en) 2001-11-13 2003-05-15 Macronix International Co., Ltd. Non-volatile semiconductor memory device with multi-layer gate insulating structure
US7115469B1 (en) 2001-12-17 2006-10-03 Spansion, Llc Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process
US6605840B1 (en) 2002-02-07 2003-08-12 Ching-Yuan Wu Scalable multi-bit flash memory cell and its memory array
US6713332B2 (en) 2002-05-13 2004-03-30 Macronix International Co., Ltd. Non-volatile memory device with enlarged trapping layer
US7042045B2 (en) 2002-06-04 2006-05-09 Samsung Electronics Co., Ltd. Non-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6897533B1 (en) 2002-09-18 2005-05-24 Advanced Micro Devices, Inc. Multi-bit silicon nitride charge-trapping non-volatile memory cell
KR100446632B1 (en) 2002-10-14 2004-09-04 삼성전자주식회사 Nonvolatile Silicon/Oxide/Nitride/Silicon/ Nitride/Oxide/ Silicon memory
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
JP2004152977A (en) 2002-10-30 2004-05-27 Renesas Technology Corp Semiconductor storage device
US7057234B2 (en) 2002-12-06 2006-06-06 Cornell Research Foundation, Inc. Scalable nano-transistor and memory using back-side trapping
US7505321B2 (en) 2002-12-31 2009-03-17 Sandisk 3D Llc Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US7233522B2 (en) 2002-12-31 2007-06-19 Sandisk 3D Llc NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
KR100504691B1 (en) 2003-01-10 2005-08-03 삼성전자주식회사 Non-volatile memory device having a charge strage insulator and method of fabricating the same
US6912163B2 (en) 2003-01-14 2005-06-28 Fasl, Llc Memory device having high work function gate and method of erasing same
US6815764B2 (en) 2003-03-17 2004-11-09 Samsung Electronics Co., Ltd. Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same
TWI220316B (en) 2003-05-22 2004-08-11 Powerchip Semiconductor Corp Flash memory cell, flash memory cell array and manufacturing method thereof
JP4040534B2 (en) 2003-06-04 2008-01-30 株式会社東芝 A semiconductor memory device
US6970383B1 (en) 2003-06-10 2005-11-29 Actel Corporation Methods of redundancy in a floating trap memory element based field programmable gate array
US20040256679A1 (en) 2003-06-17 2004-12-23 Hu Yongjun J. Dual work function metal gates and method of forming
US6979857B2 (en) 2003-07-01 2005-12-27 Micron Technology, Inc. Apparatus and method for split gate NROM memory
US7169667B2 (en) 2003-07-30 2007-01-30 Promos Technologies Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate
US6951782B2 (en) 2003-07-30 2005-10-04 Promos Technologies, Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions
US7012299B2 (en) 2003-09-23 2006-03-14 Matrix Semiconductors, Inc. Storage layer optimization of a nonvolatile memory device
KR100562743B1 (en) 2003-10-06 2006-03-21 동부아남반도체 주식회사 Method for fabricating flash memory device
KR100579844B1 (en) 2003-11-05 2006-05-12 동부일렉트로닉스 주식회사 Non volatile memory and fabrication method thereof
US7157769B2 (en) 2003-12-18 2007-01-02 Micron Technology, Inc. Flash memory having a high-permittivity tunnel dielectric
US7154779B2 (en) 2004-01-21 2006-12-26 Sandisk Corporation Non-volatile memory cell using high-k material inter-gate programming
US7151692B2 (en) 2004-01-27 2006-12-19 Macronix International Co., Ltd. Operation scheme for programming charge trapping non-volatile memory
US6937511B2 (en) 2004-01-27 2005-08-30 Macronix International Co., Ltd. Circuit and method for programming charge storage memory cells
US7209390B2 (en) 2004-04-26 2007-04-24 Macronix International Co., Ltd. Operation scheme for spectrum shift in charge trapping non-volatile memory
US7187590B2 (en) 2004-04-26 2007-03-06 Macronix International Co., Ltd. Method and system for self-convergent erase in charge trapping memory cells
US7164603B2 (en) 2004-04-26 2007-01-16 Yen-Hao Shih Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
US7075828B2 (en) 2004-04-26 2006-07-11 Macronix International Co., Intl. Operation scheme with charge balancing erase for charge trapping non-volatile memory
US7133313B2 (en) 2004-04-26 2006-11-07 Macronix International Co., Ltd. Operation scheme with charge balancing for charge trapping non-volatile memory
US6996011B2 (en) 2004-05-26 2006-02-07 Macronix International Co., Ltd. NAND-type non-volatile memory cell and method for operating same
US7133316B2 (en) 2004-06-02 2006-11-07 Macronix International Co., Ltd. Program/erase method for P-channel charge trapping memory device
US7190614B2 (en) 2004-06-17 2007-03-13 Macronix International Co., Ltd. Operation scheme for programming charge trapping non-volatile memory
US7115942B2 (en) 2004-07-01 2006-10-03 Chih-Hsin Wang Method and apparatus for nonvolatile memory
US7120059B2 (en) 2004-07-06 2006-10-10 Macronix International Co., Ltd. Memory array including multiple-gate charge trapping non-volatile cells
US7209386B2 (en) 2004-07-06 2007-04-24 Macronix International Co., Ltd. Charge trapping non-volatile memory and method for gate-by-gate erase for same
US20060007732A1 (en) 2004-07-06 2006-01-12 Macronix International Co., Ltd. Charge trapping non-volatile memory and method for operating same
US7106625B2 (en) 2004-07-06 2006-09-12 Macronix International Co, Td Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same
US20060017085A1 (en) 2004-07-26 2006-01-26 Prateep Tuntasood NAND flash memory with densely packed memory gates and fabrication process
US7457156B2 (en) 2004-09-02 2008-11-25 Micron Technology, Inc. NAND flash depletion cell structure
JP2006120834A (en) * 2004-10-21 2006-05-11 Disco Abrasive Syst Ltd Wafer dividing method
US7253050B2 (en) * 2004-12-20 2007-08-07 Infineon Technologies Ag Transistor device and method of manufacture thereof
US7642585B2 (en) 2005-01-03 2010-01-05 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US8264028B2 (en) 2005-01-03 2012-09-11 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US7315474B2 (en) 2005-01-03 2008-01-01 Macronix International Co., Ltd Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
TWI249819B (en) 2005-01-11 2006-02-21 Powerchip Semiconductor Corp Method of fabricating non-volatile memory
KR100688521B1 (en) * 2005-01-18 2007-03-02 삼성전자주식회사 Semiconductor Device comprising High-k insulating layer and Manufacturing Method for the Same
US7479425B2 (en) 2005-01-20 2009-01-20 Chartered Semiconductor Manufacturing, Ltd Method for forming high-K charge storage device
KR100647318B1 (en) 2005-02-03 2006-11-23 삼성전자주식회사 Nonvolatile memory device and fabrication method of the same
US7158420B2 (en) 2005-04-29 2007-01-02 Macronix International Co., Ltd. Inversion bit line, charge trapping non-volatile memory and method of operating same
US7279740B2 (en) 2005-05-12 2007-10-09 Micron Technology, Inc. Band-engineered multi-gated non-volatile memory device with enhanced attributes
US7612403B2 (en) 2005-05-17 2009-11-03 Micron Technology, Inc. Low power non-volatile memory and gate stack
US7636257B2 (en) 2005-06-10 2009-12-22 Macronix International Co., Ltd. Methods of operating p-channel non-volatile memory devices
US7468299B2 (en) 2005-08-04 2008-12-23 Macronix International Co., Ltd. Non-volatile memory cells and methods of manufacturing the same
US7576386B2 (en) 2005-08-04 2009-08-18 Macronix International Co., Ltd. Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
US7629641B2 (en) 2005-08-31 2009-12-08 Micron Technology, Inc. Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection
US8846549B2 (en) 2005-09-27 2014-09-30 Macronix International Co., Ltd. Method of forming bottom oxide for nitride flash memory
US8816422B2 (en) * 2006-09-15 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-trapping layer flash memory cell
US7450423B2 (en) 2007-01-03 2008-11-11 Macronix International Co., Ltd. Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure
US7737488B2 (en) * 2007-08-09 2010-06-15 Macronix International Co., Ltd. Blocking dielectric engineered charge trapping memory cell with high speed erase

Patent Citations (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE31083E (en) * 1979-02-15 1982-11-16 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure
US4630086A (en) * 1982-09-24 1986-12-16 Hitachi, Ltd. Nonvolatile MNOS memory
US4959812A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND cell structure
US5138410A (en) * 1989-12-11 1992-08-11 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having tunnel insulating film structure
US5515324A (en) * 1993-09-17 1996-05-07 Kabushiki Kaisha Toshiba EEPROM having NAND type memory cell array
US5408115A (en) * 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device
US5424569A (en) * 1994-05-05 1995-06-13 Micron Technology, Inc. Array of non-volatile sonos memory cells
US5412603A (en) * 1994-05-06 1995-05-02 Texas Instruments Incorporated Method and circuitry for programming floating-gate memory cell using a single low-voltage supply
US5566120A (en) * 1995-10-19 1996-10-15 Sun Microsystems, Inc. Apparatus and method for controlling transistor current leakage
US20010012663A1 (en) * 1995-10-30 2001-08-09 Angelo Magri' Single feature size mos technology power device
US5825062A (en) * 1995-12-12 1998-10-20 Rohm Co., Ltd. Semiconductor device including a nonvolatile memory
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US5668029A (en) * 1996-05-06 1997-09-16 United Microelectronics Corporation Process for fabricating multi-level read-only memory device
US6297096B1 (en) * 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US6566699B2 (en) * 1997-07-30 2003-05-20 Saifun Semiconductors Ltd. Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6218700B1 (en) * 1997-10-29 2001-04-17 Stmicroelectronics S.A. Remanent memory device
US6587903B2 (en) * 1998-02-27 2003-07-01 Micron Technology, Inc. Soft programming for recovery of overerasure
US6194272B1 (en) * 1998-05-19 2001-02-27 Mosel Vitelic, Inc. Split gate flash cell with extremely small cell size
US6215148B1 (en) * 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6798012B1 (en) * 1999-12-10 2004-09-28 Yueh Yale Ma Dual-bit double-polysilicon source-side injection flash EEPROM cell
US7355662B2 (en) * 2000-01-20 2008-04-08 International Business Machines Corporation Liquid crystal display panel and device thereof
US6219276B1 (en) * 2000-02-25 2001-04-17 Advanced Micro Devices, Inc. Multilevel cell programming
US6815805B2 (en) * 2000-04-06 2004-11-09 Micron Technology, Inc. Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source
US6888750B2 (en) * 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US6396741B1 (en) * 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6363013B1 (en) * 2000-08-29 2002-03-26 Macronix International Co., Ltd. Auto-stopped page soft-programming method with voltage limited component
US6356478B1 (en) * 2000-12-21 2002-03-12 Actel Corporation Flash based control for field programmable gate array
US6320786B1 (en) * 2000-12-22 2001-11-20 Macronix International Co., Ltd. Method of controlling multi-state NROM
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
US6487114B2 (en) * 2001-02-28 2002-11-26 Macronix International Co., Ltd. Method of reading two-bit memories of NROM cell
US6522585B2 (en) * 2001-05-25 2003-02-18 Sandisk Corporation Dual-cell soft programming for virtual-ground memory arrays
US6720630B2 (en) * 2001-05-30 2004-04-13 International Business Machines Corporation Structure and method for MOSFET with metallic gate electrode
US6670671B2 (en) * 2001-06-13 2003-12-30 Hitachi, Ltd. Nonvolatile semiconductor memory device and manufacturing method thereof
US6436768B1 (en) * 2001-06-27 2002-08-20 Advanced Micro Devices, Inc. Source drain implant during ONO formation for improved isolation of SONOS devices
US6858906B2 (en) * 2001-06-28 2005-02-22 Samsung Electronics Co., Ltd. Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
US6709928B1 (en) * 2001-07-31 2004-03-23 Cypress Semiconductor Corporation Semiconductor device having silicon-rich layer and method of manufacturing such a device
US6818558B1 (en) * 2001-07-31 2004-11-16 Cypress Semiconductor Corporation Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices
US6677200B2 (en) * 2001-08-09 2004-01-13 Samsung Electronics Co., Ltd. Method of forming non-volatile memory having floating trap type device
US6841813B2 (en) * 2001-08-13 2005-01-11 Matrix Semiconductor, Inc. TFT mask ROM and method for making same
US6670240B2 (en) * 2001-08-13 2003-12-30 Halo Lsi, Inc. Twin NAND device structure, array operations and fabrication method
US6714457B1 (en) * 2001-09-19 2004-03-30 Aplus Flash Technology, Inc. Parallel channel programming scheme for MLC flash memory
US6643181B2 (en) * 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US6458642B1 (en) * 2001-10-29 2002-10-01 Macronix International Co., Ltd. Method of fabricating a sonos device
US6512696B1 (en) * 2001-11-13 2003-01-28 Macronix International Co., Ltd. Method of programming and erasing a SNNNS type non-volatile memory cell
US6674138B1 (en) * 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US6645813B1 (en) * 2002-01-16 2003-11-11 Taiwan Semiconductor Manufacturing Company Flash EEPROM with function bit by bit erasing
US6784480B2 (en) * 2002-02-12 2004-08-31 Micron Technology, Inc. Asymmetric band-gap engineered nonvolatile memory device
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6690601B2 (en) * 2002-03-29 2004-02-10 Macronix International Co., Ltd. Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same
US6657894B2 (en) * 2002-03-29 2003-12-02 Macronix International Co., Ltd, Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells
US6614694B1 (en) * 2002-04-02 2003-09-02 Macronix International Co., Ltd. Erase scheme for non-volatile memory
US6617639B1 (en) * 2002-06-21 2003-09-09 Advanced Micro Devices, Inc. Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
US6646924B1 (en) * 2002-08-02 2003-11-11 Macronix International Co, Ltd. Non-volatile memory and operating method thereof
US6643185B1 (en) * 2002-08-07 2003-11-04 Advanced Micro Devices, Inc. Method for repairing over-erasure of fast bits on floating gate memory devices
US20040041192A1 (en) * 2002-08-29 2004-03-04 Baker Frank Kelsey Dielectric storage memory cell having high permittivity top dielectric and method therefor
US6829175B2 (en) * 2002-09-09 2004-12-07 Macronix International Co., Ltd. Erasing method for non-volatile memory
US6552386B1 (en) * 2002-09-30 2003-04-22 Silicon-Based Technology Corp. Scalable split-gate flash memory cell structure and its contactless flash memory arrays
US6858899B2 (en) * 2002-10-15 2005-02-22 Matrix Semiconductor, Inc. Thin film transistor with metal oxide layer and method of making same
US6795357B1 (en) * 2002-10-30 2004-09-21 Advance Micro Devices, Inc. Method for reading a non-volatile memory cell
US6856551B2 (en) * 2003-02-06 2005-02-15 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices
US6744105B1 (en) * 2003-03-05 2004-06-01 Advanced Micro Devices, Inc. Memory array having shallow bit line with silicide contact portion and method of formation
US20040251489A1 (en) * 2003-06-10 2004-12-16 Sang-Hun Jeon SONOS memory device and method of manufacturing the same
US6885044B2 (en) * 2003-07-30 2005-04-26 Promos Technologies, Inc. Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates
US20050106811A1 (en) * 2003-11-17 2005-05-19 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US20060022252A1 (en) * 2004-07-30 2006-02-02 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of fabricating the same
US7345920B2 (en) * 2004-09-09 2008-03-18 Macronix International Co., Ltd. Method and apparatus for sensing in charge trapping non-volatile memory
US20060118858A1 (en) * 2004-10-08 2006-06-08 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory device with alternative metal gate material
EP1677311A1 (en) * 2005-01-03 2006-07-05 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US20060198189A1 (en) * 2005-01-03 2006-09-07 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US20090039417A1 (en) * 2005-02-17 2009-02-12 National University Of Singapore Nonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon Dioxide
US20060186462A1 (en) * 2005-02-21 2006-08-24 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of fabricating the same
US20060197145A1 (en) * 2005-03-04 2006-09-07 Saysamone Pittikoun Non-volatile memory and manufacturing method and operating method thereof
US20060234446A1 (en) * 2005-03-09 2006-10-19 Houng-Chi Wei Non-volatile memory and fabricating method thereof
US20070012988A1 (en) * 2005-07-14 2007-01-18 Micron Technology, Inc. High density NAND non-volatile memory device
US20070120179A1 (en) * 2005-08-19 2007-05-31 Park Hong-Bae SONOS type non-volatile memory devices having a laminate blocking insulation layer and methods of manufacturing the same
US20070076477A1 (en) * 2005-10-05 2007-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US20070134855A1 (en) * 2005-12-09 2007-06-14 Macronix International Co., Ltd. A stacked non-volatile memory device and methods for fabricating the same
US20070134876A1 (en) * 2005-12-09 2007-06-14 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US20070138539A1 (en) * 2005-12-15 2007-06-21 Macronix International Co., Ltd. Non-volatile memory device having a nitride-oxide dielectric layer

Cited By (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997641B2 (en) 2007-05-25 2018-06-12 Cypress Semiconductor Corporation SONOS ONO stack scaling
US9349877B1 (en) 2007-05-25 2016-05-24 Cypress Semiconductor Corporation Nitridation oxidation of tunneling layer for improved SONOS speed and retention
US9093318B2 (en) 2007-05-25 2015-07-28 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US9355849B1 (en) 2007-05-25 2016-05-31 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US8859374B1 (en) 2007-05-25 2014-10-14 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US9502543B1 (en) 2007-05-25 2016-11-22 Cypress Semiconductor Corporation Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode
US8643124B2 (en) 2007-05-25 2014-02-04 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US9929240B2 (en) 2007-05-25 2018-03-27 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US9299568B2 (en) 2007-05-25 2016-03-29 Cypress Semiconductor Corporation SONOS ONO stack scaling
US9306025B2 (en) 2007-05-25 2016-04-05 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US20110003452A1 (en) * 2007-08-27 2011-01-06 Macronix International Co., Ltd. HIGH-k CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS
US20090059676A1 (en) * 2007-08-27 2009-03-05 Macronix International Co., Ltd. HIGH-k CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS
US7816727B2 (en) 2007-08-27 2010-10-19 Macronix International Co., Ltd. High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
US8330210B2 (en) 2007-08-27 2012-12-11 Macronix International Co., Ltd. High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
EP2031643A2 (en) 2007-08-27 2009-03-04 Macronix International Co., Ltd. Blocking dielectric bandgap engineered SONOS/MONOS memory
US8119481B2 (en) 2007-08-27 2012-02-21 Macronix International Co., Ltd. High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
US20110003446A1 (en) * 2007-10-18 2011-01-06 Macronix International Co., Ltd. Semiconductor Device and Method for Manufacturing the Same
US8101483B2 (en) * 2007-10-18 2012-01-24 Macronix International Co., Ltd. Semiconductor device and method for manufacturing the same
US20090166717A1 (en) * 2007-12-28 2009-07-02 Jin-Hyo Jung Nonvolatile memory device and method for manufacturing the same
US20090242956A1 (en) * 2008-03-28 2009-10-01 Heng Jiunn B Tunnel dielectrics for semiconductor devices
US8134201B2 (en) * 2008-05-09 2012-03-13 Kabushiki Kaisha Toshiba Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof
US20090278195A1 (en) * 2008-05-09 2009-11-12 Toba Takayuki Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof
US10199229B2 (en) 2009-04-24 2019-02-05 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US9105512B2 (en) 2009-04-24 2015-08-11 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US8710579B1 (en) 2009-04-24 2014-04-29 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US8222688B1 (en) * 2009-04-24 2012-07-17 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US9793125B2 (en) 2009-04-24 2017-10-17 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US8710578B2 (en) 2009-04-24 2014-04-29 Cypress Semiconductor Corporation SONOS stack with split nitride memory layer
US9502521B2 (en) 2009-11-02 2016-11-22 Applied Materials, Inc. Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control
US20110101442A1 (en) * 2009-11-02 2011-05-05 Applied Materials, Inc. Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control
US20110101438A1 (en) * 2009-11-03 2011-05-05 Dong-Chul Yoo Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers
US8410542B2 (en) * 2009-11-03 2013-04-02 Samsung Electronics Co., Ltd. Charge-trapping nonvolatile memory devices having gate structures therein with improved blocking layers
US8614478B2 (en) 2010-07-26 2013-12-24 Infineon Technologies Austria Ag Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor
US9171728B2 (en) 2010-07-26 2015-10-27 Infineon Technologies Austria Ag Method for forming a power semiconductor device
US9159796B2 (en) 2010-07-26 2015-10-13 Infineon Technologies Austria Ag Method for protecting a semiconductor device against degradation and a method for manufacturing a semiconductor device protected against hot charge carriers
US8724393B2 (en) 2011-05-02 2014-05-13 Macronix International Co., Ltd. Thermally assisted flash memory with diode strapping
US8824212B2 (en) 2011-05-02 2014-09-02 Macronix International Co., Ltd. Thermally assisted flash memory with segmented word lines
US8488387B2 (en) 2011-05-02 2013-07-16 Macronix International Co., Ltd. Thermally assisted dielectric charge trapping flash
US9001590B2 (en) 2011-05-02 2015-04-07 Macronix International Co., Ltd. Method for operating a semiconductor structure
US9214236B2 (en) 2011-05-02 2015-12-15 Macronix International Co., Ltd. Thermally assisted flash memory with diode strapping
TWI508075B (en) * 2011-06-09 2015-11-11 Macronix Int Co Ltd Thermally assisted dielectric charge trapping flash
US8685813B2 (en) 2012-02-15 2014-04-01 Cypress Semiconductor Corporation Method of integrating a charge-trapping gate stack into a CMOS flow
WO2013148112A1 (en) * 2012-03-27 2013-10-03 Cypress Semiconductor Corporation Sonos stack with split nitride memory layer
WO2014008166A1 (en) * 2012-07-01 2014-01-09 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers
US20140131716A1 (en) * 2012-11-12 2014-05-15 National Applied Research Laboratories Memory device and method for fabricating the same
US9721962B1 (en) 2013-09-27 2017-08-01 Cypress Semiconductor Corporation Integration of a memory transistor into high-k, metal gate CMOS process flow
US9911746B1 (en) * 2013-09-27 2018-03-06 Cypress Semiconductor Corporation Integration of a memory transistor into high-k, metal gate CMOS process flow
US9911747B2 (en) 2013-09-27 2018-03-06 Cypress Semiconductor Corporation Integration of a memory transistor into high-k, metal gate CMOS process flow
US9348748B2 (en) 2013-12-24 2016-05-24 Macronix International Co., Ltd. Heal leveling
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
WO2016191156A1 (en) * 2015-05-26 2016-12-01 Sandisk Technologies Llc Memory cell with high-k charge trapping layer

Also Published As

Publication number Publication date
CN101364602B (en) 2010-09-01
CN101364602A (en) 2009-02-11
US8343840B2 (en) 2013-01-01
US20100193859A1 (en) 2010-08-05
US7737488B2 (en) 2010-06-15
TW200908345A (en) 2009-02-16
TWI376809B (en) 2012-11-11
US20090039416A1 (en) 2009-02-12

Similar Documents

Publication Publication Date Title
US7589387B2 (en) SONOS type two-bit FinFET flash memory cell
US6674122B2 (en) Semiconductor integrated circuit
US7400009B2 (en) Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
EP0573170B1 (en) Method of manufacture of high density EEPROM cell array
KR101039244B1 (en) Nonvolatile memory and method of making same
US7050330B2 (en) Multi-state NROM device
US5999444A (en) Nonvolatile semiconductor memory device and writing and erasing method of the same
US8208279B2 (en) Integrated circuit self aligned 3D memory array and manufacturing method
US6248628B1 (en) Method of fabricating an ONO dielectric by nitridation for MNOS memory cells
Wang et al. A novel MONOS-type nonvolatile memory using high-/spl kappa/dielectrics for improved data retention and programming speed
KR101017713B1 (en) Charge-trapping memory arrays resistant to damage from contact hole formation
US7221586B2 (en) Memory utilizing oxide nanolaminates
US6784480B2 (en) Asymmetric band-gap engineered nonvolatile memory device
US6671209B2 (en) Erasing method for p-channel NROM
US7749848B2 (en) Band-engineered multi-gated non-volatile memory device with enhanced attributes
JP4601287B2 (en) Nonvolatile semiconductor memory device
JP4601316B2 (en) Nonvolatile semiconductor memory device
CN101364602B (en) Blocking dielectric engineered charge trapping memory cell with high speed erase
US7576386B2 (en) Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
US7196935B2 (en) Ballistic injection NROM flash memory
US8058118B2 (en) Methods of forming and operating back-side trap non-volatile memory cells
US20080145985A1 (en) Embedded semiconductor memory devices and methods for fabricating the same
CN101964209B (en) Methods of operating p-channel non-volatile memory devices
US7282762B2 (en) 4F2 EEPROM NROM memory arrays with vertical devices
US7829938B2 (en) High density NAND non-volatile memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LUE, HANG-TING;LAI, SHENG-CHIH;REEL/FRAME:020104/0608

Effective date: 20070907