CN1797769A - 具有多栅电介质层的半导体器件及其制造方法 - Google Patents
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Abstract
揭示一种具有双栅电介质层的半导体器件及其制造方法。该半导体器件包括:硅基板,其被分成单元区,其中形成NMOS晶体管,及外围区,其中形成NMOS及PMOS晶体管;在该单元区中的该硅基板上形成的目标硅氧化物层;在该外围区中的该硅基板上形成的氧氮化物层;在该单元区中形成的第一栅结构;在该外围区的NMOS区中的该氧氮化物层上形成的第二栅结构;及在该外围区的PMOS区中的该氧氮化物层上形成的第三栅结构。
Description
技术领域
本发明是关于一种制造半导体器件的方法,且更具体地关于一种在半导体器件中形成多栅电介质层的方法。
背景技术
最近,对片上系统(SOC)进行了积极研究,在该片上系统中将具有不同功能的各种装置集成到一个芯片中。即,需要用于施加高电压的装置的厚栅电介质层以改良可靠性,且需要用于对操作速度敏感的装置的薄栅电介质层。同样,已研究双多晶硅栅结构,以改良该装置操作速度,并获得N沟道金属氧化物半导体场效晶体管(NMOSFET)及P沟道金属氧化物半导体场效晶体管(PMOSFET),以具有对称阈值电压。
图1A为展示具有双栅电介质层的传统半导体器件的结构的图。
如图所示,硅基板11分成单元区,其中将形成NMOS晶体管,及外围区,其中将形成NMOS晶体管及PMOS晶体管。在设置于该单元区中的硅基板11上形成第一栅电介质层12,且在设置于其中将形成NMOS晶体管的该外围区的区中的硅基板11上形成第二栅电介质层13A。同样,在设置于其中将形成PMOS晶体管的该外围区的区中的硅基板11上形成第三栅电介质层13B。
在该单元区中的该第一栅电介质层12上形成第一栅结构21,其包括n+型硅电极14A、低电介质金属电极15及栅硬掩模16。在该外围区中,在该第二绝缘层13A上形成第二栅结构22,其包括该n+型硅电极14A、该低电介质金属电极15及该栅硬掩模16。同样,在该外围区中的该第三栅电介质层13B上形成第三栅电介质层13B,其包括p+型硅电极14B、该低电介质金属电极15及该栅硬掩模16。
此处,在该单元区中形成的第一栅电介质层12具有比在该外围区中形成的第二及第三栅电介质层13A及13B更厚的厚度。同样,第一及第二栅电介质层12及13A为通过利用热氧化过程而形成的硅氧化物(SiO2)层,而第三栅电介质层13B为氮化物层。
然而,在一个芯片中实现具有不同厚度的第一至第三栅电介质层存在若干困难。首先,在不同区中通过使用热过程形成具有不同厚度的栅电介质层12、13A及13B比较复杂。第二,在外围区中PMOS晶体管的P+型硅电极14B之下形成的栅电介质层13B应由氮化物而不是氧化物制成,以防止硼的渗透。当栅电介质层13B由氮化物制成时,氮化物存在于栅电介质层13B与该硅基板11之间的接口处。存在于该接口处的氮化物导致载流子的迁移率降低,其进一步导致装置速度下降。
图1B为将纯硅氧化物的标准化(normalized)跨导(Gm)与氮化物的标准化跨导相比较的图。
如图所示,氮化物具有比纯硅氧化物的跨导电平低的跨导电平。通常,已知随着作为表示晶体管特性的一个参数的跨导电平更高,晶体管特性变得更佳。
发明内容
因此,本发明的目标为提供一种具有不同厚度的多栅电介质层的半导体器件,其中该多栅电介质层可通过简单过程在一个芯片内形成,同时满足所要达到的目的,并抑制了载流子迁移率的降低,以及提供一种用于制造其的方法。
根据本发明的一方面,提供了一种半导体存储器装置,其包括:硅基板,其分成单元区,其中形成NMOS晶体管,及外围区,其中形成NMOS及PMOS晶体管;在设置于该单元区的该硅基板上形成的目标硅氧化物层;在设置于该外围区的该硅基板上形成的氧氮化物(oxynitride)层;在该目标硅层上形成的第一栅结构,且其包括n+型硅电极、低阻硅电极及栅硬掩模;在设置于该外围区的NMOS区的该氧氮化物层上形成的第二栅结构,且其包括该n+型硅电极、该低阻硅电极及该栅硬掩模;及在设置于该外围区的PMOS区的该氧氮化物层上形成的第三栅结构,且其包括p+型硅电极、该低阻金属电极及该栅硬掩模。
根据本发明的另一方面,提供了一种用于制造半导体器件的方法,其包括以下步骤:通过执行第一氧化过程而在硅基板上形成硅氧化物层,该硅基板被分成单元区,其中形成NMOS晶体管,及外围区,其中形成NMOS及PMOS晶体管;选择性地移除在该外围区中的硅氧化物层;同时地在该外围区中的硅基板曝露表面上形成硅-氮键,并在该单元区中剩余的硅氧化物层表面上形成硅-氧-氮键;且在具有硅-氮键的硅基板表面上形成氧氮化物层,并通过执行第二氧化过程而将具有该硅-氧-氮键的剩余硅氧化物层转换成目标硅氧化物层。
附图说明
本发明的上面的和其他的目标和特征将关于下面的结合附图给出的优选实施例的描述而被更好地理解。
图1A为展示具有多栅电介质层的传统半导体器件的截面图;
图1B为将纯硅氧化物层的标准化跨导特性与氮化物层的标准化跨导特性比较的图;
图2为展示根据本发明的优选实施例的具有多栅电介质层的半导体器件的截面图;
图3A至3G为用于说明一种根据本发明优选实施例的制造具有多栅电介质层的半导体器件的方法的截面图;以及
图4为展示根据本发明在使用等离子体氮化技术氮化硅氧化物层且其后再氧化该层时,氮及氧分布变化的图。
具体实施方式
将参看附图详细描述根据本发明的优选实施例的具有多栅电介质层的半导体器件及其制造方法。
图2为展示根据本发明的优选实施例的具有多栅电介质层的半导体器件的截面图。
如图所示,硅基板31被分成:单元区,其中将形成N沟道金属氧化物半导体(NMOS)晶体管;及外围区,其中将形成P沟道金属氧化物半导体(PMOS)晶体管和NMOS晶体管。在其中将形成NMOS晶体管的单元区中,在该硅基板31上形成目标硅氧化物层36B。在其中将形成NMOS及PMOS晶体管的外围区中,形成氧氮化物层36A。
在该单元区中的目标硅氧化物层36B上形成第一栅结构100,其包括n+型硅层37B、低阻金属电极40及栅硬掩模41。同样,在该外围区的NMOS区中的氧氮化物层36A上形成第二栅结构200,其包括该n+型硅层37B、该低阻金属电极40及该栅硬掩模41。在该外围区的PMOS区中的氧氮化物层36A上形成第三栅结构300,其包括p+型硅层37A、该低阻金属电极40及该栅硬掩模41。
在图2所示的半导体器件中,在该单元区中的目标硅氧化物层36B比在该外围区中的氧氮化物层36A厚。同样,通过氧化其中形成硅-氮键的硅基板31的表面来形成该氧氮化物层36A。另一方面,通过氧化其中形成硅-氧-氮键的硅氧化物层来形成该目标硅氧化物层36B。此外,该氧氮化物层36A含有以原子百分比测得的浓度范围在约5%至约30%的氮。
图3A至3G为用于说明一种根据本发明优选实施例的制造具有多栅电介质层的半导体器件的方法的截面图。应注意,相同参考数字用于图2中所描述的相同的配置元件。
参看图3A,通过执行第一氧化过程在提供有场氧化物层32的硅基板31上形成第一硅氧化物层33。即,通过氧化该硅基板31的表面来获取该第一硅氧化物层33。此处,该硅基板31被分成单元区及外围区。特别地,需要在该单元区中形成厚栅电介质层,而需要在该外围区中形成相对薄栅电介质层。在动态随机存取存储器(DRAM)装置中,将在该单元区中形成NMOS晶体管,而将在该外围区中形成NMOS及PMOS晶体管。同样,如图3A所示,在该单元区及在该外围区中的第一硅氧化物层33的厚度相同。此时,该第一硅氧化物层33的厚度在从约5至约100的范围内。
参看图3B,在该第一硅氧化物层33上形成感光层,且通过执行曝光过程及显影过程来将该感光层图案化,以形成用于遮蔽该单元区的第一掩模图案34。其后,通过使用该第一掩模图案34作为蚀刻阻挡来蚀刻在外围区中形成的该第一硅氧化物层33,且作为此蚀刻的结果,该外围区中的硅基板31的表面被曝光。参考数字33A表示以上选择性蚀刻过程之后在该单元区中的剩余第一硅氧化物层。在该外围区中,在以上选择性蚀刻过程之后,该第一硅氧化物层33不保持在该硅基板31上。
参看图3C,该第一掩模图案34被移除,且接着,执行等离子体氮化过程以氮化在该单元区中的剩余第一硅氧化物层33A的表面及在该外围区中的曝露的硅基板31的表面。通过该等离子体氮化过程,在该外围区中的硅基板31的表面上形成硅-氮(Si-N)键35A,且同时在该剩余第一硅氧化物层33A的表面上形成硅-氧-氮(Si-O-N)键35B。
此处,通过使用直接在硅基板31上产生氮等离子体的方法及首先在不同地方产生氮等离子体且接着通过仅在其上施加氮基团(radicals)而氮化该硅基板31的方法中的一种来执行该等离子体氮化过程。后一方法称作远程等离子体氮化方法。
对于上述等离子体氮化过程而言,用于产生该等离子体的源气体是选自由Ar/N2、Xe/N2、N2、NO、N2O及该等所列气体的混合气体构成的组。此时,用于产生该等离子体的功率在从约100W至约3,000W的范围内,且执行该等离子体氮化过程约5秒至约600秒。同样,该硅基板31的温度设定在约0℃至约600℃的范围内,且流动的源气体的量在约5sccm至约2,000sccm的范围内。
参看图3D,执行第二氧化过程,即,再氧化过程。此时,在其上形成硅-氮键35A的外围区中的硅基板31表面上,氧氮化物层36A,更特别地说,硅氧氮化物(SiON)层被形成为曝露于氧化环境的其上形成硅-氮键35A的硅基板31。此处,该氧氮化物层36A含有以原子百分比测得的浓度范围在约5%至约30%的氮。
然而,由于在再氧化过程期间硅-氧-氮键35B的氮原子扩散开,因此其上形成该硅-氧-氮键35B的剩余硅氧化物层33A被转换成纯硅氧化物(SiO2)层。此转换伴随厚度而增加。最后,该单元区中的剩余第一硅氧化物层33A被转换成第二硅氧化物层36B,其厚度与该剩余第一硅氧化物层33A相比增加了。下文,该第二硅氧化物层36B被称作目标硅氧化物层。
对于通过再氧化过程形成的氧氮化物层36A及目标硅氧化物层36B的厚度而言,因为在再氧化过程期间该硅-氮键35A的氮抑制氧化,所以该氧氮化物层36A的厚度比该目标硅氧化物层36B薄。即,在再氧化过程期间,该硅-氧-氮键35B的氮扩散开,且因此,由硅-氧-氮键35B的抑制效果比由硅-氮键35A产生的抑制效果弱。因此,在同时应用的再氧化过程期间,该目标硅氧化物层36B的厚度增加比该氧氮化物层35A的厚度增加更明显。
此处,由于硅-氮键35A比硅-氧-氮键35B具有更强的接合力,因此硅-氮键35A的氮几乎不扩散开。同样,氮化的剩余第一硅氧化物层33A对于该氧化而言具有较低程度的抵抗,且结果,该氮化的剩余第一硅氧化物层33A的厚度极大程度地增加。另一方面,该氮化的硅基板31对于该氧化而言具有较高程度的抵抗,且结果,该硅基板31厚度增加是低的。
参看图3E,在该氧氮化物层36A及该目标硅氧化物层36B上形成未掺杂硅层37。然后,在该未掺杂硅层37上形成感光层,并通过执行曝光过程及显影过程来将该感光层图案化,以形成第二掩模图案38。此处,该第二掩模图案38遮蔽该单元区及该外围区的NMOS区,而开放(open)该外围区的PMOS区。
接着,通过使用该第二掩模图案38作为离子注入阻挡,在第三周期中的元素的掺杂剂,即,p型掺杂剂被离子注入。此时,第三周期元素的掺杂剂是选自由硼(B)、氟化硼(BF)及二氟化硼(BF2)构成的组。通过应用约2keV至约30keV的范围内的能量及在约1×1015原子/cm2至约1×1016原子/cm2的范围内的掺杂剂剂量来执行该离子注入。
特别地,将采用上述第三周期元素的掺杂剂的离子注入应用至设置于该外围区的PMOS区中的未掺杂硅层37。通过该离子注入过程,在该外围区的PMOS区中的未掺杂硅层37被转换成P+型硅电极37A。同样,由该第二掩模图案38遮蔽的未掺杂硅层37的一部分不被转换。
参看图3F,该第二掩模图案38被移除,且接着,在该未掺杂硅层37及该p+型硅电极37A上形成感光层,且通过曝光过程及显影过程将该感光层图案化以形成第三掩模图案39。此处,该第三掩模图案39遮蔽该外围区的PMOS区,而开放该单元区及该外围区的NMOS区。
随后,该未掺杂硅层37经受采用第五周期元素的掺杂剂(即,n型掺杂剂)的离子注入过程。此时,第五周期元素掺杂剂为磷(P)与砷(As)中的一种。通过应用在约3keV至约50keV的范围内的能量及在约1×1015原子/cm2至约1×1016原子/cm2的范围内的剂量来执行该离子注入过程。作为此离子注入过程的结果,设置于该单元区与该外围区的NMOS区中的未掺杂硅层37被转换成n+型硅电极37B。
参看图3G,该第三掩模图案39被移除,且接着,低阻金属电极40与栅硬掩模41被顺序地形成在该p+型硅电极37A及该n+型硅电极37B上。此时,该低阻金属电极40是由选自由钨、钨氮化物及钨硅化物构成的组的材料制成。该栅硬掩模41由氮化物制成。然后,执行栅图案化过程,以分别在该单元区、该外围区的NOMS区及该外围区的PMOS区中形成第一至第三栅结构100至300。分别在该单元区的NMOS区中及在该外围区的NMOS区中形成的第一及第二栅结构100与200具有包括n+型硅电极37B及低阻金属电极40的双栅电极结构。另一方面,在该外围区的PMOS区中形成的第三栅结构300具有包括p+型硅电极37A及低阻金属电极40的双栅电极结构。
图4为展示当硅氧化物层通过等离子体氮化技术被氮化且其后被氧化时,氧及氮分布的变化的图。此处,参考符号○及●表示氮分布,而而参考符号■及□表示氧分布。尤其,实心圆与实心正方形的参考符号●和■分别表示再氧化过程之前的氮分布与氧分布。同样,空心圆与空心正方形的参考符号○和□分别表示再氧化过程之后的氮分布与氧分布。
如图所示,高水平的氮存在于通过等离子体氮化技术氮化的硅氧化物层的表面上。然而,氮的浓度因该再氧化过程而降低。
对于该氧分布而言,通过再氧化过程,该硅氧化物层厚度增加。
根据优选实施例,在该单元区中的NMOS晶体管使用目标硅氧化物层36B作为栅电介质层,而在该外围区中的NMOS晶体管及PMOS晶体管使用氧氮化物层36A作为其厚度较薄的栅电介质层。因此,可能在一个芯片内形成具有不同厚度的双栅电介质层。
如上所述,通过诸如等离子体氮化过程及再氧化过程的简单过程,可在一芯片内选择性地形成每个具有不同厚度的目标硅氧化物层36B及氧氮化物层36A。因此,要求对载流子迁移率高度敏感及好的可靠性的单元区中的NMOS晶体管使用目标硅氧化物层36B作为栅电介质层,而要求对硼的渗透高度敏感的外围区中的PMOS晶体管使用氧氮化物层36A作为栅电介质层。
举例而言,在将此双栅电介质层实施至DRAM装置的状况下,由于在该单元区中的NMOS晶体管要求对该载流子迁移率高度敏感及好的可靠性,因此该厚的目标硅氧化物层36B用作栅电介质层。同样,在该外围区中的PMOS晶体管使用氧氮化物层36A作为栅电介质层,以防止在p+型硅电极37A上掺杂的第三周期元素的掺杂剂渗透至栅电介质层中。
因此,基于本发明的优选实施例,选择性地形成的双电介质层(即,目标硅氧化物层及氧氮化物层)提供了确保在该单元区中的晶体管要求的预期等级的载流子迁移率及可靠性,并解决了在该外围区中硼渗透的问题的效果。同样,具有不同厚度的双栅电介质层提供了实现可用于各种目的的晶体管的另一效果。
本申请案含有关于2004年12月29日在韩国专利局申请的韩国专利申请案第KR 2004-0115352号的主题,其全文以引用的方式并入本文中。
尽管关于特定优选实施例描述了本发明,但是熟习此项技术者应明了,可在不偏离以下权利要求所界定的本发明的精神及范畴的情况下作出各种改变及修改。
主要组件符号说明
11 硅基板
12 第一栅电介质层
13A 第二栅电介质层
13B 第三栅电介质层
14A n+型硅电极
14B p+型硅电极
15 低电介质金属电极
16 栅硬掩模
21 第一栅结构
22 第二栅结构
31 硅基板
32 场氧化物层
33 第一硅氧化物层
33A 剩余第一硅氧化物层
34 第一掩模图案
35A 硅-氮键
35B 硅-氧-氮键
36A 氧氮化物层
36B 目标硅氧化物层
37 未掺杂硅层
37A p+型硅电极
37B n+型硅电极
38 第二掩模图案
39 第三掩模图案
40 低阻金属电极
41 栅硬掩模
100 第一栅结构
200 第二栅结构
300 第三栅结构。
Claims (13)
1.一种半导体存储器器件,其包含:
硅基板,其被分成单元区,其中形成NMOS晶体管,及外围区,其中形成NMOS及PMOS晶体管;
目标硅氧化物层,在设置于该单元区中的该硅基板上形成;
氧氮化物层,在设置于该外围区中的该硅基板上形成;
第一栅结构,在该目标硅层上形成,且包括n+型硅电极、低阻硅电极及栅硬掩模;
第二栅结构,在设置于该外围区的NMOS区中的该氧氮化物层上形成,并且包括该n+型硅电极、该低阻硅电极及该栅硬掩模;及
第三栅结构,在设置于该外围区的PMOS区中的该氧氮化物层上形成,并且包括p+型硅电极、该低阻金属电极及该栅硬掩模。
2.如权利要求1的半导体器件,其中该目标硅氧化物层具有比该氧氮化物层大的厚度。
3.如权利要求1的半导体器件,其中该氧氮化物层是通过氧化在其上形成硅-氮键的该硅基板的表面来形成,且该目标硅氧化物层是通过氧化在该硅基板上形成的硅氧化物层来形成,且在其上形成硅-氧-氮键。
4.如权利要求1的半导体器件,其中该氧氮化物层含有原子百分比浓度范围在约5%至约30%的氮。
5.如权利要求1的半导体器件,其中该n+型硅电极是通过离子注入磷与砷中的一种而形成。
6.如权利要求1的半导体器件,其中该p+型硅电极是通过离子注入硼、硼氟化物及二氟化硼中的一种而形成。
7.一种用于制造半导体器件的方法,其包含以下步骤:
通过执行第一氧化过程来在硅基板上形成硅氧化物层,该硅基板被分成单元区,其中形成NMOS晶体管,及外围区,其中形成NMOS及PMOS晶体管;
选择性地移除在该外围区中的该硅氧化物层;
同时在该外围区中的该硅基板的曝露表面上形成硅-氮键,并在该单元区中剩余的该硅氧化物层的表面上形成硅-氧-氮键;
通过执行第二氧化过程来在具有该硅-氮键的该硅基板的该表面上形成氧氮化物层,并将具有该硅-氧-氮键的该剩余硅氧化物层转换成目标硅氧化物层。
8.如权利要求7的方法,其中通过采用等离子体氮化过程来执行形成该硅-氮键及该硅-氧-氮键的该步骤。
9.如权利要求8的方法,其中通过采用用于在该硅基板及该硅氧化物层顶部上直接形成氮等离子体的方法及远程等离子体氮化方法中的一种来执行该等离子体氮化过程。
10.如权利要求9的方法,其中通过采用选自由Ar/N2、Xe/N2、N2、NO、N2O及该所列气体的混合气体所构成的组的源气体,连同在约100W至约3,000W的范围内的施加的功率、维持在约0℃至约600℃的范围的该硅基板温度及在约5sccm至约2,000sccm的范围内的该流动的源气体量,来执行该等离子体氮化过程约5秒至约600秒。
11.如权利要求7的方法,其中该目标硅氧化物层比该氧氮化物层厚。
12.如权利要求7的方法,该第二氧化过程之后,进一步包括以下步骤:
在该目标硅氧化物层及该氧氮化物层上形成未掺杂硅层;
将P型掺杂剂离子注入设置于该外围区的PMOS区中的该未掺杂硅层的一部分上,以形成p+型硅电极;
将n型掺杂剂离子注入设置于该单元区及该外围区的NMOS区中的该未掺杂硅层的另一部分上,以形成n+型硅电极;
在该p+型硅电极及该n+型硅电极上形成低阻金属电极;
在该低阻金属电极上形成栅硬掩模;及
图案化该栅硬掩模、该低阻金属电极、该p+型硅电极及该n+型硅电极,以形成栅结构。
13.如权利要求7的方法,其中通过该第一氧化过程形成的该硅氧化物层具有在约5至约100的范围内的厚度。
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JP (1) | JP4545046B2 (zh) |
KR (1) | KR100611784B1 (zh) |
CN (1) | CN1797769B (zh) |
DE (1) | DE102005024798B4 (zh) |
TW (1) | TWI304999B (zh) |
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WO2023123762A1 (zh) * | 2021-12-28 | 2023-07-06 | 长鑫存储技术有限公司 | 一种半导体结构及其形成方法 |
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-
2004
- 2004-12-29 KR KR1020040115352A patent/KR100611784B1/ko not_active IP Right Cessation
-
2005
- 2005-05-26 DE DE102005024798A patent/DE102005024798B4/de not_active Expired - Fee Related
- 2005-06-02 JP JP2005162180A patent/JP4545046B2/ja not_active Expired - Fee Related
- 2005-06-02 TW TW094118197A patent/TWI304999B/zh not_active IP Right Cessation
- 2005-06-09 CN CN200510076926XA patent/CN1797769B/zh not_active Expired - Fee Related
- 2005-09-16 US US11/227,156 patent/US7563726B2/en not_active Expired - Fee Related
-
2009
- 2009-06-15 US US12/457,540 patent/US20100013022A1/en not_active Abandoned
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102403197A (zh) * | 2010-09-08 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | 一种激活掺杂原子的方法 |
CN102403197B (zh) * | 2010-09-08 | 2013-11-20 | 中芯国际集成电路制造(上海)有限公司 | 一种激活掺杂原子的方法 |
CN104347501A (zh) * | 2013-08-07 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN104347501B (zh) * | 2013-08-07 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
WO2023123762A1 (zh) * | 2021-12-28 | 2023-07-06 | 长鑫存储技术有限公司 | 一种半导体结构及其形成方法 |
US11862461B2 (en) | 2021-12-28 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method of forming oxide layer on a doped substrate using nitridation and oxidation process |
Also Published As
Publication number | Publication date |
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TW200623209A (en) | 2006-07-01 |
US20100013022A1 (en) | 2010-01-21 |
CN1797769B (zh) | 2010-09-29 |
US20060138550A1 (en) | 2006-06-29 |
JP4545046B2 (ja) | 2010-09-15 |
KR100611784B1 (ko) | 2006-08-10 |
KR20060075968A (ko) | 2006-07-04 |
DE102005024798B4 (de) | 2011-11-10 |
US7563726B2 (en) | 2009-07-21 |
DE102005024798A1 (de) | 2006-07-13 |
JP2006190942A (ja) | 2006-07-20 |
TWI304999B (en) | 2009-01-01 |
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