JP2006253401A - 半導体装置の製造方法及び絶縁膜の成膜速度の調整方法 - Google Patents
半導体装置の製造方法及び絶縁膜の成膜速度の調整方法 Download PDFInfo
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Abstract
【解決手段】 シリコン基板1の第1の活性領域100と第2の活性領域110に、第1のゲート電極4−1と第2のゲート電極4−1を形成する。第1のシリコン酸化膜5を形成後、シリコン酸化膜5を介して不純物イオンを注入し、第1の活性領域100と第2の活性領域110に、第1の低濃度領域6−1と第2の低濃度領域6−2を形成する。その後、第1の活性領域100の第1のシリコン酸化膜5を除去し、第2の活性領域110では第1のシリコン酸化膜5を残存させる。オゾン及びテトラエトキシシランの熱分解CVD法により、第1の活性領域100に膜厚が第2の活性領域110より厚い膜厚NSG絶縁膜8を形成し、第1の側壁絶縁膜9−1と第1の側壁絶縁膜9−1よりも薄い膜厚の第2の側壁絶縁膜9−2とを形成する。
【選択図】 図4
Description
尚、ゲート電極構造とは、ゲート電極とゲート絶縁膜とを含む構造を意味する。
(半導体装置の製造方法)
図1乃至図5は、本発明の第1実施形態に係る半導体装置の製造方法を示す部分縦断面図である。本実施形態によれば、高耐圧MOSFETと高速MOSFETとを同一基板上に形成する。高耐圧MOSFETは、ゲート電圧が高いため、膜厚の厚いサイドウォール絶縁膜を必要とする。一方、高速MOSFETは、ゲート電圧が低いため、膜厚の薄いサイドウォール絶縁膜を必要とする。
本実施形態によれば、第1の活性領域100と第2の活性領域110とで膜厚の異なるO3―TEOS―NSG膜8を成膜する方法が提供される。第1の活性領域100においては、第1の低濃度領域6−1上、即ちシリコン領域上にO3―TEOS―NSG膜8が成膜される。一方、第2の活性領域110においては、シリコン酸化膜5上にO3―TEOS―NSG膜8が成膜される。これにより、シリコン領域上のO3―TEOS―NSG膜8の成膜速度と、酸化シリコン領域上のO3―TEOS―NSG膜8の成膜速度との差を利用し、第1の活性領域100と第2の活性領域110とで膜厚の異なるO3―TEOS―NSG膜8を成膜する。シリコンと酸化シリコンとを下地領域として選択することは、第1の低濃度領域6−1及び第2の低濃度領域6−2の不純物の種類及びその濃度に依存することなく、熱分解CVD法におけるTEOS(テトラエトキシシラン)に対するO3(オゾン)の流量比のみを調整することで、第1の活性領域100と第2の活性領域110とでO3―TEOS―NSG膜8の膜厚の差を非常に広範囲に亘り調整することを可能にする。具体的には、TEOS(テトラエトキシシラン)に対するO3(オゾン)の流量比を5−15の範囲で調整することで、シリコン領域上のO3―TEOS―NSG膜8の成膜速度に対する、酸化シリコン領域上のO3―TEOS―NSG膜8の成膜速度の比を80%―40%の範囲で調整することができる。即ち、TEOS(テトラエトキシシラン)に対するO3(オゾン)の流量比を5−15の広範囲で調整することで、シリコン領域上に成膜されたO3―TEOS―NSG膜8に対する、酸化シリコン領域上に成膜されたO3―TEOS―NSG膜8の膜厚比を80%―40%の広範囲で調整することができる。
(半導体装置の製造方法)
図7乃至図11は、本発明の第2実施形態に係る半導体装置の製造方法を示す部分縦断面図である。本実施形態によれば、高耐圧MOSFETと高速MOSFETとを同一基板上に形成する。高耐圧MOSFETは、ゲート電圧が高いため、膜厚の厚いサイドウォール絶縁膜を必要とする。一方、高速MOSFETは、ゲート電圧が低いため、膜厚の薄いサイドウォール絶縁膜を必要とする。
本実施形態によれば、第1の活性領域100と第2の活性領域110とで膜厚の異なるO3―TEOS―NSG膜8を成膜する方法が提供される。第1の活性領域100においては、水素イオン(H+)が注入された第1の低濃度領域6−1上にO3―TEOS―NSG膜8が成膜される。一方、第2の活性領域110においては、水素イオン(H+)が注入されていない第2の低濃度領域6−2上にO3―TEOS―NSG膜8が成膜される。これにより、水素イオン(H+)が注入されたシリコン領域上のO3―TEOS―NSG膜8の成膜速度と、水素イオン(H+)が注入されていないシリコン領域上のO3―TEOS―NSG膜8の成膜速度との差を利用し、第1の活性領域100と第2の活性領域110とで膜厚の異なるO3―TEOS―NSG膜8を成膜する。水素イオン(H+)の選択的注入は、第1の低濃度領域6−1及び第2の低濃度領域6−2の不純物の種類及びその濃度に依存することなく、熱分解CVD法におけるTEOS(テトラエトキシシラン)に対するO3(オゾン)の流量比のみを調整することで、第1の活性領域100と第2の活性領域110とでO3―TEOS―NSG膜8の膜厚の差を非常に広範囲に亘り調整することを可能にする。具体的には、TEOS(テトラエトキシシラン)に対するO3(オゾン)の流量比を10−20の範囲で調整することで、水素イオン(H+)が注入されたシリコン領域上のO3―TEOS―NSG膜8の成膜速度に対する、水素イオン(H+)が注入されていないシリコン領域上のO3―TEOS―NSG膜8の成膜速度の比を80%―60%の範囲で調整することができる。即ち、TEOS(テトラエトキシシラン)に対するO3(オゾン)の流量比を10−20の広範囲で調整することで、水素イオン(H+)が注入されたシリコン領域上に成膜されたO3―TEOS―NSG膜8に対する、水素イオン(H+)が注入されていないシリコン領域上に成膜されたO3―TEOS―NSG膜8の膜厚比を80%―60%の広範囲で調整することができる。
2 フィールド酸化膜
3―1 第1のゲート酸化膜
3―2 第2のゲート酸化膜
4―1 第1のゲート電極
4―2 第2のゲート電極
5 シリコン酸化膜
6−1 第1の低濃度領域
6−2 第2の低濃度領域
7 レジストパターン
8 O3―TEOS―NSG膜8
9−1 第1のサイドウォール絶縁膜
9−2 第2のサイドウォール絶縁膜
10−1 第1の高濃度ソース/ドレイン領域
10−2 第2の高濃度ソース/ドレイン領域
12 シリコン酸化膜
13 レジストパターン
14 シリコン酸化膜
15 シリコン酸化膜
100 第1の活性領域
110 第2の活性領域
Claims (11)
- 膜厚の異なるサイドウォール絶縁膜を含む半導体装置の製造方法において、
シリコン基板の第1の活性領域と第2の活性領域とに、それぞれ、第1のゲート電極構造と第2のゲート電極構造とを選択的に形成する行程と、
前記第1の活性領域と前記第2の活性領域とに第1のシリコン酸化膜を形成する行程と、
前記第1のシリコン酸化膜を介して不純物をイオン注入することで、前記第1の活性領域と前記第2の活性領域とに、それぞれ、第1の低濃度領域と第2の低濃度領域とを形成する行程と、
前記第1の活性領域において前記第1のシリコン酸化膜を除去する一方で、前記第2の活性領域において前記第1のシリコン酸化膜を残存させる行程と、
オゾン及びテトラエトキシシランを原料とした熱分解CVD法により、前記第1の活性領域における前記シリコン基板上及び前記第2の活性領域における前記第1のシリコン酸化膜上に、前記第1の活性領域における膜厚が前記第2の活性領域における膜厚より厚い絶縁膜を形成する行程と、
前記絶縁膜をエッチングして、前記第1のゲート電極構造の側壁には第1のサイドウォール絶縁膜を形成し、前記第2のゲート電極構造の側壁には前記第1のサイドウォール絶縁膜より薄い膜厚を有する第2のサイドウォール絶縁膜を形成する行程とを含むことを特徴とする半導体装置の製造方法。 - 前記熱分解CVD法は、テトラエトキシシランに対するオゾンの流量比を5−15の範囲で行うことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1のシリコン酸化膜は、100Å―500Åの範囲の膜厚を有することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の低濃度領域と前記第2の低濃度領域とは、同一導電型の不純物を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 膜厚の異なるサイドウォール絶縁膜を含む半導体装置の製造方法において、
シリコン基板の第1の活性領域と第2の活性領域とに、それぞれ、第1のゲート電極構造と第2のゲート電極構造とを選択的に形成する行程と、
前記第1の活性領域と前記第2の活性領域とに、それぞれ、第1の低濃度領域と第2の低濃度領域とを形成する行程と、
前記第1の活性領域のみに水素イオンを注入する行程と、
オゾン及びテトラエトキシシランを原料とした熱分解CVD法により、水素イオンが注入された前記第1の活性領域における前記シリコン基板上及び水素イオンが注入されていない前記第2の活性領域における前記第1のシリコン基板上に、前記第1の活性領域における膜厚が前記第2の活性領域における膜厚より厚い絶縁膜を形成する行程と、
前記絶縁膜をエッチングして、前記第1のゲート電極構造の側壁には第1のサイドウォール絶縁膜を形成し、前記第2のゲート電極構造の側壁には前記第1のサイドウォール絶縁膜より薄い膜厚を有する第2のサイドウォール絶縁膜を形成する行程とを含むことを特徴とする半導体装置の製造方法。 - 前記熱分解CVD法は、テトラエトキシシランに対するオゾンの流量比を10−20の範囲で行うことを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記第1の低濃度領域と前記第2の低濃度領域とは、同一導電型の不純物を含むことを特徴とする請求項5に記載の半導体装置の製造方法。
- オゾン及びテトラエトキシシランを原料とした熱分解CVD法における絶縁膜の成膜速度の調整方法において、
テトラエトキシシランに対するオゾンの流量比を調整することで、シリコンからなる第1の領域上の前記絶縁膜の成膜速度に対する、酸化シリコンからなる第2の領域上の前記絶縁膜の成膜速度の比を調整することを特徴とする絶縁膜の成膜速度の調整方法。 - テトラエトキシシランに対するオゾンの流量比を5−15の範囲で調整することを特徴とする請求項8に記載の成膜速度の調整方法。
- オゾン及びテトラエトキシシランを原料とした熱分解CVD法における絶縁膜の成膜速度の調整方法において、
テトラエトキシシランに対するオゾンの流量比を調整することで、水素イオンが注入されたシリコンからなる第1の活性領域上の前記絶縁膜の成膜速度に対する、水素イオンが注入されていないシリコンからなる第2の活性領域上の前記絶縁膜の成膜速度の比を調整することを特徴とする絶縁膜の成膜速度の調整方法。 - テトラエトキシシランに対するオゾンの流量比を10−20の範囲で調整することを特徴とする請求項10に記載の成膜速度の調整方法。
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