CN1791305A - 电路部件模块及其制造方法和电子电路装置 - Google Patents
电路部件模块及其制造方法和电子电路装置 Download PDFInfo
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- CN1791305A CN1791305A CNA2005101295580A CN200510129558A CN1791305A CN 1791305 A CN1791305 A CN 1791305A CN A2005101295580 A CNA2005101295580 A CN A2005101295580A CN 200510129558 A CN200510129558 A CN 200510129558A CN 1791305 A CN1791305 A CN 1791305A
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- circuit component
- resin bed
- component module
- heating panel
- wiring
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Abstract
本发明的目的在于提供高精度、可靠性高、并且能够低成本生产的电路部件模块及其制造方法。本发明提供电路部件模块(100),其特征在于,包括:散热板(8);叠层在散热板(8)的一个面(8b)上的树脂层(6);埋入在树脂层(6)中并且其一部分连接到散热板(8)的电子部件(31);以及埋入在树脂层(6)的与散热板相反侧的面(6a)并与电子部件(31)一起构成电路的布线图形(5)。
Description
技术领域
本发明涉及电路部件模块和电子电路装置及电路部件模块的制造方法。
背景技术
例如,在便携式电话和PDA等的便携式电子设备中,为了小型重量轻和低成本,正在采用将电路基板和各种部件一体化的薄板状的电路部件模块。这种电路部件模块,例如,如专利文献1和专利文献2中所示,是在树脂等的基板内埋入各种部件,在表面上形成导电性的电路图形,由于被形成为凹凸很少的平板状,薄型重量轻并且批量生产性优良,所以适合作为要求小型重量轻的便携式电子设备的部件基板。
[专利文献1]日本专利特开2001-358465号公报
[专利文献2]日本专利特开平11-220262号公报
但是,在专利文献1中记载的电路部件模块,在配置部件后用辊涂机(roll coater)等涂敷、烧结有机聚合物后,形成用于布线的接触孔,所以担心因树脂表面的凹凸而不能良好地确保部件接合的精度。此外,存在因芯片焊盘(chip pad)上的树脂残渣而容易产生导通不良、因部件和树脂之间产生的应力而容易产生接合部中的损伤等这样的问题。
此外,即使在专利文献2中记载的电路部件模块,也存在因制造工序中的热和应力而容易产生接合部中的损伤的问题。而且,由于需要多次进行图形之间的位置配合工序,所以容易导致加工精度的下降,也存在制造成本提高的问题。
而且,在将功率IC(power IC)等发热量大的电子部件作为电路部件模块的结构部件来采用的情况下,需要考虑功率IC的排热方法。
发明内容
本发明鉴于上述情况而完成,其目的在于提供高精度、可靠性高、并且可低成本生产的电路部件模块及其制造方法。此外,其目的在于提供一种电子电路装置,作为电子部件,在采用功率IC等的发热量大的部件的情况下,可向模块外部高效率地排热。
为了实现上述目的,本发明采用以下结构。
本发明的电路部件模块的特征在于包括:散热板;叠层在所述散热板的一个面上的树脂层;埋入在所述树脂层中并且其一部分连接到所述散热板的电子部件;以及埋入在所述树脂层的与所述散热板相反侧的面中并与所述电子部件一起构成电路的布线图形。
此外,在本发明的电路部件模块中,也可以为以下结构:包括两个上述电路部件模块,各电路部件模块的树脂层相互对置配置,并且在各树脂层之间夹着另一树脂层,这些树脂层被一体地接合。
此外,在本发明的电路部件模块中,也可以是以下结构,包括:散热板;分别叠层在所述散热板的两面上的一对树脂层;分别埋入在所述一对树脂层中并且一部分分别连接到所述散热板的电子部件;以及分别埋入在所述一对树脂层的与所述散热板相反侧的面中并与所述各电子部件一起构成电路的布线图形。
根据上述结构,电子部件和布线图形被埋入在各树脂层中,所以可以保护布线图形,并且实现电路部件模块本身的薄型化。同时,可以提高电子部件和布线图形的连接可靠性。此外,由于各电子部件连接到散热板,所以可以将随着电子部件的驱动而产生的热通过该散热板排热到电路部件模块的外部。
此外,在各电路部件模块的树脂层之间相互对置来配置的情况下,散热板被配置在电路部件模块的外侧,由此可以将散热板作为电路部件模块的外封装板。此外,通过在各电路部件模块之间夹着另一树脂层,可以将电路部件模块之间容易地接合。
而且,在使电子部件接合在散热板的两面上的情况下,可以减少散热板相对于电子部件的数目,可以简化结构。
此外,在本发明的电路部件模块中,最好是所述电子部件由具有散热部的部件本体部和安装在该部件本体部的端子部构成,所述散热部露出所述树脂层的散热板侧的面,并且所述端子部被配置在与散热板的相反侧并连接到所述布线图形的一部分。
根据这种结构,由于散热部在散热板侧的面上露出,所以可以使热量高效率地排热。此外,由于端子部连接到被埋入于树脂层中的布线图形,所以可以提高布线图形和端子部的连接可靠性。
此外,本发明的电路部件模块的特征在于,在上述电路部件模块中,在所述电子部件的散热部和所述散热板之间,配置导热性粘合剂。根据这种结构,可以提高电子部件和散热板之间的导热性,可以高效率地排热。
此外,本发明的电路部件模块的特征在于,在上述电路部件模块中,在所述树脂层中设置被填充了导电膏的通孔,填充了导电膏的各通孔连接到所述布线图形。根据这种结构,可以将相互叠层的电路部件模块的布线图形之间通过通孔来连接,所以可以构成具有各个电路部件模块的功能的模块。
此外,本发明的电路部件模块的特征在于,在上述电路部件模块中,在所述散热板中,设置用于贯通被填充了所述导电膏的通孔的贯通孔。根据这种结构,可以防止通孔和散热板的短路。
此外,本发明的电路部件模块的特征在于,在上述电路部件模块中,所述电子部件是功率IC。根据这种结构,可以将电路部件模块作为高频模块来使用。
此外,本发明的电子电路装置的特征在于,包括上述电路部件模块,所述各散热板是兼用作接地端子的外封装盖。
根据这种电子电路装置,由于包括上述电路部件模块,所以可以实现电子电路装置本身的薄型化。同时,可以提高电子部件和布线图形的连接可靠性。此外,由于各电子部件连接到散热板,所以可以将随着电子部件的驱动而产生的热量通过该散热板排热到电子电路装置的外部。此外,由于散热板是兼用作接地端子的外封装盖,所以可以通过散热板来屏蔽外部电波对在布线图形上传输的信号的影响、以及因该信号自身的辐射电磁场造成的影响。
而且,由于构成电路部件模块的散热板和树脂层及电子部件的相互尺寸精度高,所以特别是在将电子电路装置作为高频模块使用的情况下,可以使其发挥如设计性能那样的模块性能。
此外,本发明的电子电路装置的特征在于,包括前面记载的电路部件模块,在构成该电路部件模块的所述一对树脂层的外侧分别形成介质层,并且在各介质层的外侧包括兼用作接地端子的外封装盖。
根据上述结构,根据在外封装盖和树脂层之间配置的介质层的厚度,可以调整兼用作接地端子的外封装盖和树脂层内部的电子部件及布线图形的间隔,特别是在将电子电路装置作为高频模块来使用的情况下,可以使其发挥如设计性能那样的模块性能。
其次,本发明的电路部件模块的制造方法的特征在于,包括:在版基板的整个面上形成种子层(seed layer),并且通过镀敷在该种子层上形成多个布线部构成的布线图形,进而在所述布线部上安装电子部件的安装工序;在所述版基板的布线图形上,通过依次叠层带有贯通孔的树脂层和散热板并将它们热压接,从而将所述布线部埋入所述树脂层、并且在所述贯通孔内插入所述电子部件而使该电子部件接合于所述散热板中的叠层工序;以及除去所述版基板和所述种子层的除去工序。
根据上述结构,通过将布线图形埋入在树脂层中,并且在贯通孔内部插入电子部件,可以使电路部件模块本身为薄型。此外,通过使电子部件接合在散热板中,可以提高电子部件和散热板之间的导热性。
此外,本发明的电路部件模块的制造方法的特征在于,准备两个按照前面记载的制造方法制造的电路部件模块,各电路部件模块的树脂层之间相互对置来配置,并且在各树脂层之间夹着另一树脂层,将它们热压接。
根据这种结构,通过各电路部件模块的树脂层之间相互对置来配置,散热板被配置在电路部件模块的外侧,由此可以将散热板作为电路部件模块的外封装板。此外,通过在各电路部件模块之间夹着另一树脂层,可以将电路部件模块之间容易地接合。
此外,本发明的电路部件模块的制造方法的特征在于,包括:在版基板的整个面上形成种子层,并且通过镀敷在该种子层上形成多个布线部构成的布线图形,进而在所述布线部上安装电子部件的安装工序;在散热板的两面上分别叠层带有贯通孔的树脂层,并且在所述布线图形面向各树脂层侧的状态下,在各树脂层中叠层一对所述版基板,并通过对它们进行热压接,将所述各布线部埋入所述各树脂层,并且在所述各贯通孔内插入所述各电子部件,从而使这些电子部件分别接合至所述散热板的叠层工序;以及除去所述版基板和所述种子层的除去工序。
根据上述结构,通过将布线图形埋入树脂层,并且在贯通孔内部插入电子部件,可以使电路部件模块本身形成为薄型。此外,通过使电子部件接合至散热板,可以提高电子部件和散热板之间的导热性。而且,由于在散热板的两面上接合电子部件,所以可以减少散热板相对于电子部件的数目,可以降低部件数目并简化工序。
根据本发明,可以提供高精度、可靠性高、并且可低成本生产的电路部件模块及其制造方法。此外,可以提供一种电子电路装置,作为电子部件,在采用功率IC等的发热量大的部件的情况下,可向模块外部高效率地排热。
附图说明
图1A至图1F是表示本发明第1实施方式的电路部件模块的制造工序的一例的剖面示意图。
图2A至图2C是表示本发明第1实施方式的电路部件模块的制造工序的一例的剖面示意图。
图3A至图3D是表示叠层两个电路部件模块的工序的剖面示意图。
图4A至图4C是表示本发明第2实施方式的电路部件模块的制造工序的一例的剖面示意图。
图5A至图5D是表示本发明第2实施方式的电路部件模块的制造工序的一例的剖面示意图。
图6是表示本发明第3实施方式的电子电路装置的一例的剖面示意图。
图7A至图7B是表示本发明第4实施方式的电子电路装置的制造工序的一例的剖面示意图。
图8A至图8B是表示布线图形的另一例子的剖面示意图。
具体实施方式
[第1实施方式]
以下,参照附图来说明本发明第1实施方式的电路部件模块及其制造方法。
本实施方式的电路部件模块的制造方法大致包括:在版基板上形成种子层和布线图形,并且对电子部件进行安装的安装工序;在版基板上叠层树脂层和散热板的工序;以及除去版基板和种子层的除去工序。
若对各工序的概略进行说明,则首先安装工序是在版基板上叠层种子层,并且在该种子层上形成布线图形,进而在该布线图形中安装电子部件的工序。另外,叠层工序是在版基板上配置带有贯通孔的树脂层和散热板,将所述电子部件容纳在所述贯通孔中,同时在所述版基板中叠层所述树脂层和散热板的工序。而且,除去工序是从所述树脂层中除去所述版基板和所述种子层的工序。
以下,参照附图说明各工序的细节。图1是表示安装工序的工序图,图2是表示叠层工序和除去工序的工序图。再有,在本实施方式中参照的附图是用于说明电路部件模块和其制造方法的图,图示的各部分的大小、厚度和尺寸等不必与实际的电路部件模块的尺寸关系一致。
[安装工序]
首先,在安装工序,准备图1A所示的版基板1,接着如图1A和图1B所示,在包含版基板1的一面上1a的整个面上形成种子层2。种子层2例如可以采用由膜厚度50nm至500nm的氧化锌层2a和在氧化锌层2a上叠层了膜厚度2μm左右的金属铜层2b构成的叠层膜。通过在版基板1的全部表面上形成种子层2,可以提高版基板1与后述的布线图形之间的剥离性。氧化锌层2a例如可以通过将版基板1投入到包含氧化锌的镀敷液中后,以无电镀(electroless plating)法来形成。再有,种子层2也可以仅形成在版基板1的一个面1a上。
此外,版基板1的整个面由氧化硅形成,所以可以提高与构成种子层的氧化锌层2a的粘结性,并且在可以再利用版基板1方面较好。作为版基板1的具体例子,例如,可以使用包含以氧化硅为主要成分的玻璃板、通过热氧化法或热CVD法使整个面形成氧化硅层的硅基板、用溅射法等使氧化硅层覆盖在整个面上的树脂基板或介质基板等。此外,作为所述硅基板,也可以采用添加了B、P、As等的掺杂物的基板。而且,作为所述树脂基板,可以是具有挠性的树脂基板,这种情况下,由于可以将长的树脂基板卷绕成滚筒状,所以适合连续性的制造,可以提高生产性。版基板1的厚度没有特别限制,例如可以使用30μm至3mm的厚度。
此外,就版基板1来说,特别优选采用硬质的基板。在后述的叠层工序中将电子部件埋入树脂层时,硬质的基板成为布线图形的垫板,可以防止埋入时的应力造成的布线图形的变形。
接着,如图1C所示,在种子层2上,形成具有多个抗蚀剂(resist)除去部4a的图形化抗蚀剂(patterned resist)层4(抗蚀剂图形)。具体地说,在种子层2上例如叠层10μm左右的感光性树脂膜或干膜抗蚀剂(dry film resist)(以下称为抗蚀剂层)后,通过重叠掩模并进行曝光、显影,形成与掩模的图形对应的抗蚀剂除去部4a。这样形成具有抗蚀剂除去部4a的图形化抗蚀剂层4。
再有,在形成了图形化抗蚀剂层4的抗蚀剂除去部4a中,有时残留感光性树脂膜或干膜抗蚀剂的残渣。如果残留这种残渣,则有可能在其后形成的布线图形断线,布线图形和种子层2的粘结性下降而在后面工序——压接工序和剥离工序中产生不良状况。因此,以完全除去残渣为目的,在形成了图形抗蚀剂层4后,优选对抗蚀剂除去部4a照射氩等离子体,或通过对露出抗蚀剂除去部4a的种子层2的表面进行轻微蚀刻,除去残渣。在照射氩等离子体的情况下,例如,在等离子体功率为500W左右、环境气体压力10Pa以下、氩流量为50sccm、照射时间为30秒的条件下进行较好。此外,就对种子层的表面进行轻微蚀刻来说,可在10%的醋酸水溶液构成的蚀刻剂中进行30秒处理的条件下进行。通过这样的处理,可以使种子层2和布线图形的粘结强度达到3N/cm以上。
接着,如图1D所示,在抗蚀剂除去部4a中以镀敷法形成Cu构成的布线图形(布线部)5。具体地说,例如,使包含了硫酸铜等镀敷液接触抗蚀剂除去部4a内的种子层2后,对种子层2施加直流电流而使镀敷铜生长。布线图形5的厚度比图形化抗蚀剂层4的厚度薄较好,例如5μm左右就可以。
接着,如图1E所示,通过湿法蚀刻,除去图形化抗蚀剂层4。这样,在版基板1上,形成种子层2和布线图形5。
接着,如图1F所示,在布线图形5上安装功率IC31(电子部件)。功率IC31大致由具有散热部的IC本体(部件本体)32、配置在IC本体32下侧的例如金构成的球形凸点(ball bumps)33(端子部)构成。功率IC元件被内置在IC本体32中。此外,IC本体的上表面,成为用于将功率IC元件产生的热排出到IC本体外部的散热部32a。
通过将球形凸点32接触到布线图形5,在布线图形5上安装功率IC31。安装功率IC31后,在布线图形5和IC本体32之间填充密封材料34。作为密封材料34的材质,例如可以例示环氧树脂等。而且,在功率IC的散热部32a上涂敷导热性粘合剂35。作为导热性粘合剂35的材质,例如可以例示掺入(铝、氮化铝)填料的环氧粘合剂。
[叠层工序]
接着,如图2A所示,首先准备设有贯通孔7的树脂层6和散热板8。此外,准备另一个版基板11。在该版基板11中,在其整个面上形成种子层2,同时在种子层2上形成布线图形15。
平面观察树脂层6的贯通孔7时的形状,可以是圆形、椭圆形、三角形或包含矩形的多边形的其中之一的形状。关于贯通孔7的大小,收容功率IC31左右的大小就可以。就形成贯通孔7来说,例如可以采用金属模的冲压(punching)和所谓激光加工法的手段。再有,作为树脂层6的具体例,可以例示将环氧树脂和聚酯树脂等的热可塑性树脂作为材质的厚度50μm左右的板材、厚度50μm左右的玻璃环氧树脂板。
而散热板8例如可以采用Cu、Al等的导热性良好的金属板。散热板8的厚度例如0.02-0.2mm左右的范围较好。此外,如图2A所示,在散热板8中设置用于通孔的贯通孔8a较好。
然后,在版基板1上依次配置树脂层6和散热板8,进而在散热板8上配置另一个版基板11。在配置树脂层6时,使树脂层6的版基板1位置重合,以使树脂层6的贯通孔7和版基板1上的功率IC31重叠。此外,在配置散热板8时,使散热板8和版基板1位置重合,以使散热板8的贯通孔8a、未连接到版基板1上的功率IC31的布线图形5a重叠。而且,在配置另一个版基板11时,进行位置重合,以使该另一个基板11上形成的布线图形15和散热板8的贯通孔8a重叠。
接着,如图2B所示,将版基板1、树脂层6、散热板8和另一版基板11叠层而进行热压(heat press)。在这种热压时,树脂层6因布线图形5而产生变形,从而布线图形5被埋入在树脂层的一面6a上。同时,功率IC31被插入到贯通孔7的内部。树脂层6通过从其厚度方向被压而变形为薄板状,随着这种变形,如图2B所示,在贯通孔7和功率IC31之间树脂层6的一部分被压出、填充。这样,功率IC31被完全埋入在树脂层6的内部。此外,随着功率IC31对贯通孔7的插入,功率IC31的散热部32a成为在树脂层6的另一面6b露出的状态。
此外,散热板8和树脂层6通过这种热压而被接合。此时,在树脂层6的另一面6b侧露出的功率IC的散热部32a通过导热性粘合剂35而被接合在散热板8上。
而且,通过这种热压,另一个版基板11上形成的布线图形15被插入在散热板8的贯通孔8a内部。而且在该贯通孔8a中,随着树脂层6的变形,树脂层的一部分被压出、填充。通过该填充的树脂层,散热板8和布线图形15成为绝缘状态。
热压时的温度基于树脂层6的材质而定,但140~180℃的范围较好。而热压的压力为15~25Pa左右较好。而且,模压时间为35~50分钟左右较好。由此,布线图形5和功率IC31被埋入在树脂层6中。
[除去工序]
接着,如图2所示,在各版基板1、11和树脂层6及散热板8之间施加应力并使版基板1、11剥离。此时,在各版基板1、11和各种子层2之间引起剥离,种子层2和布线图形5一起被转印在树脂层6和散热板8侧。转印的各种子层2通过湿法蚀刻被除去。就蚀刻液而言,例如可以使用过硫酸水溶液。再有,对于剥离后的版基板1、11,通过用酸或碱来除去未被转印而保留的种子层2,从而可以再次利用。
在版基板1和种子层2之间引起的剥离被认为是以下的机理。
即,在使版基板1从树脂层6剥离时,在种子层2中其膜厚方向上被施加拉伸应力。此时,布线图形5被接合至构成种子层2的金属铜层,该布线图形5被埋入树脂层6并与该树脂层6牢固地接合,所以向树脂层6侧的拉伸应力占优,由此,种子层2和布线图形5一起被转印到树脂层6侧。此外,就构成种子层2的金属铜层2b来说,在剥离时在布线图形5上施加拉伸剪切应力,但在金属铜层2b中氧化锌层2a作为衬底层而形成衬底,所以金属铜层2b自身不损坏,与氧化锌层2a一起从版基板1完全地剥离。此外,氧化锌层2a本身也以50nm至500nm的膜厚形成,所以氧化锌层2a的膜强度提高,氧化锌层2a本身也不会担心被损坏,从版基板1完全地剥离。
在另一个版基板11和被填充在散热板8的贯通孔8a中的树脂层6之间,也引起与上述同样的现象,在版基板11和种子层2之间引起剥离。
再有,在上述种子层2的蚀刻时,布线图形5、15也被稍稍蚀刻,但布线图形5、15的线宽度不减少。其理由在于,布线图形5、15的大部分被埋入树脂层6,布线图形5、15的露出部分少,布线图形5、15通过树脂层6受到保护。这样,由于布线图形5、15被树脂层6保护,所以可以防止蚀刻液造成的布线图形5、15的腐蚀,可以防止布线图形5、15的线宽度的减小。由此,可以实现用现有的转印法不可能达到的10μm/10μm的线间距(line and space)(L/S)。
这样,通过上述制造方法来制造电路部件模块100。
根据上述制造方法,将布线图形5、15埋入在树脂层6中,并且在贯通孔7内部插入功率IC31,从而可以将电路部件模块100自身形成为薄形。此外,通过使功率IC31接合在散热板8上,可以提高功率IC31和散热板8之间的导热性。
[电路部件模块的一例]
图2C所示的电路部件模块100大致包括:散热板8;叠层在散热板8的一面8b上的树脂层6;埋入在树脂层6中,并且一部分连接到散热板8的功率IC(电子部件)31;埋入在树脂层6的与散热板相反侧的面6a中并与功率IC31一起构成电路的布线图形5。此外,在散热板8中设有贯通孔8a,在该贯通孔8a内配置另一布线图形15。此外,在贯通孔8a和布线图形15之间,填充一部分树脂层6。此外,该散热板8连接到省略图示的另一散热部件,或散热板8自身露出至电路部件模块100的外部环境中。
功率IC31由具有散热部32a的IC本体(部件本体部)32和安装在IC本体32上的球形凸点(端子部)33构成。此外,在IC本体32中内置未图示的功率IC元件。而且,散热部32a被露出到树脂层6的散热板侧的面6b上,同时端子部33配置在与散热板8的相反侧并连接到布线图形5的一部分。此外,散热部32a通过导热性粘合剂35而接合至散热板8。
通过上述结构,随着功率IC元件的驱动而产生的热在IC本体32的内部进行导热而传递至散热部32a。而且,这种热从散热部32a通过导热性粘合剂35被传导到散热板8。传导到散热板8的热还被传导到省略图示的另一个散热部件,或通过散热板8散热到外部环境中。
根据上述电路部件模块100,由于功率IC31连接到散热板8,所以可以将随着功率IC31的驱动而产生的热通过该散热板8而排热到电路部件模块100的外部。此外,由于功率IC31和布线图形5、15被埋入在树脂层6中,所以可以保护布线图形5、15,并且可以实现电路部件模块100本身的薄形化。同时,可以提高功率IC31和布线图形5的连接可靠性。
[配有通孔的电路部件模块的制造方法]
下面,说明对图2C所示的电路部件模块100进一步加工的、配有通孔的电路部件模块的制造方法。
首先,如图3A所示,在电路部件模块100中设置用于通孔的贯通孔101、101。设置该贯通孔101、101,以使其贯通树脂层6,并且贯通配置在散热板8的贯通孔8a内部的布线图形15和不与功率IC31连接的布线图形5a。
接着,如图3B所示,在贯通孔101、101的内部填充导电膏102,而且形成用于堵住贯通孔101的盖板103。就盖板103来说,例如可使用Cu板。这样,形成导电膏102和盖板103构成的通孔104。通过该通孔104,散热板侧的布线图形15和树脂层侧的布线图形5被连接。
[配有多个电路部件模块的电路部件模块(电子电路装置)的制造方法]
接着,如图3C所示,准备两个形成了通孔104的电路部件模块100、100。这里,配置各电路部件模块100、100以使各树脂层6、6相互对置。而且,在各电路部件模块100、100之间配置厚度20μm-50μm左右的另一个树脂层106。在该另一个树脂层106中,在与电路部件模块100的通孔104对应的位置填充导电膏107。就树脂层106的材质来说,可以例示环氧树脂和聚酯树脂等热可塑性树脂。
接着,如图3D所示,将电路部件模块100、100和树脂层106进行叠层并进行热压(heat press)。通过该热压,电路部件模块100、100的各树脂层6、6被接合至另一个树脂层106的两面106a、106b。另外,此时,构成电路部件模块100的通孔104的盖板103和另一个树脂层106的导电膏107接合。由此,通过各通孔104、104和导电膏107,形成将各电路部件模块100、100的布线图形5、15相互连接的通孔108。由此制造图3D所示的电路部件模块200。
根据上述制造方法,通过配置成将各电路部件模块100、100的树脂层6、6相互对置,从而散热板8被配置在电路部件模块200的外侧,由此可以将散热板8作为电路部件模块200的外封装板。此外,通过在各电路部件模块100、100之间隔着另一个树脂层106,可以将电路部件模块100、100间容易地接合。
[配有两个电路部件模块的电路部件模块(电子电路装置)]
图3D所示的电路部件模块200配有两个图2C中的电路部件模块100、100,各电路部件模块100、100的树脂层6、6间被相互对置地配置,并且在各树脂层6、6之间隔着另一个树脂层106,它们被接合为一体。通过使树脂层6、6间对置配置,各散热板8、8被配置在电路部件模块200的外侧,由此可以将各散热板8、8作为电路部件模块200的外封装板。
另外,在各树脂层6、6、106中设有被填充了导电膏102、107的通孔108,这些通孔108连接到布线图形5、15。由此,可以将各电路部件模块100、100的各功率IC31、31和各布线图形5、15相互地连接。
图3D所示的电路部件模块200可以用作配有两个功率IC31、31的电子电路装置。在该电子装置中,配有兼用作外封装板的散热板8、8,可通过该散热板8、8来屏蔽外部电波对布线图形5、15传送的信号的影响、该信号本身的辐射电磁场造成的影响。此外,构成电路部件模块100的散热板8和树脂层6及功率IC31的相互尺寸精度提高,所以特别是在其用作高频模块的情况下,可以发挥如设计性能那样的模块性能。
[第2实施方式]
下面说明本发明第2实施方式的电路部件模块及其制造方法。图4表示叠层工序和除去工序的工序图。再有,在本实施方式中参照的附图是用于说明电路部件模块及其制造方法的图,图示的各部的大小、厚度和尺寸不必与实际的电路部件模块的尺寸关系一致。
[电路部件模块的制造方法]
首先,如图4A所示,准备两个版基板1、1、两个树脂层6、6,和散热板8。
版基板1是与第1实施方式中说明的同一结构的基板,形成种子层2和布线图形5,而且,被安装了功率IC31。此外,树脂层6由厚度100μm-500μm左右的热可塑性树脂或玻璃环氧树脂板构成,设有贯通孔7。此外,散热板8由Al等导热性良好的厚度100μm左右的金属板构成,设有多个贯通孔8a。
然后,如图4A所示,在散热板8的两面8b、8c侧配置树脂层6、6,并且在各树脂层6、6的外侧、即散热板8的相反侧配置版基板1、1。版基板1进行定位,以使功率IC31重合在树脂层6的贯通孔7上。此外,版基板1进行定位,以使不连接到功率IC31的布线图形5的形成位置与散热板的贯通孔8a重合。
接着,如图4B所示,将各版基板1、1、各树脂层6、6和散热板8进行叠层并进行热压。在这种热压时,树脂层6因布线图形5而产生变形,从而布线图形5被埋入在树脂层6的一面6a上。同时,功率IC31被插入到贯通孔7的内部。树脂层6通过从其厚度方向进行模压而变形为薄板状,随着这种变形,如图4B所示,在贯通孔7和功率IC31之间树脂层6的一部分被压出并填充。这样,功率IC31被完全埋入在树脂层6的内部。此外,随着功率IC31向贯通孔7的插入,功率IC的散热部32a成为露出树脂层的另一面6b侧的状态。
此外,散热板8和各树脂层6、6通过这种热压而被接合。此时,在散热板8的贯通孔8a中树脂层6的一部分被压出并填充。而且,树脂层6的另一面6b侧露出的功率IC的散热部32a通过导热性粘合剂35而接合于散热板8。
接着,如图4C所示,在各版基板1、1和树脂层6、6之间施加应力并使版基板1、1剥离。此时,在各版基板1和各种子层2之间引起剥离,种子层2和布线图形5一起被转印至树脂层6侧。转印后的各种子层2通过湿法蚀刻被除去。
这样,制造了作为本实施方式的一个例子的电路部件模块300。
[电路部件模块的一例]
图4C所示的电路部件模块300包括:散热板8;散热板8的两面8b、8c上分别叠层的一对树脂层6、6;各树脂层6中分别埋入并且其一部分分别连接到散热板8的功率IC31;以及被分别埋入在各树脂层6、6的与散热板的相反侧的面6a上并与各功率IC31一起构成电路的布线图形5。此外,散热板8与第1实施方式同样,连接到省略图示的另一个散热部件,或散热板本身在电路部件模块的外部环境中露出。
根据上述电路部件模块300,功率IC31连接到散热板8,所以可将随着功率IC31的驱动而产生的热通过该散热板8而排热到电路部件模块300的外部。此外,由于功率IC31和布线图形5埋入在树脂层6中,所以可以保护布线图形5,并且可以实现电路部件模块300本身的薄形化。同时,可以提高功率IC31和布线图形5的连接可靠性。而且,使功率IC31接合于散热板的两面8b、8c,所以可以减少散热板8相对功率IC31的数目,可以简化结构。
[配有多个电路部件模块的电路部件模块(电子电路装置)的制造方法]
下面,说明对图4C所示的电路部件模块300进一步加工,从而制造配有多个电路部件模块的电路部件模块(电子电路装置)的方法。
首先,如图5A所示,在电路部件模块300中设置用于通孔的贯通孔301。设置该贯通孔301,以使其贯通树脂层6、6,并且贯通散热板8的贯通孔8a。而且,设置贯通孔301,以使其贯通不连接到功率IC31的布线图形5a。
接着,如图5B所示,在贯通孔301的内部填充导电膏302,而且形成用于堵住贯通孔301的盖板303。这样,形成导电膏302和盖板303构成的通孔304。通过该通孔304,位于散热板两侧的布线图形5a、5a间被连接。
接着,如图5C所示,准备两个具有图5B所示的通孔304的电路部件模块300a、300b。此时,在一个电路部件模块300a中,预先叠层另一个树脂层306。在该另一个树脂层306中设置被填充了导电膏307的贯通孔308,将该导电膏307进行定位,以使其与通孔304重合。然后,将另一个电路部件模块300b的通孔304进行定位,以使其与该导电膏307重合。
接着,如图5D所示,将电路部件模块300a、300b进行叠层并进行热压。通过这种热压,电路部件模块300a、300b间通过树脂层306而被接合。此时,构成各电路部件模块300a、300b的通孔304的盖板303和另一个树脂层306的导电膏307相互接合。由此,通过各通孔304和导电膏307,形成将各电路部件模块300a、300b的布线图形5a、5a相互连接的通孔310。这样,制造了本实施方式的另一个例子的电路部件模块400。
[配有两个电路部件模块的电路部件模块(电子电路装置)]
图5D所示的该电路部件模块400配有两个图4C中的电路部件模块300、300,各电路部件模块300、300之间夹着另一个树脂层306,它们被接合为一体。通过在树脂层306中设置被填充了导电膏307的贯通孔308,各导电膏307连接到各通孔304、304。由此,可以将电路部件模块300的各功率IC31和各布线图形5相互连接。
图5D所示的电路部件模块400可以用作配有四个功率IC31的电子电路装置。在该电子装置中,对四个功率IC31配有两块散热板8、8,通过减少散热板8相对于功率IC31的数目,可以简化结构。此外,构成电路部件模块400的散热板8和树脂层6、306及功率IC31的相互尺寸精度提高,所以特别是在其用作高频模块的情况下,可以发挥如设计性能那样的模块性能。
[第3实施方式]
图6表示第3实施方式的电子电路装置500的剖面示意图。图6所示的电子电路装置500如下构成:配有两个第1实施方式的电路部件模块100、100,各电路部件模块100的树脂层6、6间被相互对置地配置,而且在各树脂层6、6之间夹着另一个树脂层106,它们被接合为一体。此外,各电路部件模块100、100中,配有厚度20μm-500μm左右的兼用作外封装板的散热板508、508。在该散热板508上通过导热性粘合剂35分别接合功率IC31的散热部32a。
根据上述电子电路装置500,具备兼作外封装板的散热板50g,可以通过该散热板508来屏蔽外部电波对布线图形5传送的信号的影响、该信号本身的辐射电磁场造成的影响。此外,散热板508和树脂层6、106及功率IC31的相互尺寸精度提高,所以特别是在将该电子电路装置500用作高频模块的情况下,可以发挥如设计性能那样的模块性能。
[第4实施方式]
图7表示第4实施方式的电子电路装置及其制造方法。如图7A所示,该电子电路装置600在第2实施方式的电路部件模块300的厚度方向两侧,在介质层602面向电路部件模块300的状态下配置带有介质层的外封装板601。带有介质层的外封装板601由介质层602和外封装板603叠层构成。接着,如图7B所示,将带有介质层的外封装板601和电路部件模块300相互叠层后,通过热压来制造。通过热压,构成电路部件模块300的树脂层6、6和介质层602接合并一体化。就介质层602而言,使用环氧树脂、聚酯树脂等构成的厚度20μm-250μm左右的介质。通过介质层602的厚度,电路部件模块300和外封装板603的间隔受到控制。此外,就外封装板603来说,使用Al等的厚度200μm左右的金属板,这种外封装板603被用作电子电路装置600的接地端子。
根据上述电子电路装置600,通过在外封装板603和树脂层6之间配置的介质层602的厚度,可以调整兼用作接地端子的外封装板603和树脂层6内部的功率IC31及布线图形5的间隔,特别是在将电子电路装置600用作高频模块的情况下,可以发挥如设计性能那样的模块性能。
再有,本发明的技术范围不限定于上述实施方式,在不脱离本发明的意图的范围内可实施各种变更。例如,在上述各实施方式,作为布线图形,使用单层Cu构成的布线图形,但如图8A所示,也可以使用多个金属层构成的叠层结构的布线图形115。该布线图形115包括:形成于种子层2上的Au层121;叠层于Au层121上的Cu层122;叠层于Cu层122上的Ni层123;以及形成于Ni层123上的Au层124。这样,本实施方式的布线图形115在Cu层122和Ni层123的厚度方向两侧形成Au层121、124。Au层121的膜厚在0.01μm-0.1μm的范围较好,Cu层122的膜厚在5μm-10μm的范围较好,Ni层123的膜厚在2μm-4μm的范围较好,Au层124的膜厚在0.1μm-0.5μm的范围较好。更具体地说,Au层121为0.03μm、Cu层122为10μm、Ni层123为2μm、Au层124为0.2μm即可。各层都可用镀敷法形成。
再有,布线图形的叠层结构不限于图8A所示的方式,例如,如图8B所示,也可以使用由Au层126、Ni层127、Cu层128、Ni层129和Au层130构成的五层结构的布线图形125。
在这些叠层结构的布线图形中,由于包含强度比较高的Ni层,所以在叠层工序中将电子部件埋入树脂层时,即使是布线图形上施加了应力的情况,也可以防止布线图形的变形。此外,由于布线图形的表面为Au层,所以可以降低电子部件和布线图形之间的接触电阻,可以提高布线图形和电子部件的连接可靠性。
Claims (13)
1.一种电路部件模块,其特征在于,包括:散热板;叠层在所述散热板的一个面上的树脂层;埋入在所述树脂层中并且一部分连接到所述散热板的电子部件;以及埋入在所述树脂层的与所述散热板相反侧的面中并与所述电子部件一起构成电路的布线图形。
2.一种电路部件模块,其特征在于,包括两个权利要求1所述的电路部件模块,各电路部件模块的树脂层相互对置配置,并且在各树脂层之间夹着另一树脂层,这些树脂层被一体地接合。
3.一种电路部件模块,其特征在于,包括两个权利要求1所述的电路部件模块,各电路部件模块的散热板侧相互对置配置,各电路部件模块共用散热板。
4.如权利要求1所述的电路部件模块,其特征在于,所述电子部件由具有散热部的部件本体部、和安装在该部件本体部上的端子部构成,所述散热部在所述树脂层的散热板侧的面中露出,并且所述端子部被配置在与散热板相反侧并连接到所述布线图形的一部分。
5.如权利要求4所述的电路部件模块,其特征在于,在所述电子部件的散热部和所述散热板之间,配置导热性粘合剂。
6.如权利要求1所述的电路部件模块,其特征在于,在所述树脂层中设置被填充了导电膏的通孔,填充了导电膏而成的各通孔连接到所述布线图形。
7.如权利要求6所述的电路部件模块,其特征在于,在所述散热板中,设置用于使填充了所述导电膏而成的通孔贯通的贯通孔。
8.如权利要求1所述的电路部件模块,其特征在于,所述电子部件是功率IC。
9.一种电子电路装置,其特征在于,包括权利要求2所述的电路部件模块,所述各散热板是兼用作接地端子的外封装盖。
10.一种电子电路装置,其特征在于,包括权利要求3所述的电路部件模块,构成该电路部件模块的所述树脂层的外侧上分别形成介质层,并且在各介质层的外侧包括兼用作接地端子的外封装盖。
11.一种电路部件模块的制造方法,其特征在于,包括:
安装工序,在版基板的整个面上形成种子层,并且通过镀敷在该种子层上形成由多个布线部构成的布线图形,并在所述布线部上安装电子部件;
叠层工序,通过在版基板的所述布线图形上,依次叠层具有贯通孔的树脂层和散热板并将它们热压接,将所述布线部埋入所述树脂层并且将所述电子部件插入所述贯通孔内而使该电子部件接合至所述散热板;以及
除去工序,除去所述版基板和所述种子层。
12.一种电路部件模块的制造方法,其特征在于,准备两个用权利要求11所述的制造方法制造的电路部件模块,各电路部件模块的树脂层相互对置地配置,并且在各树脂层之间夹着另一树脂层,将这些树脂层热压接。
13.如权利要求11所述的电路部件模块的制造方法,其特征在于,在所述叠层工序中,在叠层了所述散热板之后,叠层形成了具有贯通孔的树脂层以及布线图形的另一基板,并将它们热压接。
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DE102008000842A1 (de) * | 2008-03-27 | 2009-10-01 | Robert Bosch Gmbh | Verfahren zur Herstellung einer elektronischen Baugruppe |
JP5367616B2 (ja) * | 2009-02-23 | 2013-12-11 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5340789B2 (ja) * | 2009-04-06 | 2013-11-13 | 新光電気工業株式会社 | 電子装置及びその製造方法 |
JP5330065B2 (ja) * | 2009-04-13 | 2013-10-30 | 新光電気工業株式会社 | 電子装置及びその製造方法 |
US9355962B2 (en) * | 2009-06-12 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with redistribution and method of manufacture thereof |
JP2011049367A (ja) * | 2009-08-27 | 2011-03-10 | Panasonic Corp | 基板接続構造および電子機器 |
US8304286B2 (en) * | 2009-12-11 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit packaging system with shielded package and method of manufacture thereof |
JP5601447B2 (ja) * | 2010-01-14 | 2014-10-08 | 東芝ディーエムエス株式会社 | 半導体チップを内蔵するプリント配線板 |
KR101212061B1 (ko) * | 2010-06-09 | 2012-12-13 | 에스케이하이닉스 주식회사 | 반도체 칩 및 그 반도체 패키지와 이를 이용한 스택 패키지 |
JP5533350B2 (ja) * | 2010-06-30 | 2014-06-25 | 株式会社デンソー | 半導体装置及びその製造方法 |
JP5589743B2 (ja) * | 2010-10-13 | 2014-09-17 | トヨタ自動車株式会社 | 配線基板 |
WO2013027795A1 (ja) * | 2011-08-23 | 2013-02-28 | 株式会社フジクラ | 部品内蔵基板およびその製造方法 |
AT13432U1 (de) * | 2011-08-31 | 2013-12-15 | Austria Tech & System Tech | Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt |
AT13436U1 (de) * | 2011-08-31 | 2013-12-15 | Austria Tech & System Tech | Verfahren zur integration eines bauteils in eine leiterplatte oder ein leiterplatten-zwischenprodukt sowie leiterplatte oder leiterplatten-zwischenprodukt |
JP5167516B1 (ja) * | 2011-11-30 | 2013-03-21 | 株式会社フジクラ | 部品内蔵基板及びその製造方法並びに部品内蔵基板実装体 |
JP2013225622A (ja) * | 2012-04-23 | 2013-10-31 | Jtekt Corp | モーター制御用多層回路基板 |
KR101905893B1 (ko) * | 2012-06-13 | 2018-10-08 | 에스케이하이닉스 주식회사 | 복수의 유전층을 포함하는 임베디드 패키지 및 제조 방법 |
US9252734B2 (en) * | 2012-09-14 | 2016-02-02 | National Instruments Corporation | High frequency high isolation multichip module hybrid package |
KR102107038B1 (ko) * | 2012-12-11 | 2020-05-07 | 삼성전기주식회사 | 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법 |
AT514085B1 (de) | 2013-06-11 | 2014-10-15 | Austria Tech & System Tech | Leistungsmodul |
JP2015028986A (ja) * | 2013-07-30 | 2015-02-12 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
CN105934823A (zh) | 2013-11-27 | 2016-09-07 | At&S奥地利科技与系统技术股份公司 | 印刷电路板结构 |
AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
US9184128B2 (en) * | 2013-12-13 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC package and methods of forming the same |
AT515447B1 (de) * | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
US10257937B2 (en) * | 2014-07-07 | 2019-04-09 | Infineon Technologies Austria Ag | Device for electrically coupling a plurality of semiconductor device layers by a common conductive layer |
DE102014118462A1 (de) * | 2014-12-11 | 2016-06-16 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Semiflexible Leiterplatte mit eingebetteter Komponente |
JP6318084B2 (ja) * | 2014-12-17 | 2018-04-25 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US9837484B2 (en) * | 2015-05-27 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming substrate including embedded component with symmetrical structure |
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KR20220081020A (ko) * | 2020-12-08 | 2022-06-15 | 삼성전기주식회사 | 인쇄회로기판 |
US11581233B2 (en) | 2021-05-04 | 2023-02-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical circuit pattern within encapsulant of SIP module |
WO2024080270A1 (ja) * | 2022-10-14 | 2024-04-18 | 株式会社村田製作所 | 電子機器 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP2000269411A (ja) | 1999-03-17 | 2000-09-29 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
KR100324333B1 (ko) * | 2000-01-04 | 2002-02-16 | 박종섭 | 적층형 패키지 및 그 제조 방법 |
JP2001358465A (ja) | 2000-06-16 | 2001-12-26 | Hitachi Chem Co Ltd | 多層プリント配線板およびその製造方法 |
JP3546961B2 (ja) | 2000-10-18 | 2004-07-28 | 日本電気株式会社 | 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ |
US6861757B2 (en) | 2001-09-03 | 2005-03-01 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
JP4040389B2 (ja) | 2001-09-27 | 2008-01-30 | 大日本印刷株式会社 | 半導体装置の製造方法 |
JP3524545B2 (ja) | 2002-01-23 | 2004-05-10 | 松下電器産業株式会社 | 回路部品内蔵モジュールの製造方法 |
TW200302685A (en) | 2002-01-23 | 2003-08-01 | Matsushita Electric Ind Co Ltd | Circuit component built-in module and method of manufacturing the same |
US7365273B2 (en) * | 2004-12-03 | 2008-04-29 | Delphi Technologies, Inc. | Thermal management of surface-mount circuit devices |
-
2004
- 2004-12-06 JP JP2004352814A patent/JP2006165175A/ja not_active Ceased
-
2005
- 2005-11-29 US US11/290,314 patent/US7514636B2/en not_active Expired - Fee Related
- 2005-12-06 CN CNA2005101295580A patent/CN1791305A/zh active Pending
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US20060120056A1 (en) | 2006-06-08 |
US7514636B2 (en) | 2009-04-07 |
JP2006165175A (ja) | 2006-06-22 |
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