CN1759480A - 用于倒装片的由被覆线形成的涂覆金属柱形突起 - Google Patents
用于倒装片的由被覆线形成的涂覆金属柱形突起 Download PDFInfo
- Publication number
- CN1759480A CN1759480A CNA2004800067345A CN200480006734A CN1759480A CN 1759480 A CN1759480 A CN 1759480A CN A2004800067345 A CNA2004800067345 A CN A2004800067345A CN 200480006734 A CN200480006734 A CN 200480006734A CN 1759480 A CN1759480 A CN 1759480A
- Authority
- CN
- China
- Prior art keywords
- conductive
- semiconductor chip
- conductive region
- stud bump
- scolder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title description 3
- 239000002184 metal Substances 0.000 title description 3
- 230000009977 dual effect Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims description 32
- 229910052802 copper Inorganic materials 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 230000003064 anti-oxidating effect Effects 0.000 claims description 9
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910000510 noble metal Inorganic materials 0.000 claims description 4
- 229910052745 lead Inorganic materials 0.000 claims description 3
- 210000003516 pericardium Anatomy 0.000 claims 1
- 239000010410 layer Substances 0.000 description 34
- 230000008021 deposition Effects 0.000 description 13
- 229910000765 intermetallic Inorganic materials 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 239000002131 composite material Substances 0.000 description 6
- 229910017835 Sb—Sn Inorganic materials 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/38—Applying electric currents by contact electrodes alternating or intermittent currents for producing shock effects
- A61N1/39—Heart defibrillators
- A61N1/3956—Implantable devices for applying electric shocks to the heart, e.g. for cardioversion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/38—Applying electric currents by contact electrodes alternating or intermittent currents for producing shock effects
- A61N1/39—Heart defibrillators
- A61N1/395—Heart defibrillators for treating atrial fibrillation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Cardiology (AREA)
- Biomedical Technology (AREA)
- Heart & Thoracic Surgery (AREA)
- Manufacturing & Machinery (AREA)
- Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
- Radiology & Medical Imaging (AREA)
- Life Sciences & Earth Sciences (AREA)
- Animal Behavior & Ethology (AREA)
- General Health & Medical Sciences (AREA)
- Public Health (AREA)
- Veterinary Medicine (AREA)
- Wire Bonding (AREA)
Abstract
揭示了一种用于形成柱形突起的半导体小片的方法。该方法包括在穿过毛细管(22)中的孔的被覆线(21)的末端形成一个球(18和19),其中被覆线包括线心(19)和抗氧化涂层(18)。形成的球被压到半导体小片(1)上的导电区域(2)上。被覆线被切断(图7),从而在导电区域上留下导电柱形突起,其中导电柱形突起包括内部导电部分(19)和外部抗氧化层(18)。
Description
本发明的背景
在电子组件中有许多不同等级的组件和互连。在典型的第一级封装工艺中,一个硅小片被连接到一个陶瓷衬底托架上。在典型的第二级封装工艺中,具有小片的陶瓷衬底托架被固定在有机板上。
在常规的形成第一级组件的方法中,在半导体小片(可能位于一个半导体晶片中)上形成一个钝化层。钝化层包括将半导体小片上的导电区域暴露出来的开口。钛和铜层被溅射到导电区域和钝化层的上表面。然后将一层光刻胶涂在半导体小片上被加上图样,使得加上图样的涂光刻胶层中的开口在导电区域的上面。焊料被电镀到光刻胶层中的开口里,直到开口被焊料填满。然后光刻胶被剥离,而焊料沉积物周围钛和铜层的部分被去除。然后,焊料沉积物要经历一次全回流工艺。全回流工艺使得焊料沉积物形成焊球。形成焊球以后,半导体小片面朝下接合到托架上。半导体小片上的焊球接触小片托架上的导电区域。不可溶的隔离物设置在导电区域周围且限制焊球。位于托架上的导电区域和半导体小片之间的焊球熔化并浸渍托架上的导电区域。表面张力避免熔化的焊料完全塌陷并且保持半导体小片悬浮在托架上面。
在回流步骤中,沉积的焊料基本上变形为焊球。由于这一变形,故在半导体小片上所得的焊球的高度可能不均匀。如果焊球的高度不均匀,当半导体小片被固定在芯片托架上,焊球可能不全部同时与托架的导电区域相接触。如果这一情况发生,形成的焊料焊缝处的强度可能会较薄弱,从而潜在地减少形成的组件的可靠性。另外,在回流工艺中,沉积的焊料长期地暴露在高温下。过度加热沉积的焊料会促进焊料沉积物中金属间化合物的过度生长。焊料焊缝处的金属间化合物使得焊料焊缝处变脆并且降低焊料焊缝处的抗疲劳强度。最后,进行全回流工艺花费时间和能量,从而增加了最终生产的小片组件的成本。如果可能的话,希望能减少与全回流工艺相关联的时间和能量。
一种解决上述问题的方法是使用“柱形突起”技术以在导电区域上形成一个铜球,以替代焊料。铜球采用一种引线接合技术形成,其中引线的末端形成一个球,该球被压缩到半导体小片的一个导电区域。然后切断引线,留下铜柱形状的压缩球。半导体小片然后被翻转,并用Pb-Sb-Sn焊料固定到具有导电焊接区的电路板的托架上。
虽然所述的柱形突起方案是可行的,但还是有一些问题需要处理。首先,在上述方案中,在铜球和Pb-Sb-Sn焊料间会形成厚的金属间化合物。厚的金属间化合物层会增加小片组件的“接通电阻”。第二,在铜柱中的铜以及厚金属间化合物层中之间可能产生空隙。例如,如图1中所示,经过150℃下1000小时的测试后,在形成的金属间化合物层与铜柱之间显示出一个缝隙(或者空隙)。该缝隙导致在半导体小片和与其相连的托架间较差的电气和机械连接性。不受理论的束缚,发明者认为在铜/金属间化合物界面间的空隙的形成是由铜氧化和/或Cu、Sn和Sb的扩散速率的不同导致的。
本发明的实施例处理这些和其它一些问题。
本发明的概要
本发明的实施例针对柱形突起的半导体小片,用突起的半导体小片来形成的半导体小片组件,及其制造方法。
本发明的一个实施例针对一种方法,包括:(a)在穿过毛细管中的孔的被覆线的末端形成一个球,其中该被覆线包括线心和外部抗氧化涂层;(b)将该球压到半导体小片上的导电区域上;(c)切断被覆线,从而在导电区域上留下一导电柱形突起,其中该导电柱形突起包括内部导电部分和外部抗氧化层。
本发明的另一个实施例针对一种突起的半导体小片,包括:(a)包括导电区域的半导体小片;(b)导电区域上的导电柱形突起,其中导电柱形突起包括内部导电部分和外部抗氧化层。
本发明的另一个实施例针对一种半导体小片组件,包括:(a)突起的半导体小片包括:(i)包括第一导电区域的半导体小片(ii)导电区域上的导电柱形突起,其中导电柱形突起包括内部导电部分和外部抗氧化层;以及(b)包括第二导电区域的电路衬底,第二导电区域上的焊料,其中突起的半导体小片被固定在电路衬底上,而导电柱形突起与第二导电区域上的焊料相接触。
本发明的这些和其它实施例将在下文中更详细的被描述。
附图的简单描述
图1(a)示出铜柱、焊料膏、和处于铜柱与焊料膏之间的金属间化合物层的横截面图。
图1(b)示出形成于金属间化合物层和铜柱之间的缝隙。
图2示出其上有导电柱形突起的半导体小片的横截面图。
图3示出被固定在电路衬底上的带有导电柱形突起的半导体小片的横截面图。
图4-7示出在形成导电突起的过程中,被覆线、毛细管和半导体小片的横截面图。
图8是一张图表,示出使用包括铜线心和包括钯的外部涂层的被覆线接合到半导体小片的导电区域的球的剪切/拉伸试验强度与时间关系。
为了便于说明,图中各种元件的尺寸可能未按照比例。此外,在图中,相同的标号表示相同的元件。
详细的描述
图2示出依据本发明的一个实施例的柱形突起的半导体小片100。柱形突起的半导体小片100包括第一导电区域2在内半导体小片1,以及第一导电区域2上的导电柱形突起27。
半导体小片100可包含任何适当的材料(例如,硅、砷化镓)并且可包括任何适当的有源或者无源的半导体器件。例如,半导体小片可包含金属氧化物场效应晶体管(MOSFET),比如功率MOSFET。MOSFET可有一平面或者沟道的栅。最好是沟道栅。包含沟道栅的晶体管单元要比包含平面栅的窄。此外,MOSFET可以是纵向MOSFET。在纵向MOSFET中,源区和漏区位于半导体小片的相对的两側,从而晶体管中的电流垂直流过半导体小片。
每个导电区域2可以是,举例来说,导电焊接区。每个导电区域也可包含一层或多层材料。例如,根据本发明的一个实施例,导电区域可包含一层铝,带有一层或多层包括Ti、Ni、Cr等在内小突起的冶金层。
每个导电柱形突起27包括内部导电部分9和外部抗氧化层8。每个导电柱形突起27也包括突出部27(a)和底座27(b)。如图所示,突出部27(a)比底座27(b)要窄。如果半导体小片1包含功率MOSFET,比如纵向功率MOSFET,则导电柱形突起27可以与该MOSFET的源区和栅区相连接。
内部导电部分9最好包含铜(例如,纯铜或者铜合金)。外部抗氧化层8包含抗氧化的材料。合适的材料包括贵金属(或者其合金),比如Pd、Pt、Au、Ag、等等。尽管图示的实施例示出一带有两个不同的区域(也就是内部导电部分9和抗氧化层8)的导电柱形突起27,但应该理解根据本发明的实施例的导电柱形突起可以有任何适当数量的不同的区域。
抗氧化层8可以为任何适当的厚度。例如,在一些实施例中,其厚度大约为0.01微米到0.5微米。抗氧化层8可以至少涂在内部导电部分9的侧面、顶部、和底座中的至少一处,也可能是导电柱形突起的27的最外层。
图3示出柱形突起的半导体小片100如何被固定在电路衬底200上。电路衬底200可包括一些位于基础衬底15上的第二导电区域30。基础衬底15可包括一层或多层电介质层(例如,陶瓷或者聚合电介质层),也可包括位于相邻电介质层间的导电层。电路衬底200可以是半导体小片托架、电路板、或者任何其它用于支持半导体小片电子设备。例如,电路衬底200或者可以是一个带有引线的引线框。将突起的半导体小片100固定到引线框上之后,引线框的内部部分和突起的半导体小片100可以封装在成型的化合物中。
如图所示,第二导电区域30上可有焊料沉积物28。举例来说,每个焊料沉积28包含含有像Pb、Sn、也可以是Sb这样材料的焊料。在其它实施例中,焊料可是无铅焊料,例如包含Sn、Ag和Sb的焊料。在柱形突起的半导体小片100被翻转过来并且被固定在电路衬底200上之前,焊料沉积物28可处于第二导电区域30上。焊料沉积物28可以使用适当的工艺来沉积,其中包括网屏(screening)工艺、夹入(pick and place)工艺、或者电镀工艺、或者焊料分配工艺。
如图3中所示,柱形突起的半导体小片100可以被翻转,然后导电柱形突起27的突出部27(a)可以穿入焊料沉积物28并且此后电气地与第一导电区域2和第二导电区域30相连接。固定后会进行焊料回流工艺。回流工艺在本领域内为人所熟知,不需要在此详细描述。这样就提供了半导体小片1和电路衬底200间的电气连接。
导电柱形突起27的抗氧化层8保护内部导电部分9不被氧化。这降低了在导电柱形突起27的内部导电部分9和焊料沉积物之间形成空隙的可能性。如上所解释的,空隙的形成被认为是由铜的氧化和/或例如Cu、Sn和Sb(例如,用于与Pb-Sb-Sn焊料接触的纯铜柱)的原子的扩散速率的不同所致。
本发明的一些实施例针对形成上述柱形突起半导体小片100的方法。合适的方法包括在穿过毛细管中的孔的被覆线末端形成一个球。被覆线包含线心和外部抗氧化涂层。然后使用超声能量和/或热量将球接合到导电区域上,使球被压到半导体小片的导电区域上。然后,切断被覆线,从而在导电区域上留下一导电柱形突起。然后可以任选地整平导电柱形突起以使其高度与其它导电柱形突起一致。
如上所述,所得到的导电柱形突起包括内部导电部分和外部抗氧化层。然后,如上所述,突起的半导体小片被固定在电路衬底上。电路衬底包括导电区域和导电区域上的焊料,其中导电区域上的焊料与导电柱形突起接触。
用于在半导体小片上形成导电柱形突起的方法可以参照图4-7来描述。图4示出形成在被覆线21的前端的复合球32。被覆线21穿过毛细管22,而复合球32在毛细管的末端形成。通过采用例如气焰、电子脉冲、超声能量或类似的方法,热能量和/或声波能量被施加于被覆线21的末端。
被覆线21以及复合球32分别包含导电线心19和外部抗氧化涂层18。被覆线21的直径小于1mm。在一些实施例中,抗氧化层涂层18的厚度大约在0.01到0.5微米范围。导电线心19包含铜(或铜合金)而抗氧化涂层18包含贵金属,例如Pd(或者它的合金)。
毛细管22(具有超声能量和/或热量)可以被用于把球32压到半导体小片1的第一导电区域2上。通过使用热压缩接合工艺,和/或使用超声能量,复合球32被固定在第一导电区域2上。施加于复合物球32的压力可变,举例来讲,加到每个复合球32的压力可以是大约20到大约45克。可施加的超声能量可在60kHz范围内。
此后,毛细管22沿着路径25移动以形成图6中所示的一个环,当毛细管如图7中所示那样向下移动时,被覆线21被毛细管22的边沿切断。导电柱形突起形成时,向其提供惰性或还原气体,比如氮气或者N2H2,从而降低形成氧化物的可能。
接下来,通过对导电柱形突起的上表面施加压力(用一个平坦的表面)而使之被整平。通过对刚形成的导电柱形突起的顶部施加压力(例如,大约50g/突起),有可能使得突起的高度与其它突起一致。
市场上可购的进行上述工艺的装置包括有新加坡的ASM股份有限公司的产品(例如,ASM AB339)。同样可用购自Kulike&Soffa of Willow Grove,PA KNS1488L的涡轮常规线接合机。
在上述柱形突起工艺中使用被覆线有很多优点。首先,位于根据本发明的一个实施例形成的导电柱形突起中的铜被抗氧化层所保护,与仅包含铜在其中的柱形突起相比,该柱形突起的拉力强度更好。例如,图8中示出的图表表示通过使用包括铜线心与含钯的外部涂层的被覆线接合到导电区域上的球的球剪切/拉伸试验强度与时间的关系。如图表中所示,接合到半导体小片的导电区域的球的剪切强度与拉伸强度很高。第二,用于本发明的实施例中的被覆线的储藏寿命和工艺寿命时间很长。被覆线内的抗氧化涂层保护线的线心不被氧化,因此改善了其储藏寿命。第三,与用铜线形成的铜柱突起相比,由Cu/Pd形成的Cu/Pd柱形突起降低了在Cu/金属间化合物界面形成空隙的可能性。这改进了用被覆线形成的组件的总体可靠性。第四,导电柱形突起中的抗氧化层防止了内部导电部分的氧化,因而改进了导电柱形突起在使用期间的可靠性。第五,导电柱形突起中的抗氧化层作为一种金属间化合物的形成的阻挡金属,该金属间化合物是由于焊料材料的普遍使用而形成的。第六,本发明的实施例在突起和电路衬底间提供了一种坚固而可焊的界面。第七,由于在本发明的实施例中使用了基本实心的导电柱形突起,与只使用焊料作为连接材料的工艺相比,所用焊料较少。因此,不需要进行全回流工艺(如前所述),从而在本发明的实施例中减少了形成金属间化合物的可能性。
此处所用的术语和表述是用来作为描述性的,而非限制性的,并且在这些术语和表述的使用中,并没有要排除所示和所述的特征,或者其部分的等效物的意图,认为各种更改都可能在本发明范围内。此外,本发明的任何一个实施例的的任何一个或多个特征可以与本发明的任何其它实施例的任何一个或多个特征相结合而不背离本发明的范围。
Claims (13)
1.一种方法,其特征在于,所述方法包括:
(a)在穿过毛细管中的孔的被覆线的末端形成一个球,其中被覆线包含线心和外部抗氧化涂层;
(b)将该球压到半导体小片的导电区域上;并且
(c)切断被覆线,从而在导电区域上留下导电柱形突起,其中导电柱形突起包括内部导电部分和外部抗氧化层。
2.如权利要求1所述的方法,其特征在于,所述线心包含铜和所述涂层包含钯。
3.如权利要求1所述的方法,其特征在于,所述半导体小片包含纵向功率MOSFET。
4.如权利要求1所述的方法,其特征在于,所述抗氧化层包含贵金属。
5.如权利要求1所述的方法,其特征在于,所述半导体小片上的导电区域是第一导电区域,其中该方法还包含:
在步骤(c)以后,
(d)将半导体小片固定在电路衬底上,其中所述电路衬底包括第二导电区域和导电区域上的焊料,其中第二导电区域上的焊料与导电柱形突起接触。
6.如权利要求5所述的方法,其特征在于,所述焊料包括Pb、Sn或者无铅焊料。
7.一种突起的半导体小片,其特征在于,所述小片包括:
(a)包括导电区域的半导体小片;以及
(b)导电区域上的导电柱形突起,其中导电柱形突起包括内部导电部分和外部抗氧化层。
8.如权利要求7所述的突起的半导体小片,其特征在于,所述导电柱形突起包括底座和突出部,其中所述底座比所述突出部要宽。
9.如权利要求7所述的突起的半导体小片,其特征在于,所述半导体小片包括纵向功率MOSFET。
10.如权利要求7所述的突起的半导体小片,其特征在于,所述内部导电部分包括铜和所述外部抗氧化层包含贵金属。
11.一种半导体小片组件,其特征在于,所述组件包括:
(a)突起的半导体小片,包括(i)包括第一导电区域的半导体小片,以及(ii)位于导电区域上的导电柱形突起,其中所述导电柱形突起包括内部导电部分和外部抗氧化层;以及
(b)包括第二导电区域的电路衬底,和第二导电区域上的焊料,其中突起的半导体小片被固定在电路衬底上并且导电柱形突起与第二导电区域上的焊料接触。
12.如权利要求11所述的半导体小片组件,其特征在于,所述内部导电部分包含铜,所述外部抗氧化层包含钯。
13.如权利要求11所述的半导体小片组件,其特征在于,所述焊料包含Pb和Sn,或无铅焊料。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/386,211 | 2003-03-10 | ||
US10/386,211 US7271497B2 (en) | 2003-03-10 | 2003-03-10 | Dual metal stud bumping for flip chip applications |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1759480A true CN1759480A (zh) | 2006-04-12 |
CN100565857C CN100565857C (zh) | 2009-12-02 |
Family
ID=32961649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800067345A Expired - Lifetime CN100565857C (zh) | 2003-03-10 | 2004-03-10 | 用于倒装片的由被覆线形成的涂覆金属柱形突起 |
Country Status (6)
Country | Link |
---|---|
US (3) | US7271497B2 (zh) |
JP (1) | JP2006520103A (zh) |
CN (1) | CN100565857C (zh) |
DE (1) | DE112004000360T5 (zh) |
TW (1) | TWI353643B (zh) |
WO (1) | WO2004081990A2 (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102699466A (zh) * | 2012-06-19 | 2012-10-03 | 中国振华集团永光电子有限公司 | 半导体电极组件的钎焊方法 |
CN102804371A (zh) * | 2009-06-11 | 2012-11-28 | 高通股份有限公司 | 用于制造紧密间距倒装芯片集成电路封装的方法 |
CN103219309A (zh) * | 2012-01-23 | 2013-07-24 | 台湾积体电路制造股份有限公司 | 多芯片扇出型封装及其形成方法 |
CN103378039A (zh) * | 2012-04-30 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 用于半导体封装组件的柱形凸块结构 |
US9984987B2 (en) | 2016-08-05 | 2018-05-29 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
Families Citing this family (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10388626B2 (en) | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
EP1278612B1 (en) * | 2000-03-10 | 2010-02-24 | Chippac, Inc. | Flip chip Interconnection structure and method of obtaining the same |
US20050161814A1 (en) | 2002-12-27 | 2005-07-28 | Fujitsu Limited | Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus |
US7271497B2 (en) | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
JP2005005598A (ja) * | 2003-06-13 | 2005-01-06 | Fujitsu Ltd | 半導体装置 |
DE102004034821A1 (de) * | 2004-07-19 | 2006-03-16 | Infineon Technologies Ag | Halbleiter und Verfahren zu dessen Herstellung |
US7730790B2 (en) * | 2004-08-10 | 2010-06-08 | Nordson Corporation | Shear test device |
US7256479B2 (en) * | 2005-01-13 | 2007-08-14 | Fairchild Semiconductor Corporation | Method to manufacture a universal footprint for a package with exposed chip |
US7148086B2 (en) * | 2005-04-28 | 2006-12-12 | Stats Chippac Ltd. | Semiconductor package with controlled solder bump wetting and fabrication method therefor |
US20090057852A1 (en) * | 2007-08-27 | 2009-03-05 | Madrid Ruben P | Thermally enhanced thin semiconductor package |
US7371616B2 (en) * | 2006-01-05 | 2008-05-13 | Fairchild Semiconductor Corporation | Clipless and wireless semiconductor die package and method for making the same |
US7541221B2 (en) * | 2006-02-04 | 2009-06-02 | Stats Chippac Ltd. | Integrated circuit package system with leadfinger support |
US20070210426A1 (en) * | 2006-03-07 | 2007-09-13 | Gerber Mark A | Gold-bumped interposer for vertically integrated semiconductor system |
DE102006024943A1 (de) * | 2006-05-29 | 2007-12-06 | Texas Instruments Deutschland Gmbh | Entwurf und Verfahren für die Befestigung eines Dies auf einem Leiterrahmen in einem Halbleiterbauelement |
US7626262B2 (en) * | 2006-06-14 | 2009-12-01 | Infineon Technologies Ag | Electrically conductive connection, electronic component and method for their production |
US7713782B2 (en) * | 2006-09-22 | 2010-05-11 | Stats Chippac, Inc. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps |
US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
US7659192B2 (en) * | 2006-12-29 | 2010-02-09 | Intel Corporation | Methods of forming stepped bumps and structures formed thereby |
US7768105B2 (en) * | 2007-01-24 | 2010-08-03 | Fairchild Semiconductor Corporation | Pre-molded clip structure |
US8106501B2 (en) | 2008-12-12 | 2012-01-31 | Fairchild Semiconductor Corporation | Semiconductor die package including low stress configuration |
KR101391925B1 (ko) * | 2007-02-28 | 2014-05-07 | 페어차일드코리아반도체 주식회사 | 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형 |
KR101489325B1 (ko) | 2007-03-12 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법 |
US7659531B2 (en) * | 2007-04-13 | 2010-02-09 | Fairchild Semiconductor Corporation | Optical coupler package |
US8637394B2 (en) * | 2007-07-05 | 2014-01-28 | Stats Chippac Ltd. | Integrated circuit package system with flex bump |
JP5282380B2 (ja) * | 2007-08-06 | 2013-09-04 | 富士通株式会社 | 半導体装置およびその製造方法 |
US7902657B2 (en) * | 2007-08-28 | 2011-03-08 | Fairchild Semiconductor Corporation | Self locking and aligning clip structure for semiconductor die package |
US7737548B2 (en) | 2007-08-29 | 2010-06-15 | Fairchild Semiconductor Corporation | Semiconductor die package including heat sinks |
US20090057855A1 (en) * | 2007-08-30 | 2009-03-05 | Maria Clemens Quinones | Semiconductor die package including stand off structures |
US7750466B2 (en) * | 2007-09-07 | 2010-07-06 | Intel Corporation | Microelectronic assembly having second level interconnects including solder joints reinforced with crack arrester elements and method of forming same |
JP4431606B2 (ja) * | 2007-10-05 | 2010-03-17 | シャープ株式会社 | 半導体装置、半導体装置の実装方法、および半導体装置の実装構造 |
US20090140266A1 (en) * | 2007-11-30 | 2009-06-04 | Yong Liu | Package including oriented devices |
US7589338B2 (en) * | 2007-11-30 | 2009-09-15 | Fairchild Semiconductor Corporation | Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice |
KR20090062612A (ko) * | 2007-12-13 | 2009-06-17 | 페어차일드코리아반도체 주식회사 | 멀티 칩 패키지 |
US7749887B2 (en) * | 2007-12-18 | 2010-07-06 | Micron Technology, Inc. | Methods of fluxless micro-piercing of solder balls, and resulting devices |
US7781872B2 (en) * | 2007-12-19 | 2010-08-24 | Fairchild Semiconductor Corporation | Package with multiple dies |
US8106406B2 (en) | 2008-01-09 | 2012-01-31 | Fairchild Semiconductor Corporation | Die package including substrate with molded device |
US7626249B2 (en) * | 2008-01-10 | 2009-12-01 | Fairchild Semiconductor Corporation | Flex clip connector for semiconductor device |
US20090194856A1 (en) * | 2008-02-06 | 2009-08-06 | Gomez Jocel P | Molded package assembly |
KR101524545B1 (ko) * | 2008-02-28 | 2015-06-01 | 페어차일드코리아반도체 주식회사 | 전력 소자 패키지 및 그 제조 방법 |
US8018054B2 (en) * | 2008-03-12 | 2011-09-13 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple semiconductor dice |
US7768108B2 (en) * | 2008-03-12 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die package including embedded flip chip |
KR101519062B1 (ko) * | 2008-03-31 | 2015-05-11 | 페어차일드코리아반도체 주식회사 | 반도체 소자 패키지 |
US9324611B2 (en) | 2008-04-03 | 2016-04-26 | Micron Technology, Inc. | Corrosion resistant via connections in semiconductor substrates and methods of making same |
US20090278241A1 (en) * | 2008-05-08 | 2009-11-12 | Yong Liu | Semiconductor die package including die stacked on premolded substrate including die |
US7951648B2 (en) | 2008-07-01 | 2011-05-31 | International Business Machines Corporation | Chip-level underfill method of manufacture |
US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
US8193618B2 (en) | 2008-12-12 | 2012-06-05 | Fairchild Semiconductor Corporation | Semiconductor die package with clip interconnection |
US20100148337A1 (en) * | 2008-12-17 | 2010-06-17 | Yong Liu | Stackable semiconductor package and process to manufacture same |
US7973393B2 (en) | 2009-02-04 | 2011-07-05 | Fairchild Semiconductor Corporation | Stacked micro optocouplers and methods of making the same |
US8222718B2 (en) * | 2009-02-05 | 2012-07-17 | Fairchild Semiconductor Corporation | Semiconductor die package and method for making the same |
US8377816B2 (en) | 2009-07-30 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming electrical connections |
US8841766B2 (en) | 2009-07-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
TW201133745A (en) * | 2009-08-27 | 2011-10-01 | Advanpack Solutions Private Ltd | Stacked bump interconnection structure and semiconductor package formed using the same |
US8324738B2 (en) | 2009-09-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
US8659155B2 (en) * | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
US8766439B2 (en) | 2009-12-10 | 2014-07-01 | International Business Machines Corporation | Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip |
US8610270B2 (en) | 2010-02-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
US8441124B2 (en) | 2010-04-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
US9018758B2 (en) | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
US8360303B2 (en) * | 2010-07-22 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming low stress joints using thermal compress bonding |
US8381965B2 (en) * | 2010-07-22 | 2013-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal compress bonding |
CN101937858A (zh) * | 2010-08-03 | 2011-01-05 | 清华大学 | 一种倒装芯片凸点结构的圆片级制造方法 |
US8546254B2 (en) | 2010-08-19 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
US20120161312A1 (en) * | 2010-12-23 | 2012-06-28 | Hossain Md Altaf | Non-solder metal bumps to reduce package height |
US8421204B2 (en) | 2011-05-18 | 2013-04-16 | Fairchild Semiconductor Corporation | Embedded semiconductor power modules and packages |
TWI453837B (zh) * | 2011-06-13 | 2014-09-21 | Advanced Semiconductor Eng | 具有非導電層的半導體封裝及其製造方法 |
JP6035714B2 (ja) * | 2011-08-17 | 2016-11-30 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、及び、電子機器 |
US9818734B2 (en) | 2012-09-14 | 2017-11-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over a temporary substrate |
US9385052B2 (en) | 2012-09-14 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages |
US9576888B2 (en) * | 2013-03-12 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on-package joint structure with molding open bumps |
US9893017B2 (en) | 2015-04-09 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Double-sided semiconductor package and dual-mold method of making same |
FR3041625B1 (fr) * | 2015-09-29 | 2021-07-30 | Tronics Microsystems | Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support |
WO2017171857A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Systems and methods for replaceable ball grid array (bga) packages on board substrates |
US10600755B2 (en) * | 2017-08-10 | 2020-03-24 | Amkor Technology, Inc. | Method of manufacturing an electronic device and electronic device manufactured thereby |
Family Cites Families (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1170186A (en) | 1968-08-21 | 1969-11-12 | Standard Telephones Cables Ltd | Relay Contacts and Method of Manufacture of Same. |
US4005472A (en) * | 1975-05-19 | 1977-01-25 | National Semiconductor Corporation | Method for gold plating of metallic layers on semiconductive devices |
US4188438A (en) * | 1975-06-02 | 1980-02-12 | National Semiconductor Corporation | Antioxidant coating of copper parts for thermal compression gang bonding of semiconductive devices |
JPS6115370A (ja) * | 1984-06-30 | 1986-01-23 | Toshiba Corp | 半導体装置 |
DE3344291A1 (de) * | 1983-12-07 | 1985-06-13 | Skw Trostberg Ag, 8223 Trostberg | Dispergiermittel fuer salzhaltige systeme |
JPS60160554A (ja) * | 1984-01-31 | 1985-08-22 | Nec Home Electronics Ltd | 螢光ランプ |
US5829128A (en) * | 1993-11-16 | 1998-11-03 | Formfactor, Inc. | Method of mounting resilient contact structures to semiconductor devices |
US5476211A (en) * | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
JPS6297360A (ja) * | 1985-10-24 | 1987-05-06 | Mitsubishi Metal Corp | 半導体装置のボンデイングワイヤ用表面被覆高純度銅極細線 |
JPS62206857A (ja) * | 1986-03-07 | 1987-09-11 | Oki Electric Ind Co Ltd | 突起状電極の形成方法 |
US4750666A (en) * | 1986-04-17 | 1988-06-14 | General Electric Company | Method of fabricating gold bumps on IC's and power chips |
JP2515745B2 (ja) * | 1986-07-14 | 1996-07-10 | 株式会社日立製作所 | 半導体装置の製造方法 |
US5189507A (en) * | 1986-12-17 | 1993-02-23 | Raychem Corporation | Interconnection of electronic components |
US4976393A (en) | 1986-12-26 | 1990-12-11 | Hitachi, Ltd. | Semiconductor device and production process thereof, as well as wire bonding device used therefor |
JPS63168031A (ja) * | 1986-12-29 | 1988-07-12 | Tanaka Electron Ind Co Ltd | 半導体装置 |
US5169680A (en) * | 1987-05-07 | 1992-12-08 | Intel Corporation | Electroless deposition for IC fabrication |
JP2852134B2 (ja) * | 1991-02-20 | 1999-01-27 | 日本電気株式会社 | バンプ形成方法 |
JP3116412B2 (ja) * | 1991-05-16 | 2000-12-11 | セイコーエプソン株式会社 | 半導体装置のバンプ電極形成方法、表示装置及び電子印字装置 |
US6295729B1 (en) * | 1992-10-19 | 2001-10-02 | International Business Machines Corporation | Angled flying lead wire bonding process |
US5334804A (en) * | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
US5485949A (en) | 1993-04-30 | 1996-01-23 | Matsushita Electric Industrial Co., Ltd. | Capillary for a wire bonding apparatus and a method for forming an electric connection bump using the capillary |
JPH0766209A (ja) | 1993-08-23 | 1995-03-10 | Furukawa Electric Co Ltd:The | バンプ材並びにその製造方法及びそれを用いた光部品実装方法 |
US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JP2928724B2 (ja) | 1994-05-18 | 1999-08-03 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5813115A (en) * | 1994-08-03 | 1998-09-29 | Matsushita Electric Industrial Co., Ltd. | Method of mounting a semiconductor chip on a wiring substrate |
JP2992464B2 (ja) * | 1994-11-04 | 1999-12-20 | キヤノン株式会社 | 集電電極用被覆ワイヤ、該集電電極用被覆ワイヤを用いた光起電力素子及びその製造方法 |
US5854558A (en) * | 1994-11-18 | 1998-12-29 | Fujitsu Limited | Test board for testing a semiconductor device and method of testing the semiconductor device |
DE4442960C1 (de) * | 1994-12-02 | 1995-12-21 | Fraunhofer Ges Forschung | Lothöcker für die Flip-Chip-Montage und Verfahren zu dessen Herstellung |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
EP0722198A3 (en) * | 1995-01-10 | 1996-10-23 | Texas Instruments Inc | Bond wire with integrated contact area |
US5660319A (en) * | 1995-01-17 | 1997-08-26 | Texas Instruments Incorporated | Ultrasonic bonding process |
US5831441A (en) * | 1995-06-30 | 1998-11-03 | Fujitsu Limited | Test board for testing a semiconductor device, method of testing the semiconductor device, contact device, test method using the contact device, and test jig for testing the semiconductor device |
US5789809A (en) | 1995-08-22 | 1998-08-04 | National Semiconductor Corporation | Thermally enhanced micro-ball grid array package |
KR100186752B1 (ko) * | 1995-09-04 | 1999-04-15 | 황인길 | 반도체 칩 본딩방법 |
US5637916A (en) | 1996-02-02 | 1997-06-10 | National Semiconductor Corporation | Carrier based IC packaging arrangement |
JP3409957B2 (ja) * | 1996-03-06 | 2003-05-26 | 松下電器産業株式会社 | 半導体ユニット及びその形成方法 |
JP3146345B2 (ja) * | 1996-03-11 | 2001-03-12 | アムコー テクノロジー コリア インコーポレーティド | バンプチップスケール半導体パッケージのバンプ形成方法 |
US6104201A (en) * | 1996-11-08 | 2000-08-15 | International Business Machines Corporation | Method and apparatus for passive characterization of semiconductor substrates subjected to high energy (MEV) ion implementation using high-injection surface photovoltage |
JP3065549B2 (ja) * | 1997-01-09 | 2000-07-17 | 富士通株式会社 | 半導体チップ部品の実装方法 |
JP2962351B2 (ja) * | 1997-03-31 | 1999-10-12 | 日本電気株式会社 | 半導体チップへの接合構造及びそれを用いた半導体装置 |
KR100244504B1 (ko) * | 1997-11-15 | 2000-02-01 | 김영환 | 칩 사이즈 반도체 패키지의 제조방법 |
US5969418A (en) * | 1997-12-22 | 1999-10-19 | Ford Motor Company | Method of attaching a chip to a flexible substrate |
US6023094A (en) | 1998-01-14 | 2000-02-08 | National Semiconductor Corporation | Semiconductor wafer having a bottom surface protective coating |
JPH11307585A (ja) * | 1998-04-22 | 1999-11-05 | Sony Corp | 半導体装置 |
US6084308A (en) | 1998-06-30 | 2000-07-04 | National Semiconductor Corporation | Chip-on-chip integrated circuit package and method for making the same |
US6133634A (en) | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6246011B1 (en) * | 1998-12-02 | 2001-06-12 | Nortel Networks Limited | Solder joint reliability |
JP4260263B2 (ja) * | 1999-01-28 | 2009-04-30 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2001326245A (ja) * | 2000-05-16 | 2001-11-22 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP3382918B2 (ja) | 2000-05-31 | 2003-03-04 | 田中電子工業株式会社 | 半導体素子接続用金線 |
EP1215724B1 (en) * | 2000-11-20 | 2012-10-31 | Texas Instruments Incorporated | Wire bonded semiconductor device with low capacitance coupling |
JP3910363B2 (ja) * | 2000-12-28 | 2007-04-25 | 富士通株式会社 | 外部接続端子 |
US6469384B2 (en) | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US6653170B1 (en) * | 2001-02-06 | 2003-11-25 | Charles W. C. Lin | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit |
US6495397B2 (en) * | 2001-03-28 | 2002-12-17 | Intel Corporation | Fluxless flip chip interconnection |
JP3845033B2 (ja) * | 2001-03-29 | 2006-11-15 | 株式会社東芝 | 半導体パッケージ及びその製造方法 |
JP2002353371A (ja) * | 2001-05-25 | 2002-12-06 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002368034A (ja) * | 2001-06-11 | 2002-12-20 | Denso Corp | バンプ形成装置及びそれを用いたバンプ形成方法 |
JP3868766B2 (ja) * | 2001-07-02 | 2007-01-17 | 株式会社東芝 | 半導体装置 |
US6500760B1 (en) * | 2001-08-02 | 2002-12-31 | Sandia Corporation | Gold-based electrical interconnections for microelectronic devices |
JP2003068783A (ja) * | 2001-08-23 | 2003-03-07 | Tanaka Electronics Ind Co Ltd | 無鉛クラッドワイヤ |
EP1295985B1 (en) * | 2001-09-20 | 2005-08-31 | Sumitomo Rubber Industries Ltd. | Method for making coated metallic cord |
US6566749B1 (en) | 2002-01-15 | 2003-05-20 | Fairchild Semiconductor Corporation | Semiconductor die package with improved thermal and electrical performance |
TWI287282B (en) * | 2002-03-14 | 2007-09-21 | Fairchild Kr Semiconductor Ltd | Semiconductor package having oxidation-free copper wire |
TW200414453A (en) * | 2002-03-26 | 2004-08-01 | Sumitomo Electric Wintec Inc | Bonding wire and IC device using the bonding wire |
JP4204359B2 (ja) * | 2002-03-26 | 2009-01-07 | 株式会社野毛電気工業 | ボンディングワイヤーおよびそれを使用した集積回路デバイス |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
JP3716391B2 (ja) * | 2003-03-18 | 2005-11-16 | 株式会社野毛電気工業 | バンプ形成用パラジウム被覆ワイヤ |
-
2003
- 2003-03-10 US US10/386,211 patent/US7271497B2/en not_active Expired - Lifetime
-
2004
- 2004-03-09 TW TW093106173A patent/TWI353643B/zh not_active IP Right Cessation
- 2004-03-10 JP JP2006507108A patent/JP2006520103A/ja active Pending
- 2004-03-10 DE DE112004000360T patent/DE112004000360T5/de not_active Ceased
- 2004-03-10 WO PCT/US2004/007528 patent/WO2004081990A2/en active Application Filing
- 2004-03-10 CN CNB2004800067345A patent/CN100565857C/zh not_active Expired - Lifetime
-
2006
- 2006-04-14 US US11/404,650 patent/US7501337B2/en not_active Expired - Fee Related
-
2009
- 2009-01-22 US US12/357,981 patent/US7932171B2/en not_active Expired - Lifetime
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102804371A (zh) * | 2009-06-11 | 2012-11-28 | 高通股份有限公司 | 用于制造紧密间距倒装芯片集成电路封装的方法 |
CN102804371B (zh) * | 2009-06-11 | 2015-05-13 | 高通股份有限公司 | 用于制造紧密间距倒装芯片集成电路封装的方法 |
CN103219309A (zh) * | 2012-01-23 | 2013-07-24 | 台湾积体电路制造股份有限公司 | 多芯片扇出型封装及其形成方法 |
US10163857B2 (en) | 2012-01-23 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip fan out package and methods of forming the same |
US10833039B2 (en) | 2012-01-23 | 2020-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip fan out package and methods of forming the same |
CN103378039A (zh) * | 2012-04-30 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 用于半导体封装组件的柱形凸块结构 |
CN103378039B (zh) * | 2012-04-30 | 2016-08-03 | 台湾积体电路制造股份有限公司 | 用于半导体封装组件的柱形凸块结构 |
CN102699466A (zh) * | 2012-06-19 | 2012-10-03 | 中国振华集团永光电子有限公司 | 半导体电极组件的钎焊方法 |
CN102699466B (zh) * | 2012-06-19 | 2015-08-19 | 中国振华集团永光电子有限公司 | 半导体电极组件的钎焊方法 |
US9984987B2 (en) | 2016-08-05 | 2018-05-29 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
US10141275B2 (en) | 2016-08-05 | 2018-11-27 | Nanya Technology Corporation | Method for manufacturing a semiconductor structure |
Also Published As
Publication number | Publication date |
---|---|
US20060189116A1 (en) | 2006-08-24 |
WO2004081990A3 (en) | 2005-03-31 |
US7932171B2 (en) | 2011-04-26 |
CN100565857C (zh) | 2009-12-02 |
US20040178481A1 (en) | 2004-09-16 |
TW200425364A (en) | 2004-11-16 |
WO2004081990A2 (en) | 2004-09-23 |
US7501337B2 (en) | 2009-03-10 |
JP2006520103A (ja) | 2006-08-31 |
US20090186452A1 (en) | 2009-07-23 |
US7271497B2 (en) | 2007-09-18 |
DE112004000360T5 (de) | 2013-04-11 |
TWI353643B (en) | 2011-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100565857C (zh) | 用于倒装片的由被覆线形成的涂覆金属柱形突起 | |
TWI390642B (zh) | 穩定之金凸塊焊料連接 | |
US7847399B2 (en) | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles | |
KR100719905B1 (ko) | Sn-Bi계 솔더 합금 및 이를 이용한 반도체 소자 | |
US5476211A (en) | Method of manufacturing electrical contacts, using a sacrificial member | |
US6350386B1 (en) | Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly | |
KR101119839B1 (ko) | 범프 구조물 및 그 제조 방법 | |
US9412715B2 (en) | Semiconductor device, electronic device, and semiconductor device manufacturing method | |
US20240047439A1 (en) | Batch Soldering of Different Elements in Power Module | |
EP0966038A2 (en) | Bonding of semiconductor power devices | |
KR20100080352A (ko) | 금속 범프를 가진 반도체 패키지 기판 | |
US20210104454A1 (en) | Wiring substrate device | |
CN115148697A (zh) | 半导体封装结构及其制造方法 | |
JPH08111432A (ja) | 半導体装置及びその製造方法 | |
CN1502439A (zh) | 预镀可湿引线框倒焊晶片组件限制回流时焊料扩散的方法 | |
JP2002026084A (ja) | 半導体装置用テープキャリア及びその製造方法 | |
JPH08316272A (ja) | 半導体装置、その製造方法、及び半導体装置用フレキシブル基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20091202 |