CN103378039B - 用于半导体封装组件的柱形凸块结构 - Google Patents
用于半导体封装组件的柱形凸块结构 Download PDFInfo
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- CN103378039B CN103378039B CN201210496981.4A CN201210496981A CN103378039B CN 103378039 B CN103378039 B CN 103378039B CN 201210496981 A CN201210496981 A CN 201210496981A CN 103378039 B CN103378039 B CN 103378039B
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- stud bumps
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- tube core
- package
- outer peripheral
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- 239000004065 semiconductor Substances 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 230000005855 radiation Effects 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000000945 filler Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 229910000838 Al alloy Inorganic materials 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000155 melt Substances 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000005728 strengthening Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims 12
- 239000000203 mixture Substances 0.000 description 6
- 239000012141 concentrate Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000013467 fragmentation Methods 0.000 description 3
- 238000006062 fragmentation reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L21/4814—Conductive parts
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Abstract
一种半导体封装件结构包括衬底、接合到衬底的管芯以及将管芯连接到衬底的一个或多个柱形凸块结构,其中每个柱形凸块结构都具有柱形凸块和封装该柱形凸块的焊球,从而增强散热并降低半导体封装件结构中的高应力集中。本发明提供了用于半导体封装组件的柱形凸块结构。
Description
技术领域
一般而言,本发明涉及芯片封装,更具体而言,涉及用于诸如倒装芯片、晶圆级芯片规模封装件和堆叠封装件(packageonpackage)组件的半导体封装组件的柱形凸块(studbump)结构。
背景技术
倒装芯片组件包括使用芯片的导电凸块接合焊盘直接电连接到诸如陶瓷衬底或电路板的载具上的面向下的(即,“倒装的”)半导体芯片或管芯。倒装芯片组件通常通过以下步骤制造:在芯片的凸块接合焊盘上设置焊料凸块,将焊料凸块接合的芯片(solderbumpedchip)接合至载具,以及在芯片和载具之间应用粘着性底部填充物。
倒装芯片组件的凸块发挥多种功能但由于应力导致易出现故障。在这些功能中,凸块提供从芯片到其上安装芯片的衬底的导电路径。凸块还提供芯片到衬底的部分机械安装。可惜的是,凸块易于碎裂,通常是由应力引起的,包括通过芯片和载具衬底之间的热膨胀不匹配引起的应力。当发生热变化时,热膨胀系数的显著差异将应力引入结构。大部分应力集中在芯片和/或倒装芯片组件的角部上,且芯片越大,集中在管芯和/或倒装芯片组件上的应力就越多。图2是示出将焊球或焊料凸块40安装到芯片20的接合焊盘30的倒装芯片组件的一部分。由于倒装芯片组件中的材料之间的热膨胀不匹配引起的应力,在焊料凸块40中出现裂缝50。这些裂缝在接合处在所经受的应力下可能更容易形成,并更容易沿着焊料凸块40的长度扩展。
在金属凸块中使用铜使得这个问题更加恶化。因为铜是刚性的,高应力可能施加在邻接铜凸块的焊料上,并因此使焊料更容易出现碎裂。
解决热膨胀系数差异引起的问题的一种方法是使用环氧树脂底部填充物填充芯片和衬底之间的间隙。底部填充物有助于扩散应力并保护焊料凸块或焊球。但有时底部填充物也具有高热膨胀系数,造成芯片和底部填充物之间的膨胀不匹配。这种不匹配将更多的应力引入封装件中,从而可能导致故障。
近些年来引入了晶圆级芯片规模封装件(WLCSP),通常用于增大密度、增强性能和增加成本效益,同时在电子封装产业中减轻器件的重量并减小器件的尺寸并满足市场趋向于增强小型化和功能性的需求。当前的WLCSP技术的一个缺点是在焊球和电极接线柱(electrodepost)之间形成裂缝。焊球或焊料凸块通常被直接设置在凸块电极或接线柱上,依赖用于结构完整性的焊接点。组成WLCSP器件的不同层通常具有不同的热膨胀系数。结果,在接线柱和凸块电极之间的接合处表现出由这种不同引起的相对大的应力,这种应力常常会导致在凸块电极/接线柱和焊球或焊料凸块之间的接合区域中形成裂缝。
发明内容
为解决上述技术问题,一方面,本发明提供了一种封装件结构,包括:衬底;管芯,接合到所述衬底;以及一个或多个柱形凸块结构,将所述管芯连接到所述衬底,其中,每个柱形凸块结构具有柱形凸块和封装所述柱形凸块的焊球,从而增强散热并降低所述封装件结构中的高应力集中。
在所述的封装件结构中,每个柱形凸块结构都连接到接合焊盘。
所述的封装件结构还包括将所述管芯连接到所述衬底的一个或多个柱形凸块。
所述的封装件结构还包括将所述管芯连接到所述衬底的一个或多个铜柱。
在所述的封装件结构中,所述柱形凸块包括选自由铝、铝合金、铜、铜合金、金、金合金所组成的组中的材料。
所述的封装件结构还包括设置在所述管芯、所述衬底和所述一个或多个柱形凸块结构之间的用于强化所述封装件结构的底部填充物。
在所述的封装件结构中,在靠近所述管芯的外围处,所述一个或多个柱形凸块结构将所述管芯连接到所述衬底。
在所述的封装件结构中,在靠近所述管芯的角部处,所述一个或多个柱形凸块结构将所述管芯连接到所述衬底。
另一方面,本发明还提供了一种堆叠封装件结构,包括:第一衬底;第一管芯,接合到所述第一衬底;第二衬底,设置在所述第一管芯上方并接合到所述第一衬底;第二管芯,接合到所述第二衬底;以及一个或多个第一柱形凸块结构,将所述第二衬底连接到所述第一衬底,其中每个第一柱形凸块结构都具有柱形凸块和封装所述柱形凸块的焊球,从而增强散热并降低所述堆叠封装件结构中的高应力集中。
在所述的堆叠封装件结构中,每个第一柱形凸块结构都连接到接合焊盘。
所述的堆叠封装件结构还包括将所述第一管芯连接到所述第一衬底的一个或多个焊料凸块。
所述的堆叠封装件结构还包括将所述第一管芯连接到所述第一衬底的一个或多个铜柱。
在所述的堆叠封装件结构中,所述柱形凸块包含选自由铝、铝合金、铜、铜合金、金、金合金所组成的组中的材料。
在所述的堆叠封装件结构中,在靠近所述第一衬底的外周处,所述一个或多个第一柱形凸块结构将所述第二衬底连接到所述第一衬底。
在所述的堆叠封装件结构中,在靠近所述第一衬底的角部处,所述一个或多个第一柱形凸块结构将所述第二衬底连接到所述第一衬底。
所述的堆叠封装件结构还包括连接到所述第一衬底的一个或多个第二柱形凸块结构,其中,每个第二柱形凸块结构具有柱形凸块和封装所述柱形凸块的焊球。
又一方面,本发明提供了一种在封装件结构中形成柱形凸块结构的方法,包括:提供导线;将所述导线的一端按压到接合焊盘,并熔化该导线端以在所述接合焊盘上形成柱形凸块;接近所述柱形凸块的上方切断所述导线的另一端;以及将焊球焊接到所述柱形凸块的顶面,所述焊球封装所述柱形凸块。
在所述的在封装件结构中形成柱形凸块结构的方法中,所述导线包含铝、铝合金、铜、铜合金、金或金合金。
在所述的在封装件结构中形成柱形凸块结构的方法中,按压并熔化所述导线以在所述接合焊盘上形成柱形凸块是通过引线接合工具来实施的。
在所述的在封装件结构中形成柱形凸块结构的方法中,按压并熔化所述导线以在所述接合焊盘上形成柱形凸块是通过柱形凸块接合器来实施的。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制。实际上,为了清楚论述起见,各种部件的尺寸可以被任意增大或缩小。
图1是根据本发明的一个实施例示出制造用于半导体封装组件的柱形凸块结构的方法的流程图。
图2是举例说明在焊球或焊料凸块中碎裂的倒装芯片组件的一部分。
图3是根据本发明的一个实施例在形成柱形凸块结构的最初阶段的半导体器件封装件的一部分的横截面图。
图4是根据本发明的一个实施例在形成柱形凸块结构的另一阶段的图3的半导体器件封装件的一部分的横截面图。
图5是根据本发明的一个实施例在倒装芯片组件中配置的具有一个或多个柱形凸块结构的倒装芯片凸块组件的横截面图。
图6是根据本发明的一个实施例在倒装芯片组件中配置的具有一个或多个柱形凸块结构的倒装芯片铜柱组件的横截面图。
图7是根据本发明的一个实施例在封装件中配置的具有一个或多个柱形凸块结构的晶圆级芯片规模封装件的横截面图。
图8是根据本发明的一个实施例在堆叠封装件中配置的具有一个或多个柱形凸块结构的堆叠封装件结构的横截面图。
图9是根据本发明的一个实施例示出柱形凸块结构的布置的图8的堆叠封装件结构的平面图。
具体实施方式
在以下描述中,阐述了许多具体的细节从而提供对本发明的实施例的透彻理解。然而,本领域的普通技术人员应意识到没有这些具体的细节也可以实施本发明的实施例。在一些实例中,没有详细描述公知的结构和工艺以便避免不必要地模糊本发明的实施例。
在整个说明书中提及的“一个实施例”或“实施例”意为关于该实施例描述的特定部件、结构或特征包括在本发明的至少一个实施例中。因此在本说明书的各个位置出现的短语“在一个实施中”或“在实施例中”不一定全都是指同一个实施例。而且,在一个或多个实施例中可以以任何合适的方式组合特定的部件、结构或特征。应当理解,以下附图没有按比例绘制;实际上这些附图仅是用于举例说明的目的。
图1示出的是根据本发明的多个方面制造用于半导体封装组件(诸如,例如倒装芯片、晶圆级芯片规模封装件和堆叠封装件组件)的柱形凸块结构的方法2的流程图。柱形凸块结构通过柱形凸块接合器和/或引线接合工具来实现的。参照图1,方法包括框4,其中,提供了导线。导线可以由铝、铝合金、铜、铜合金、金、金合金、无铅导体等组成。方法2包括框6,其中,将导线的一端按压到接合焊盘上。然后将该导线端熔化以在接合焊盘上形成球体或柱形凸块。引线接合工具对着接合焊盘按压该球体,施加机械力、热量及超声能量来形成金属连接件。方法2包括框8,其中,通过引线切割器接近柱形凸块的上方切断导线的另一端。如果移动仅是垂直的,则可能会在柱形凸块上留下“尾巴”。该尾巴的高度和重复性主要取决于引线的组成。图3是在管芯20的接合焊盘30上形成的具有尾巴65的柱形凸块60的横截面图。所得到的保留在接合焊盘30上的球或柱形凸块60提供了与下面的接合焊盘金属的永久性可靠的连接。本领域技术人员可以理解,柱形凸块60的尺寸取决于引线的尺寸和类型以及接合工具和接合工艺。
对于期望更大程度的平衡来帮助补偿热不匹配的应用,在另一实施例中,一种方法实现了在一个柱形凸块的顶部上堆叠另一柱形凸块。
方法2包括框10,其中将焊球焊接到柱形凸块的顶面上,焊球封装柱形凸块。在图4中,将焊球40焊接到柱形凸块60上,形成在柱形凸块60周围并封装柱形凸块60,从而形成柱形凸块结构75。通过在柱形凸块60周围形成焊球40,支持焊球40到管芯20的接合点的切变强度增强。因此,裂缝,诸如图2中所示的开始于焊球40的一端的裂缝50将优选不如在没有柱形凸块60的焊球中那么容易地扩展。柱形凸块结构75优选减缓裂缝的扩展并增强了焊接点的切变强度。
可以理解的是,为完成柱形凸块结构的制造,可以在图1所示的框2至框10之前、期间或之后实施额外的步骤,但是为了简明起见,这些额外的步骤在此处不再详述。
本发明的创造性方面可以应用于各种半导体封装组件,诸如倒装芯片、晶圆级芯片规模封装件和堆叠封装件组件,从而增强散热并降低封装组件中的高应力集中。图5示出了根据本发明的一个实施例在倒装芯片组件中配置的具有一个或多个柱形凸块结构75的倒装芯片凸块组件的横截面图。一个或多个柱形凸块结构75将管芯20连接到衬底100,其中每一个柱形凸块结构75连接到接合焊盘30。在一个实施例中,柱形凸块结构75将管芯20连接到衬底100。由于大部分的应力集中在管芯的角部,在另一实施例中,在靠近管芯20的角部处,一个或多个柱形凸块结构75将管芯20连接到衬底100。在另一实施例中,在靠近管芯20的外围处,一个或多个柱形凸块结构75将管芯20连接到衬底100。在又一实施例中,柱形凸块结构75和焊球或焊料凸块40的混合物将管芯20连接到衬底100。在又一实施例中,代替焊料凸块40,柱形凸块结构75和铜柱110的混合物将管芯20连接到衬底100,如图6所示。图5和图6还示出了在管芯20和衬底100之间以及在柱形凸块结构75、焊料凸块40和/或铜柱110周围加入底部填充物80。底部填充物80有助于扩散应力并保护柱形凸块结构75、焊料凸块40和/或铜柱110。
图7示出了根据本发明的一个实施例在封装件中配置的具有一个或多个柱形凸块结构75的晶圆级芯片规模封装件的横截面图。一个或多个柱形凸块结构75接合到管芯20,其中每一个柱形凸块结构都连接到接合焊盘30。由于大部分的应力集中在管芯20的角部,在一个实施例中,在靠近管芯20的角部处,一个或多个柱形凸块结构75接合到管芯。在本发明的另一实施例中,在靠近管芯20的外周处,一个或多个柱形凸块结构75接合到管芯20。在又一实施例中,柱形凸块结构75和焊球40的混合物接合到管芯20。
图7还示出了在柱形凸块结构75和/或焊料凸块40周围加入模塑材料120。模塑材料120有助于扩散应力并保护柱形凸块结构75和/或焊料凸块40。
图8是根据本发明的一个实施例在堆叠封装件中配置的具有一个或多个柱形凸块结构的堆叠封装件结构的横截面图。堆叠封装件结构包括第一衬底130、接合至第一衬底130的第一管芯135、接合至第二衬底140的第二管芯145以及将第二衬底140连接到第一衬底130的一个或多个柱形凸块结构75a。每一个柱形凸块结构都连接到接合焊盘30。由于大部分的应力集中在第一衬底130和/或第二衬底140的角部,在一个实施例中,在靠近第一衬底130或第二衬底140中的任一衬底的角部处,一个或多个柱形凸块结构75a将第一衬底130连接到第二衬底140。在另一实施例中,在靠近第一衬底130或第二衬底140中的任一衬底的中间部分处,一个或多个柱形凸块结构75a将第一衬底130连接到第二衬底140。图9是示出柱形凸块结构75a在第一衬底130中间部分的布置的图8的堆叠封装件结构的平面图。在另一实施例中,在靠近第一衬底130或第二衬底140中的任一衬底的外围处,一个或多个柱形凸块结构75a将第一衬底130连接到第二衬底140。在又一实施例中,柱形凸块结构75a和焊球40的混合物将第一衬底130连接到第二衬底140。
为了进一步从第一管芯135和/或第二管芯145散热并增强散热,根据另一实施例,一个或多个柱形凸块结构75b接合到第一衬底130的底面。
应该理解,为了更好地理解本发明的发明构思而将以上的一些附图简化了。在以上附图中所描述的具体部件和材料并不用来限制本发明的其他的或可选的应用。
可以进一步地理解,图5-图9表示可以形成在关于本发明的多个实施例的接合焊盘或接线柱上的柱形凸块结构的数量的实例。可以在半导体封装组件中形成任何数量的柱形凸块结构,该数量仅受技术限制或在其上形成柱形凸块结构的成本的限制。本发明的多个实施例并不限于任何一个数量的柱形凸块结构。
本发明一个或多个实施例的优点可以包括下列优点中的一个或多个。
在一个或多个实施例中,增强了封装件结构的散热。
在一个或多个实施例中,强化了封装件结构。
在一个或多个实施例中,减少在焊球或焊料凸块中由应力引起的裂缝。
在一个或多个实施例中,减少了可以形成在焊球或焊料凸块中的裂缝的扩展,因此增强了封装件结构的整体可靠性。
本发明还描述了各种示例性实施例。根据一个实施例,一种封装件结构包括衬底、接合到衬底的管芯以及将管芯连接到衬底的一个或多个柱形凸块结构,其中每个柱形凸块结构具有柱形凸块和封装该柱形凸块的焊球,从而增强散热并降低封装件结构中的高应力集中。
根据另一实施例,一种堆叠封装件结构包括第一衬底;接合到第一衬底的第一管芯;设置在第一管芯上方并接合到第一衬底的第二衬底;接合到第二衬底的第二管芯;以及将第二衬底连接到第一衬底的一个或多个柱形凸块结构,其中每个柱形凸块结构具有柱形凸块和封装该柱形凸块的焊球,从而增强散热并降低堆叠封装件结构中的高应力集中。
根据又一实施例,一种在封装件结构中形成柱形凸块结构的方法包括:提供导线;将导线的一端按压到接合焊盘并熔化该导线端以在接合焊盘上形成柱形凸块;接近柱形凸块的上方切断导线的另一端;以及将焊球焊接到柱形凸块的顶面,所述焊球封装柱形凸块。
在前面的详细描述中,已经描述了具体示例性实施例。然而,在不背离本发明较广泛的精神和范围的情况下,可以对本发明做出多种修改、结构、工艺或改变,这对本领域普通技术人员而言是显而易见的。因此,说明书和附图应被视为示例性的而不是限制性的。可以理解,本发明的实施例在权利要求书的范围内能够使用各种其他组合和环境并且能够进行改变或修改。
Claims (17)
1.一种封装件结构,包括:
衬底;
管芯,接合到所述衬底,其中,所述管芯具有靠近所述管芯的第一边缘的第一外围区域和靠近所述管芯的第二边缘并与所述管芯的第一边缘相对的第二外围区域,并且中心区域介于所述第一外围区域和所述第二外围区域之间;以及
多个柱形凸块结构,将所述管芯连接到所述衬底,其中,每个柱形凸块结构具有柱形凸块和封装所述柱形凸块的焊球,从而增强散热并降低所述封装件结构中的高应力集中;
多个导电结构,将所述管芯连接至所述衬底,其中,每个导电结构都没有封装配置,
其中,所述多个柱形凸块结构设置在所述管芯的第一外围区域和所述第二外围区域中并且所述多个导电结构设置在所述管芯的中心区域中。
2.根据权利要求1所述的封装件结构,其中,每个柱形凸块结构都连接到接合焊盘。
3.根据权利要求1所述的封装件结构,其中,所述多个导电结构中的导电结构为将所述管芯连接到所述衬底的焊料凸块。
4.根据权利要求1所述的封装件结构,其中,所述多个导电结构中的导电结构为将所述管芯连接到所述衬底的铜柱。
5.根据权利要求1所述的封装件结构,其中,所述柱形凸块包括选自由铝、铝合金、铜、铜合金、金、金合金所组成的组中的材料。
6.根据权利要求1所述的封装件结构,还包括设置在所述管芯、所述衬底和所述多个柱形凸块结构之间的用于强化所述封装件结构的底部填充物。
7.根据权利要求1所述的封装件结构,其中,在所述第一外围区域中的所述管芯的第一角部处,所述多个柱形凸块结构中的第一柱形凸块结构将所述管芯连接到所述衬底,并且在所述第二外围区域中的所述管芯的第二角部处,所述多个柱形凸块结构中的第二柱形凸块结构将所述管芯连接到所述衬底。
8.一种堆叠封装件结构,包括:
第一衬底;
第一管芯,接合到所述第一衬底;
第二衬底,设置在所述第一管芯上方并接合到所述第一衬底,所述第一管芯介于所述第一衬底和所述第二衬底之间;
第二管芯,接合到所述第二衬底;
多个第一柱形凸块结构,将所述第二衬底连接到所述第一衬底,其中所述多个第一柱形凸块结构中的每个第一柱形凸块结构都具有设置在所述第一衬底的顶面上的柱形凸块和封装所述柱形凸块的焊球,从而增强散热并降低所述堆叠封装件结构中的高应力集中;以及
多个导电结构,将所述第二衬底连接至所述第一衬底,其中,所述多个导电结构中的每个导电结构没有封装配置,
其中,所述第一柱形凸块结构和所述多个导电结构配置为所述第一衬底上的预定图案,所述预定图案包括设置为靠近所述管芯的侧边的中心区域的所述多个第一柱形凸块结构和设置为靠近所述管芯的角部区域的所述多个导电结构。
9.根据权利要求8所述的堆叠封装件结构,其中,所述多个第一柱形凸块结构中的所述柱形凸块都连接到接合焊盘。
10.根据权利要求8所述的堆叠封装件结构,其中,所述导电结构为将所述第二衬底连接到所述第一衬底的焊料凸块。
11.根据权利要求8所述的堆叠封装件结构,还包括将所述第一管芯连接到所述第一衬底的一个或多个铜柱。
12.根据权利要求8所述的堆叠封装件结构,其中,所述柱形凸块包含选自由铝、铝合金、铜、铜合金、金、金合金所组成的组中的材料。
13.根据权利要求8所述的堆叠封装件结构,还包括连接到所述第一衬底的底面的一个或多个第二柱形凸块结构,其中,每个第二柱形凸块结构具有柱形凸块和封装所述柱形凸块的焊球。
14.一种形成封装件结构的方法,包括:
提供导线;
将所述导线的一端按压到接合焊盘,并熔化该导线端以在所述接合焊盘上形成柱形凸块;
接近所述柱形凸块的上方切断所述导线的另一端;以及
将焊球焊接到所述柱形凸块的顶面,所述焊球封装所述柱形凸块,以在管芯上形成多个柱形凸块结构;
通过多个导电结构和所述多个柱形凸块结构将所述管芯连接至衬底,其中,每个导电结构都没有封装配置,
其中,所述多个柱形凸块结构设置在靠近所述管芯的第一边缘的第一外围区域和靠近所述管芯的第二边缘并与所述管芯的第一边缘相对的第二外围区域中,并且所述多个导电结构设置在所述管芯的所述第一外围区域和所述第二外围区域之间的中心区域中。
15.根据权利要求14所述的形成封装件结构的方法,其中,所述导线包含铝、铝合金、铜、铜合金、金或金合金。
16.根据权利要求14所述的形成封装件结构的方法,其中,按压并熔化所述导线以在所述接合焊盘上形成柱形凸块是通过引线接合工具来实施的。
17.根据权利要求14所述的形成封装件结构的方法,其中,按压并熔化所述导线以在所述接合焊盘上形成柱形凸块是通过柱形凸块接合器来实施的。
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