CN1649118A - 具有上下导电层的导通部的半导体装置及其制造方法 - Google Patents

具有上下导电层的导通部的半导体装置及其制造方法 Download PDF

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CN1649118A
CN1649118A CNA2005100047738A CN200510004773A CN1649118A CN 1649118 A CN1649118 A CN 1649118A CN A2005100047738 A CNA2005100047738 A CN A2005100047738A CN 200510004773 A CN200510004773 A CN 200510004773A CN 1649118 A CN1649118 A CN 1649118A
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base plate
conductive layer
semiconductor
semiconductor device
constituting body
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CN100343965C (zh
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定别当裕康
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Abstract

一种半导体装置，具有底板(1)；支撑在所述底板(1)上的至少一层的第1导电层(2、24)；半导体构成体(4)，其设置在所述底板(1)上，并且，具有半导体基板5和设置在该半导体基板5上的多个外部连接用电极(6、13)；设置在所述半导体构成体(4)周围的所述底板(1)上的绝缘层(15)；第2导电层(19)，其连接于所述半导体构成体(4)的外部连接用电极(6、13)，设置在所述半导体构成体(4)和所述绝缘层(15)上；和上下导通部(27)，其设置在所述绝缘膜(15)和所述底板(1)的侧面，电连接所述第1导电层(2、24)与所述第2导电层(19)。

Description

具有上下导电层的导通部的半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置，尤其是涉及一种具有上下导电层的导通部的半导体装置及其制造方法。
背景技术
特开2003-298005号公报中公开的现有的半导体装置，为了在硅基板的尺寸外还配备作为外部连接用连接端子的焊锡孔，构成为在底板的上面设置在上面具有多个连接衬垫的硅基板，在硅基板周围的底板的上面设置绝缘层，在硅基板和绝缘层的上面设置上层绝缘膜，使上层配线连接于硅基板的连接衬垫设置在上层绝缘膜的上面，用外涂层膜(overcoat)覆盖去除上层配线的连接衬垫部的部分，在上层配线的连接衬垫部上设置焊锡孔。
但是，上述现有半导体装置中，虽仅在硅基板和绝缘层的上面侧设置有上层配线，但为了有效利用空间，考虑在底板的上面或下面设置配线，经设置在绝缘层和底板中设置的转接孔内的上下导通部来连接该配线的一部分与上层配线的一部分。但是，在这种情况下，由于在设置在绝缘层和底板中设置的转接孔内的上下导通部的外侧存在绝缘层和底板，所以半导体装置会比所需的还要大型化。
发明内容
因此，本发明的目的在于提供一种即便具有上下导通部也可小型化的半导体装置及其制造方法。
根据本发明，提供一种半导体装置，其特征在于：具有底板1；支撑在所述底板1上的至少一层的第1导电层2、24；半导体构成体4，其设置在所述底板1上，并且，具有半导体基板5和设置在该半导体基板5上的多个外部连接用电极6、13；设置在所述半导体构成体4周围的所述底板1上的绝缘层15；第2导电层19，其连接于所述半导体构成体4的外部连接用电极6、13，设置在所述半导体构成体4和所述绝缘层15上；和上下导通部27，其设置在所述绝缘膜15和所述底板1的侧面，电连接所述第1导电层2、24与所述第2导电层19。
另外，根据本发明，提供一种半导体装置的制造方法，其特征在于，具有如下步骤：
在具有第1导电层2、24的底板1上，使分别具有半导体基板5和设置在该半导体基板5上的多个外部连接用电极6、13的多个半导体构成体4彼此离间配置；
在所述半导体构成体4周围的所述底板1上形成绝缘层15；
在所述半导体构成体4和所述绝缘层15上，连接于所述半导体构成体4的所述外部连接用电极6、13，形成至少一层第2导电层19；
在所述底板1的对应于所述绝缘层15的区域中，策划切断线41，以包含至少一个所述半导体构成体4；
形成上下导通部27，其包含所述切断线41，向其两侧的区域伸出，并且，电连接所述第1导电层2、24与所述第2导电层19；
沿所述切断线41切断所述绝缘层15、所述底板1和所述上下导通部27，得到多个在侧面上具有上下导通部27的一部分的半导体装置。
根据本发明，因为在设置于半导体构成体周围的底板上的绝缘层和底板侧面中设置上下导通部，所以在上下导通部的外侧不存在绝缘层和底板，因此，即便有上下导通部，也可以小型化。
附图说明
图1的作为本发明第1实施方式的半导体装置的截面图。
图2是切掉图1所示半导体装置的一部分的底面图。
图3是当制造图1和图2所示半导体构成体时、最初准备的半导体装置的截面图。
图4是接于图3的工序的截面图。
图5是接于图4的工序的截面图。
图6是接于图5的工序的截面图。
图7是接于图6的工序的截面图。
图8是接于图7的工序的截面图。
图9是接于图8的工序的截面图。
图10是接于图8的工序的截面图。
图11是接于图10的工序的截面图。
图12是接于图11的工序的截面图。
图13是接于图12的工序的截面图。
图14是图13所示状态的一部分的底面图。
图15是接于图13的工序的截面图。
图16是接于图15的工序的截面图。
图17是接于图16的工序的截面图。
图18是接于图17的工序的截面图。
图19是切掉图18所示状态中的一部分的底面图。
图20是作为本发明第2实施方式的半导体装置的截面图。
图21是作为本发明第3实施方式的半导体装置的截面图。
图22是制造图21所示的半导体装置时、规定工序的截面图。
图23是接于图22的工序的截面图。
图中：1-底板，2-接地层，3-导电性粘接层，4-半导体构成体，5-硅基板，6-连接衬垫，12-配线，13-柱状电极，14-密封膜，15-绝缘层，16-上层绝缘层，19-上层配线，20-上层外涂层膜，22-焊锡孔，24-下层配线(第1导电层)，25-下层外涂层膜，26-沟，27-上下导通部，27a-底部金属层(上下导通层)，52-芯片零件(电子零件)，53-导电材
具体实施方式
(第1实施方式)
图1表示作为本发明第1实施方式的半导体装置的截面图。该半导体装置备有由玻璃布原料(基材)环氧树脂等构成的平面方形的底板1。在底板1的整个上面设置有由铜箔构成的β图案的接地层(第1导电层)2。在接地层2的整个上面设置有导电性粘接层3。
在导电性粘接层3上面的规定部位，粘接着尺寸比底板1的尺寸小一些的平面方形的半导体构成体4的下面。此时，半导体构成体4具有后述的配线12、柱状电极13、密封膜14，通常称为CSP(chip size package)，尤其是如后所述，由于采用在硅晶片上形成配线12、柱状电极13、密封膜14之后、利用切片来得到各个半导体构成体4的方法，所以也特别称作晶片级CSP(W-CSP)。下面，说明半导体构成体4的构成。
半导体构成体4具备硅基板(半导体基板)5。硅基板5的下面粘接于导电性粘接层3上。因此，硅基板5的下面经导电性粘接层3电连接于接地层2上。在硅基板5的上面设置规定功能的集成电路(未图示)，在上面周围部，连接于集成电路而设置有由铝系金属等构成的多个连接衬垫6。在去除连接衬垫6的中央部的硅基板5的上面，设置由氧化硅等构成的绝缘膜7，经设置在绝缘膜7中的开口部8使连接衬垫6的中央部露出。
在绝缘膜7的上面设置有由环氧类树脂或聚酰亚胺类树脂等构成的保护膜9。此时，在对应于绝缘膜7的开口部8的部分中的保护膜9中设置有开口部10。在保护膜9的上面设置有由铜等构成的底部金属层11。在底部金属层11的整个上面设置有由铜构成的配线12。将包含底部金属层11的配线12的一端部经两开口部8、10连接于连接衬垫6上。
在配线12的连接衬垫部上面设置有由铜构成的柱状电极(外部连接用电极)13。在包含配线12的保护膜9的上面设置有由环氧类树脂或聚酰亚胺类树脂等构成的密封膜14，以使其上面变得与柱状电极13的上面大致为齐平面。这样，称为W-CSP的半导体构成体4构成为包含硅基板5、连接衬垫6、绝缘膜7，还包含保护膜9、配线12、柱状电极13、密封膜14。
在半导体构成体4周围的导电性粘接层3的上面设置有方形框状的绝缘层15，使其上面变得与半导体构成体4的上面大致为齐平面。绝缘层15例如由环氧类树脂等热固化树脂、或在这种热固化树脂中混入由硅质填料等构成的加强材料的树脂来构成。
在半导体构成体4和绝缘层15的上面，使其上面平坦地设置了上层绝缘膜16。上层绝缘膜16由用于增强(build up)基板中的通常称为增强材料的、例如在环氧类树脂等热固化树脂中混入由硅质填料等构成的加强材料的树脂来构成。
在对应于柱状电极12的上面中央部的部分中的上层绝缘膜16中设置有开口部17。在上层绝缘膜16的上面设置有由铜等构成的上层底部金属层18。在上层底部金属层18的整个上面设置有由铜构成的上层配线(第2导电层)19。包含上层底部金属层18的上层配线19的一端部经上层绝缘膜16的开口部17连接于柱状电极12的上面。
在包含上层配线19的上层绝缘膜16的上面，设置有由焊料抗蚀剂等构成的上层涂层膜20。在上层配线19的对应于连接衬垫部的部分中的上层涂层膜20中设置有开口部21。在开口部21内和其上方，连接于上层配线19的连接衬垫部而设置有焊锡孔22。在上层涂层膜20上将多个焊锡孔22配置成矩阵状。
在底板1的整个下面设置有由铜等构成的β图案的下层底部金属层23。在下层底部金属层23的整个下面设置有由铜构成的下层配线(第1导电层)24。此时，下层配线24是设置在下层底部金属层23的整个下面中的β图案，构成下层接地层。在下层配线24的整个下面设置有由焊料抗蚀剂等构成的下层涂层膜25。
这里，图2表示切掉图1所示半导体装置的一部分的底面图。在底板1、接地层2、导电性粘接层3、绝缘层15和上层绝缘膜16侧面的规定的两个部位设置有平面大致为半圆形的沟26。在沟26内设置有由铜等构成的底部金属层27a和铜层27b所构成的上下导通层。即，利用沟26与底部金属层27a和铜层27b所构成的上下导通层来构成上下导通部27。在上下导通部27的沟26内设置有由焊料抗蚀剂等构成的侧面绝缘膜28。
另外，将上下导通部27连接于包含接地层3、上层底部金属层18的上层配线19的一部分和包含下层底部金属层23的下层配线24上。即，构成接地层3和下层接地层的下层配线24经上下导通部27和上层配线19的一部分连接于接地用焊锡孔22和半导体构成体4的接地用柱状电极13上。
如上所述，在该半导体装置中，在底板1、绝缘层15和上层绝缘膜16等的侧面中设置平面大致为半圆形的沟26，在沟26内设置有用于连接接地层2与上层配线19的一部分的上下导通部27，所以与例如在设置于底板1、绝缘层15和上层绝缘膜16等中的转接孔内设置上下导通部的情况相比，由于在上下导通部27的外侧不存在底板1、绝缘层15和上层绝缘膜16等，所以可就该部分来实现小型化。
然而，使底板1的尺寸比半导体构成体4的尺寸大一些是由于对应于硅基板5上的连接衬垫7的个数的增加，使焊锡孔22的配置区域比半导体构成体4的尺寸大一些，从而，使上层配线19的连接衬垫部(上层涂布膜20的开口部21内的部分)的尺寸和间距比柱状电极14的尺寸和间距大。
因此，配置成矩阵状的上层配线19的连接衬垫部不仅被配置在对应于半导体构成体4的区域，而且还配置在对应于设置在半导体构成体4周侧面外侧的绝缘层15的区域上。即，配置成矩阵状的焊锡孔22中、至少最外周的焊锡孔22被配置在位于半导体构成体4外侧的周围。
下面，为了说明本半导体装置的制造方法的一例，首先，说明半导体构成体4的制造方法的一例。此时，首先如图3所示，作如下准备，即，在晶片状态的硅基板(半导体基板)5上设置由铝类金属等构成的连接衬垫6、由氧化硅等构成的绝缘膜7和由环氧类树脂或聚酰亚胺类树脂等构成的保护膜9，使连接衬垫6的中央部经绝缘膜7和保护膜9中形成的开口部8、10露出。上述中，在晶片状态的硅基板5中，在形成各半导体构成体的区域中形成规定功能的集成电路，将连接衬垫6分别电连接于形成于对应区域中的集成电路上。
接着，如图4所示，在包含经两开口部8、10露出的连接衬垫6的上面的保护膜9的整个上面形成底部金属层11。此时，底部金属层11可以仅是由无电解电镀形成的铜层，或仅是由溅射形成的铜层，或是在通过溅射形成的钛等薄膜层上通过溅射形成铜层。
之后，在底部金属层11的上面图案形成电镀抗蚀剂膜31。此时，在对应于配线12形成区域的部分中的电镀抗蚀剂膜31中形成有开口部32。接着，通过将底部金属层11作为电镀电流路径进行铜的电解电镀，在电镀抗蚀剂膜31的开口部32内的底部金属层11的上面形成配线12。之后，剥离电镀抗蚀剂膜31。
之后，如图5所示，在包含配线12的底部金属层11的上面图案形成电镀抗蚀剂膜31。此时，在对应于柱状电极13形成区域的部分中的电镀抗蚀剂膜31中形成开口部34。之后，通过将底部金属层11作为电镀电流路径进行铜的电解电镀，在电镀抗蚀剂膜33的开口部34内的配线12的连接衬垫部上面形成柱状电极13。之后，剥离电镀抗蚀剂膜33，之后，当将配线12作为掩膜并蚀刻去除底部金属层11的无用部分时，如图6所示，仅在配线12下残留底部金属层11。
接着，如图7所示，通过网板印刷法、旋涂法、脱膜(die coat)法等，在包含柱状电极13和配线12的保护膜9的整个上面形成由环氧类树脂或聚酰亚胺类树脂等构成的密封膜14，使其厚度比柱状电极13的高度厚。因此，在该状态下，柱状电极13的上面被密封膜14所覆盖。
之后，适当研磨密封膜14和柱状电极13的上面侧，如图8所示，使柱状电极13的上面露出，并且，平坦化包含该露出的柱状电极13上面的密封膜14的上面。这里，适当研磨柱状电极13的上面侧是由于通过电解电镀形成的柱状电极13的高度有差异，所以为了消除该差异，使柱状电极13的高度均匀。
接着，将硅基板5的下面粘贴到切割带(未图示)上，在经过图9所示的切割工序之后，从切割带上剥离时，得到多个图1所示的半导体构成体4。
之后，说明使用如此得到的半导体构成体4来制造图1所示的半导体装置时的一例。首先，如图10所示，在可采取多个图1所示的底板的大小下，虽然不是限定含义，但准备平面方形的底板1。此时，在底板1的整个上面设置由铜箔构成的图案的接地层2，在其整个上面设置导电性粘接层3。另外，图10中，符号41所示区域是对应于切割线(切断线)的区域。
接着，如图11所示，在导电性粘接层3上面的规定部位分别粘接半导体构成体4的硅基板5的下面。如后所述，由于通过切割线切断底板1来得到各个半导体构成体4，所以各半导体构成体4被固定在其切断位置与切割线41一致的位置上。接着，在半导体构成体4周围的导电性粘接层3的上面，通过例如网板印刷法或旋涂法等，形成绝缘层形成用层15a。绝缘层形成用层15a例如是环氧类树脂等热固化性树脂，或在这种热固化性树脂中混入由硅质填料等构成的加强材料的树脂。
之后，在半导体构成体4和绝缘层形成用层15a的上面配置上层绝缘膜形成用薄片16a。上层绝缘膜形成用薄片16a虽然不是限定含义，但最好是薄片状的增强材料，作为该增强材料，可以使硅质填料混入环氧类树脂等热固化性树脂中，使热固化性树脂变为半固化状态。另外，作为上层绝缘膜形成用薄片16a，也可使用使环氧类树脂等热固化性树脂浸含在玻璃纤维中，将热固化性树脂变为半固化状态而构成薄片状的半固化片材料，或使用不混入硅质填料，仅由热固化性树脂构成的薄片状材料。
接着，如图12所示，使用一对的加热加压板42、43，从上下加热加压绝缘层形成用层15a和上层绝缘膜形成用薄片16a。此时，在半导体构成体4周围的导电性粘接层3的上面形成绝缘层15，在半导体构成体4和绝缘层15的上面形成上层绝缘膜16。此时，上层绝缘膜16的上面由于通过上侧加热加压板42的下面压接，所以变为平坦面。因此，不需要平坦化上层绝缘膜16上面用的研磨工序。
接着，如图13所示，通过照射激光束的激光加工，在对应于柱状电极13上面中央部的部分中的上层绝缘膜16中形成开口部17。另外，如作为图13所示状态中的部分底面图的图14所示，使用机械钻眼，在对应于切割线41和其两侧的区域中，在上层绝缘膜16、绝缘层15、导电性粘接层3、接地层2和底板1的规定部位，形成直径比切割线41的宽度大一些的圆形的贯穿孔26a。即，贯穿孔26a形成为包含底板1和绝缘层15的切割线41，并且向其两侧的区域伸出。之后，必要时，通过消拖尾(desmear表面沾污去除)处理来去除在开口部17内和贯穿孔26a内等产生的环氧污迹等。
之后，如图15所示，在包含经开口部17露出的柱状电极13上面的上层绝缘膜16的整个上面、底板1的整个下面和贯穿孔26a的内壁面中，通过铜的无电解电镀或溅射法，形成上层底部金属层18、下层底部金属层23和底部金属层27a。接着，在上层底部金属层18的上面图案形成电镀抗蚀剂膜44。此时，在对应于上层配线19形成区域的部分中的电镀抗蚀剂膜44中形成有开口部45。
之后，通过将底部金属层18、23、27a作为电镀电流路径进行铜的电解电镀，在电镀抗蚀剂膜44的开口部45内的上层底部金属层18的上面形成上层配线19，另外，在下层底部金属层23的下面形成下层配线24，并且，在贯穿孔26a内的底部金属层27a的表面形成铜层27b。之后，剥离电镀抗蚀剂膜44，然后，将上层配线19作为掩膜蚀刻去除上层底部金属层18的无用部分时，如图16所示，仅在上层配线19下残留上层底部金属层18。另外，在该状态下，在贯穿孔26a内形成具有底部金属层27a和铜层27b的上下导通部27。
接着，如图17所示，通过网板印刷法等，在包含上层配线19的上层绝缘膜16的整个上面，形成由焊料抗蚀剂等构成的上层涂层膜20，另外，在下层配线24的整个下面形成由焊料抗蚀剂等构成的下层涂层膜25。此时，在上下导通部27内形成由焊料抗蚀剂等构成的侧面绝缘膜28。此时，在对应于上层配线19的连接衬垫部的部分中的上层涂层膜20中，形成有开口部21。
接着，在开口部21内和其上方，连接于上层配线19的连接衬垫部形成焊锡孔22。之后，如图18和图19所示，在彼此相邻的半导体构成体4之间的贯穿孔17的表面形状的大致中心位置，沿切割线41，切断上层涂层膜20、上层绝缘膜16、绝缘层15、导电性粘接层3、接地层2、底板1、下层涂层膜25、上下导通部27和侧面绝缘膜28时，得到多个图1所示的半导体装置。此时，上下导通部27的沟26的内壁面连接于底板1和绝缘膜15的侧面形成，形成半导体装置的周围的侧面。
如上所述，在上述制造方法中，在底板1上配置多个半导体构成体4，并对多个半导体构成体4统一进行上层配线24、下层配线24、上下导通部27和焊锡孔22的形成，之后分断而得到多个半导体装置，所以可简化制造工序。另外，在图12所示制造工序以后，由于可与底板1一起搬运多个半导体构成体4，所以也可由此来简化制造工序。
(第2实施方式)
图20表示作为本发明的第2实施方式的半导体装置的截面图。在该半导体装置中，与图1所示情况的不同之处在于图案形成包含下层底部金属层23的下层配线24，设为通常的配线，并在对应于下层配线24的连接衬垫部的部分中的下层涂层膜25中设置开口部51，使由电容器或电阻等构成的芯片零件52经由焊锡等构成的导电材料53连接于下层配线24的连接衬垫部上，装载于下层涂层膜25之下。此时，由于下层配线24是通常的配线，所以连接下层配线24的至少一部分与上层配线19的至少一部分用的上下导通部27的条数是与之对应的条数。
(第3实施方式)
图21表示作为本发明第3实施方式的半导体装置的截面图。在该半导体装置中，与图20所示情况的不同之处在于，不备有接地层2和导电性粘接层3，经由芯片粘合材料构成的粘接层54将半导体构成体4的硅基板5的下面粘接于底板1的上面。
下面，说明该半导体构成体的制造方法的一例的一部分。在经过图8所示工序之后，如图21所示，将粘接层54粘接于硅基板5的整个下面。粘接层54由环氧类树脂、聚酰亚胺类树脂等芯片粘合材料构成。通过加热加压，在半固化状态下固定于硅基板5上。之后，将固定于硅基板5上的粘接层54粘贴于切割带(未图示)上，经过图22所示的切割工序之后，从切割带上剥离时，如图23所示，得到多个在硅基板5的下面具有粘接层54的半导体构成体4。
在如此得到的半导体构成体4中，由于在硅基板5的下面具有粘接层54，所以不需要在切割工序之后在各半导体构成体4的硅基板5的下面分别设置粘接层的极麻烦的作业。另外，在切割工序之后从切割带上剥离的作业与在切割工序之后在各半导体构成体4的硅基板5的下面分别设置粘接层的作业相比，极简单。另外，在将该半导体构成体4配置于底板1上的情况下，通过加热加压，使粘接层54固化。
(其它实施方式)
另外，在上述实施方式中，说明通过激光加工将上下导通部17的贯穿孔26a的平面形成圆形、并由通过圆形大致中心的切断线来切断的情况，但贯穿孔26a的平面形状不限于圆形，也可以是矩形、菱形或不等边多边形。另外，设通过电镀来形成在贯穿孔26a的内壁面形成的导电层，但不限于此，也可以填充导电性胶。
并且，例如图20中，将设置在上层绝缘膜16上的上层配线设为1层，将设置在下层绝缘膜37下的下层配线设为1层，但不限于此，也可以将设置在上层绝缘膜16上的上层配线设为2层以上，另外，将设置在下层绝缘膜37下的下层配线设为2层以上。另外，装载于下层涂层膜25之下的电子零件不限于芯片零件53，例如也可以是裸芯片、CSP等。
另外，在上述实施方式中，作为半导体构成体4，设具有作为外部连接用电极的柱状电极，但不限于此，也可以不具有柱状电极，具有备有作为外部连接用电极的连接衬垫部的配线12，另外，也可以不具有柱状电极和配线，而具有作为外部连接用电极的连接衬垫6。

Claims (19)

1、一种半导体装置，其特征在于：具有
底板(1)；
支撑在所述底板(1)上的至少一层的第1导电层(2、24)；
半导体构成体(4)，其设置在所述底板(1)上，并且，具有半导体基板5和设置在该半导体基板5上的多个外部连接用电极(6、13)；
设置在所述半导体构成体(4)周围的所述底板(1)上的绝缘层(15)；
第2导电层(19)，其连接于所述半导体构成体(4)的外部连接用电极(6、13)，设置在所述半导体构成体(4)和所述绝缘层(15)上；和
上下导通部(27)，其设置在所述绝缘膜(15)和所述底板(1)的侧面，电连接所述第1导电层(2、24)与所述第2导电层(19)。
2、根据权利要求1所述的半导体装置，其特征在于：
所述上下导通部(27)，具有设置在所述绝缘膜(15)和所述底板(1)的侧面中的沟(26)和设置在所述沟(26)内的上下导通层(27a、27b)。
3、根据权利要求2所述的半导体装置，其特征在于：
所述沟(26)的内壁面连接于所述绝缘膜(15)和所述底板(1)的侧面而形成。
4、根据权利要求2所述的半导体装置，其特征在于：
所述沟(26)的内壁面的平面形状是半圆形。
5、根据权利要求1所述的半导体装置，其特征在于：
在所述底板(1)的上面，连接于所述上下导通部(27)设置有接地层(2)。
6、根据权利要求5所述的半导体装置，其特征在于：
所述半导体构成体(4)的半导体基板5经导电性粘接层(3)连接于所述接地层(2)上。
7、根据权利要求1所述的半导体装置，其特征在于：
设置多层所述第2导电层(19)，最上层的所述第2导电层具有连接衬垫部，所述最上层的第2导电层去除所述连接衬垫部的部分后由上层外涂层膜(20)覆盖。
8、根据权利要求7所述的半导体装置，其特征在于：
在所述最上层的第2导电层的所述连接衬垫部上设置有焊锡孔(22)。
9、根据权利要求1所述的半导体装置，其特征在于：
在所述底板(1)的下面，连接于所述上下导通部(27)而设置有接地层(24)。
10、根据权利要求1所述的半导体装置，其特征在于：
在所述底板(1)的下面，设置至少1层第1导电层(24)，所述第1导电层(24)的一部分连接于所述上下导通部(27)。
11、根据权利要求10所述的半导体装置，其特征在于：
设置多层所述第1导电层(24)，最上层的所述第1导电层具有连接衬垫部，所述最下层的第1导电层去除所述连接衬垫部的部分后由下层外涂层膜(25)覆盖。
12、根据权利要求11所述的半导体装置，其特征在于：
在所述下层涂层膜(25)的下面，连接于所述最下层的第1导电层的连接衬垫部设置有电子零件(52)。
13、一种半导体装置的制造方法，其特征在于，具有如下步骤：
在具有第1导电层(2、24)的底板(1)上，使分别具有半导体基板(5)和设置在该半导体基板(5)上的多个外部连接用电极(6、13)的多个半导体构成体(4)彼此离间配置；
在所述半导体构成体(4)周围的所述底板(1)上形成绝缘层(15)；
在所述半导体构成体(4)和所述绝缘层(15)上，连接于所述半导体构成体(4)的所述外部连接用电极(6、13)，形成至少一层第2导电层(19)；
在所述底板(1)的对应于所述绝缘层(15)的区域中，策划切断线(41)，以包含至少一个所述半导体构成体(4)；
形成上下导通部(27)，其包含所述切断线(41)，向其两侧的区域伸出，并且，电连接所述第1导电层(2、24)与所述第2导电层(19)；
沿所述切断线(41)切断所述绝缘层(15)、所述底板(1)和所述上下导通部(27)，得到多个在侧面上具有上下导通部(27)的一部分的半导体装置。
14、根据权利要求13所述的半导体装置的制造方法，其特征在于：
形成所述上下导通部(27)的步骤包含形成贯穿所述绝缘层(15)和所述底板(1)的贯穿孔(26a)、和在所述贯穿孔(26a)内形成上下导通层(27a、27b)。
15、根据权利要求14所述的半导体装置的制造方法，其特征在于：
形成所述贯穿孔(26a)的步骤包含照射激光。
16、根据权利要求13所述的半导体装置的制造方法，其特征在于：
在所述底板(1)上配置所述半导体构成体(4)的步骤，包含在所述底板(1)上设置导电性粘接层(3)、和在所述导电性粘接层(3)上粘接所述半导体构成体(4)的半导体基板5。
17、一种半导体装置的制造方法，其特征在于，具有如下步骤：
使分别具有半导体基板5和设置在该半导体基板5上的多个外部连接用电极(6、13)的多个半导体构成体(4)彼此离间配置在底板(1)上；
在所述半导体构成体(4)周围的所述底板(1)上形成绝缘层(15)；
在所述半导体构成体(4)和所述绝缘层(15)上，连接于所述半导体构成体(4)的所述外部连接用电极(6、13)，形成至少一层第2导电层(19)；
在所述底板(1)上的底面中形成第1导电层(24)；
在所述底板(1)的对应于所述绝缘层(15)的区域中，策划切断线(41)，以包含至少一个所述半导体构成体(4)；
形成上下导通部(27)，其包含所述切断线(41)，向其两侧的区域伸出，并且，电连接所述第1导电层(2、24)与所述第2导电层(19)；
沿所述切断线(41)切断所述绝缘层(15)、所述底板(1)和所述上下导通部(27)，得到多个在侧面上具有上下导通部(27)的一部分的半导体装置。
18、根据权利要求17所述的半导体装置的制造方法，其特征在于：
形成所述上下导通部(27)的步骤，包含形成贯穿所述绝缘层(15)和所述底板(1)的贯穿孔(26a)、和在所述贯穿孔(26a)内形成上下导通层(27a、27b)。
19、根据权利要求18所述的半导体装置的制造方法，其特征在于：
形成所述贯穿孔(26a)的步骤包含照射激光。
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