CN1572718A - 半导体装置及其制造方法 - Google Patents
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Abstract
一种半导体装置及其制造方法,把配置表面形成有MEMS器件11A及其未图示的配线的多个半导体芯片10A而构成的半导体芯片30A,和配置多个密封罩20A的罩阵列晶片40A加以粘接,把MEMS器件11A密封在其空腔CV内。设置多个贯穿半导体晶片30A的通孔13,形成嵌入式电极14,再形成凸点电极15。在上述工序后,沿着划线L把该结构体切断,分割成单个的封装。
Description
技术领域
本发明涉及半导体装置及其制造方法,特别是涉及把被密封器件密封在封装中的半导体装置及其制造方法。
背景技术
近几年来,采用微电子机械系统的器件(下面简称“MEMS器件”)、在图像传感器等中使用的电荷结合元件(下面简称CCD)、电检测红外线的传感器(下面简称“IR传感器”)等正在被开发。
这些电子器件及微小的机械器件(下面简称“电子器件”)被形成在半导体芯片上,被封装化。这种封装,可以举出用密封外壳密封的密封外壳封装、由陶瓷构成的罩加以密封的陶瓷封装等。
另外,相关的参考技术文献,例如可举出下列专利文献。
[专利文献1]特开平11-351959号公报
[专利文献2]特开平11-258055号公报
[专利文献3]特开2001-13156号公报
然而,根据现有封装,形成有电子器件等被密封器件的半导体芯片和,用于将其密封的罩等要分别加以准备,然后将它们加以组装。因此,大量生产时的制造工序烦杂,制造成本相应地增大。另外,封装的尺寸加大,安装在印刷线路板等上时的安装面积增大的问题产生。
发明内容
本发明提供一种半导体装置及其制造方法,可在电子器件等封装化时,使制造工序简化、制造成本下降,同时,可使尺寸小型化。
本发明的半导体装置是鉴于上述课题而开发的,在表面形成有被密封器件的半导体芯片上粘结密封罩,在由半导体芯片和密封罩之间的空间所形成的空腔内封入被密封器件。在这里,被密封器件为MEMS器件、IR传感器、CCD等电子器件或微小的机械器件等。
在半导体芯片上形成有贯穿该芯片的通孔,在该通孔中形成嵌入式电极。嵌入式电极通过配线与被密封器件连接。外部连接用电极连接在嵌入式电极上。
附图说明
图1是本发明第1实施方案的半导体装置平面图及其X-X线剖面图;
图2是本发明第1实施方案的半导体晶片及罩阵列晶片的平面图;
图3是说明本发明第1实施方案的半导体装置的制造方法的剖面图;
图4是本发明第2实施方案的半导体装置的平面图及其Y-Y线剖面图。
具体实施方式
下面,对本发明第1实施方案的半导体装置的结构,参照附图加以说明。
图1(a)是本实施方案的半导体装置的平面图。另外,图1(b)是沿图1的X-X线的剖面图。
在半导体芯片10A(例如,硅芯片)表面的被密封器件形成区域SA(用虚线围起来的区域)中形成有作为被密封器件的多个MEMS器件11A(例如,继电器、电容、线圈、电机等)。这些MEMS器件11A,例如是在半导体芯片10A上实现微型机械等微小机构时的电子及机械构成要素。
另外,连接在这些MEMS器件11A上的配线12(由Cu、Al、Al合金等构成),延伸设置到被密封器件形成区域SA的周边。这些配线12以1μm左右较薄的厚度形成,并由在半导体芯片10A上形成MEMS器件11A的制造工序形成。
另外,在延长至被密封器件形成区域SA的周边而形成的各配线12的端部的正下方形成贯穿半导体芯片10A的多个通孔13。在该通孔13中形成嵌入式电极14(由Cu、Al、Al合金等构成)。在这里,嵌入式电极14通过镀敷法或溅射法等形成,与MEMS器件11A的配线12连接。还有,在图1(b)中,嵌入式电极14完全装填入通孔13内,但通过调节镀敷时间或溅射时间,也可不完全地装填。
另一方面,在半导体芯片10A背面侧的嵌入式电极14上形成有作为外部连接用电极的凸点电极15(由焊料等构成)。由此,不必把封装后的半导体芯片10A的导线从半导体芯片10A的侧面引出,而从底面引出,从而可以实现封装的小型化。因此,可以避免在印刷线路板等上安装时安装面积增大的问题。
在半导体芯片10A的表面上粘接有由玻璃、硅、陶瓷或树脂(例如,塑料)形成的密封罩20A。在这里,使半导体芯片10A的表面和密封罩20A的凹部21A的形成面(密封罩20A的内面)相对,用环氧树脂等粘合剂,把半导体芯片10A和密封罩20A进行粘接。
在半导体芯片10A的表面和密封罩20A的凹部21A之间的空间形成空腔CV。在该空腔CV内封入MEMS器件11A。在这里,密封罩20A的厚度d为数十μm~数百μm左右,空腔CV的高度h为数μm~数十μm,但不限于此。
在上述半导体芯片10A的表面形成的MEMS器件11A在真空状态或填充惰性气体(例如,N2)的状态下密封在空腔CV内。由此,密封的MEMS器件11A通过密封罩20A加以机械保护,同时,由于密封的MEMS器件11A不与大气接触,从而可以防止氧化等引起的腐蚀和老化。因此,可使在半导体芯片10A上形成的MEMS器件11A的寿命及可靠性提高。
还有,当密封罩20A由玻璃或硅构成时,在其凹部21A的形成面上还可以形成具有隔断或透过特定波长光的过滤器功能的金属薄膜(未图示)。此时,由于由金属薄膜形成的过滤器强度弱,故操作时必须注意,但利用形成的空腔CV,在密封罩20A的凹部21A形成面上形成该过滤器,具有操作简便的效果。
其次,对晶片片上形成多个上述半导体芯片10A及密封罩20A的结构,参照附图加以说明。
图2(a)是多个上述半导体芯片10A以矩阵状形成而构成的半导体芯片30A的平面图。
半导体晶片30A由硅等半导体材料形成。多个半导体芯片10A通过在横向及纵向延伸的划线L加以划分,在各半导体芯片10A内的被密封器件形成区域SA内形成有MEMS器件11A。
另外,虽未图示,但在各MEMS器件11A上连接有向被密封器件形成区域SA的周边延伸的配线12(由Cu、Al、Al合金等构成)。
图2(b)是多个上述密封罩20A以矩阵状形成而构成的罩阵列晶片40A的平面图。
罩阵列晶片40A由玻璃、硅、陶瓷或树脂(例如,塑料)形成。通过划线L’划分的各区域是对应于半导体芯片10A的区域。该罩阵列晶片40A的划线L’是假想的,在两者粘接时,与半导体晶片30A的划线L重合。
在对应于半导体芯片10A的被密封器件形成区域SA的区域内形成有凹部21A。在这里,罩阵列晶片40A由玻璃、硅、或陶瓷形成时,凹部21A通过蚀刻等形成。
另一方面,在罩阵列晶片40A由树脂形成时,通过注射成型形成罩阵列晶片40A,并使其具有多个凹部21A。
另外,在上述半导体芯片10A及半导体晶片30A中,是通过配线12,在MEMS器件11A上连接嵌入式电极14及作为外部连接用电极的凸点电极15而形成的,但也可不通过配线12,而将嵌入式电极14和凸点电极15直接连接。这一点,下述的第2实施方案也同样。
其次,对本实施方案的半导体装置的制造方法,参照附图加以说明。
如图3(a)所示,准备其表面形成有MEMS器件11A及其配线12(未图示)的半导体芯片30A。半导体晶片30A的构成与图2(a)所示的同样。
另外,准备具有多个凹部21A的罩阵列晶片40A。罩阵列晶片40A的构成与图2(b)所示的同样。还有,当罩阵列晶片40A由玻璃或硅构成时,可以在其凹部21A的形成面上,形成具有隔断或透过特定波长光的过滤功能的金属薄膜(未图示)。
在这里,把罩阵列晶片40A和半导体芯片30A以罩阵列晶片40A的凹部21A的形成面和半导体芯片30A的表面相对的方式对置。
其次,如图3(b)所示,把罩阵列晶片40A和半导体芯片30A,用环氧树脂等粘合剂粘结。在这里,使罩阵列晶片40A的凹部21A与半导体晶片30A的各被密封器件形成区域SA一致地进行粘接。
即,在罩阵列晶片40A的各凹部21A和半导体芯片30A表面之间的空间形成空腔CV,并在该空腔CV内密封MEMS器件11A。此时,通过在真空中将罩阵列晶片40A和半导体芯片30A的粘接,使空腔CV内形成真空状态。或者,也可以通过在惰性气体(例如,N2)的氛围气中,将罩阵列晶片40A和半导体晶片30A进行粘接,将惰性气体(例如,N2)填充入空腔CV内。
然后,也可以对半导体芯片30A的背面进行背面研磨,使半导体芯片30A的厚度减薄至例如数十μm~数百μm左右。另外,背面研磨可以对罩阵列晶片40A,或半导体晶片30A和罩阵列晶片40A两者实施。
其次,如图30(c)所示,从半导体晶片30A的背面贯穿表面形成多个通孔13。为了形成这些通孔13,可以采用蚀刻或照射激光光束等方法。
而且,在这些通孔13中,采用镀敷法或溅射法形成嵌入式电极14(由Cu、Al、Al合金等构成)。另外,在半导体晶片30A的背面侧的嵌入式电极14上形成凸点电极15(由焊料等形成)。还有,在图3(c)中,凸点电极15在嵌入式电极14正下方形成,但在半导体晶片30A的背面,形成连接在嵌入式电极14的背面配线,在该背面配线上形成凸点电极15也可以。
在上述工序后,用切割刀或激光等沿划线L切断与上述罩阵列晶片40A粘接的半导体晶片30A,将其分割成单个封装。
如上所述,由于多个封装由罩阵列晶片40A及半导体晶片30A同时形成,从而可以简化大量生产时的制造工序。由此,可以削减各封装的制造成本。
在上述实施方案中,被密封器件为MEMS器件11A,但也可以把其他的电子器件(例如,IR传感器)作为被密封器件。
其次,对本发明第2实施方案的半导体装置的构成,参照附图加以说明。
图4(a)是本实施方案的半导体装置的平面图。另外,图4(b)是沿图4的Y-Y线的剖面图。
在半导体芯片10B(例如,硅芯片)表面的被密封器件形成区域SB(用虚线围起来的区域)中,形成有作为被密封器件的CCD11B。这里的CCD11B例如用作图像传感器。另一方面,在与被密封器件形成区域SB相邻的半导体芯片10B上的其他被密封器件形成区域中,形成有用于控制CCD11B的逻辑电路LGC。
另外,CCD11B及与该逻辑电路LGC连接的配线12(由Cu、Al、Al合金等构成),延长形成至被密封器件形成区域SB及逻辑电路LGC周边。这些配线12厚度为1μm左右,由在半导体芯片10B上形成CCD11B及逻辑电路LGC的制造工序形成。
另外,在延长至被密封器件形成区域SB周边的各配线12端部正下方,形成贯穿半导体芯片10B的多个通孔13。在该通孔13中形成嵌入式电极14(由Cu、Al、Al合金等构成)。这里的嵌入式电极14由镀敷法或溅射法形成,与CCD11B及逻辑电路LGC的配线12连接。
另一方面,在半导体芯片10B背面侧的嵌入式电极14上形成凸点电极15(由焊料构成)。由此,封装化的半导体芯片10B的导线不必从半导体芯片10B的侧面引出,而可从底面引出,从而可以实现封装的小型化。因此,可以避免在印刷线路板等上安装时安装面积增大的问题。
然后,在半导体芯片10B的表面上粘接密封罩20B(由玻璃、硅、或树脂构成)。在这里,使半导体芯片10B表面的被密封器件形成区城SB和密封罩20B的凹部21B的形成面相对粘接半导体芯片10B和密封罩20B。
在半导体芯片10B表面的被密封器件形成区城SB和密封罩20B的凹部21B之间的空间形成空腔CV。在该空腔CV内封入CCD11B。这里,上述半导体芯片10B表面形成的CCD11B,在真空状态或填充惰性气体(例如,N2)的状态下密封到空腔CV内。由此,由于密封的CCD11B不与大气接触,从而可以防止氧化等引起的腐蚀和老化。所以,可使在半导体芯片10B上形成的CCD11B的寿命及可靠性提高。
另一方面,在逻辑电路LGC的形成区域上粘接密封罩20B的凸部(未图示),不形成空腔CV。
把CCD11B密封入空腔CV内可防止由于形成密封罩20B和半导体芯片10B的材料膨胀率不同所产生的应力对CCD11B的不良影响。另一方面,可通过在逻辑电路LGC上粘接密封罩20B的凸部,使密封罩20B的粘接面积加大,增大粘接强度。
还有,当密封罩20B由玻璃或硅构成时,在其凹部21B的形成面上还可以形成具有隔断或透过特定波长光的过滤功能的金属薄膜(未图示)。此时,由于金属薄膜构成的过滤器强度弱,故操作时必须注意,但利用形成的空腔CV,在密封罩20B的凹部21B形成面上形成该过滤器,从而具有处理简便的效果。
其次,对上述半导体芯片10B及密封罩20B在晶片30A上形成多个的构成,参照图2(a)及图2(b)加以说明。
本实施方案的半导体芯片10B,与图2(a)中示出的半导体晶片30A相同,由划线L区分,以矩阵状配置多个(未图示)。但是,在由划线L区分的各区域内,在被密封器件形成区域SB(未图示)内形成CCD11B,在与CCD11B相邻的位置,形成控制CCD11B的逻辑电路LGC(未图示)。在这里,在各CCD11B及逻辑电路LGC连接有向被密封器件形成区域SB及逻辑电路LGC形成区域的周边延伸的配线12(未图示)。
本实施方案的半导体芯片20B与图2(b)所示的罩阵列晶片40A同样,通过假想的划线L’加以区分,以矩阵状配置多个(未图示)。但是,在通过划线L’加以区分的各区域中,仅在对应于半导体芯片10B的被密封器件形成区域SB(未图示)的区域内,形成凹部21B(未图示)。
凹部21B与第1实施方案相同,在本实施方案中的罩阵列晶片由玻璃或硅形成时,通过蚀刻形成,当罩阵列晶片由树脂形成时,在其注射成型时同时形成。
上述本实施方案中的半导体晶片及罩阵列晶片,经过与第1实施方案示出的制造方法同样的工序,最终分割成单个的封装。
还有,在上述实施方案中,被密封器件为CCD11B,但也可把其他电子器件作为被密封器件。
按照本发明,经过在晶片上形成、粘结多个半导体装置的密封罩和半导体芯片,然后,分割成多个封装的工序,可简化大量生产时的制造工序。由此,可以削减各封装的制造成本。
另外,通过设置贯穿各封装的半导体芯片的通孔,并形成嵌入式电极,可在其底面上形成凸点电极。由此,使封装小型化成为可能,可以减少在印刷线路板等上安装时的安装面积。
另外,通过使密封被密封器件的空腔形成真空或填充惰性气体的状态,可以提高被密封器件的寿命及可靠性等。
Claims (18)
1、一种半导体装置,其特征在于,包括:半导体芯片,其表面形成有被密封器件;密封罩,其粘接在该半导体芯片表面上、将上述被密封器件密封在其与上述半导体芯片之间的空间所形成的空腔内。
2、按照权利要求1所述的半导体装置,其特征在于,所述密封罩是由玻璃、硅、陶瓷、或树脂的任何一种构成的。
3、按照权利要求1或2所述的半导体装置,其特征在于,所述被密封器件是MEMS器件。
4、按照权利要求1或2所述的半导体装置,其特征在于,所述被密封器件是红外线传感器。
5、按照权利要求1或2所述的半导体装置,其特征在于,所述被密封器件是CCD。
6、按照权利要求5所述的半导体装置,其特征在于,在上述半导体芯片表面上所述空腔外的区域,形成控制上述CCD的逻辑电路,在该区域上粘接上述密封罩的凸部。
7、按照权利要求1、2、6任一项所述的半导体装置,其特征在于,上述空腔内为真空。
8、按照权利要求1、2、6任一项所述的半导体装置,其特征在于,上述空腔内填充有惰性气体。
9、按照权利要求1、2、6任一项所述的半导体装置,其特征在于,在上述密封罩的内侧形成具有隔断或透过特定波长光的过滤器功能的金属薄膜。
10、按照权利要求1所述的半导体装置,其特征在于,具有:在贯穿上述半导体芯片的通孔中形成的嵌入式电极;连接该嵌入式电极和上述被密封器件的配线。
11、一种半导体装置的制造方法,其特征在于,其包括:准备配置多个表面上形成有被密封器件、用划线加以区分的半导体芯片构成的半导体晶片;和配置多个形成有凹部的密封罩而构成的罩阵列晶片,
通过把上述罩阵列晶片和上述半导体芯片表面加以粘接,由上述罩阵列晶片的凹部和上述半导体晶片表面之间的空间形成空腔,并将上述被密封器件密封在该空腔内的工序;
沿着划线,把上述半导体晶片及上述罩阵列晶片切断,分割成单个封装的工序。
12、按照权利要求11所述的半导体装置的制造方法,其特征在于,使所述空腔内形成真空状态。
13、按照权利要求11所述的半导体装置的制造方法,其特征在于,在所述空腔内填充情性气体。
14、按照权利要求11、12、13任一项所述的半导体装置的制造方法,其特征在于,在上述罩阵列晶片的凹部内面上形成具有隔断或透过特定波长光的过滤器功能的金属薄膜。
15、按照权利要求11所述的半导体装置的制造方法,其特征在于,具有:在上述半导体芯片上形成通孔的工序;在上述通孔内形成嵌入式电极的工序;形成连接上述嵌入式电极和上述被密封器件的配线的工序。
16、按照权利要求11所述的半导体装置的制造方法,其特征在于,具有在将上述罩阵列晶片和上述半导体晶片表面粘接的工序后,对该半导体晶片进行背面研磨的工序。
17、按照权利要求11所述的半导体装置的制造方法,其特征在于,具有在将上述罩阵列晶片和上述半导体晶片表面粘接的工序后,对所述罩阵列晶片进行背面研磨的工序。
18、按照权利要求11所述的半导体装置的制造方法,其特征在于,具有在将上述罩阵列晶片和上述半导体芯片表面粘接的工序后,对上述半导体晶片和上述罩阵列晶片两者进行背面研磨的工序。
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- 2004-06-02 EP EP04013033A patent/EP1484796A3/en not_active Withdrawn
- 2004-06-04 KR KR1020040040618A patent/KR100636762B1/ko not_active IP Right Cessation
- 2004-06-07 CN CNA2004100492676A patent/CN1572718A/zh active Pending
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CN100494046C (zh) * | 2006-03-10 | 2009-06-03 | 中国科学院上海微系统与信息技术研究所 | 凸点连接气密封装微机械系统器件的结构及制作方法 |
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CN102738013A (zh) * | 2011-04-13 | 2012-10-17 | 精材科技股份有限公司 | 晶片封装体及其制作方法 |
CN102738013B (zh) * | 2011-04-13 | 2016-04-20 | 精材科技股份有限公司 | 晶片封装体及其制作方法 |
CN106206527A (zh) * | 2015-05-25 | 2016-12-07 | 华亚科技股份有限公司 | 半导体组件及其制造方法 |
CN106206527B (zh) * | 2015-05-25 | 2019-08-13 | 美光科技公司 | 半导体组件及其制造方法 |
Also Published As
Publication number | Publication date |
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EP1484796A3 (en) | 2008-03-12 |
US20070096294A1 (en) | 2007-05-03 |
KR20040108601A (ko) | 2004-12-24 |
TWI275168B (en) | 2007-03-01 |
TW200500595A (en) | 2005-01-01 |
KR100636762B1 (ko) | 2006-10-20 |
US20050012169A1 (en) | 2005-01-20 |
US7154173B2 (en) | 2006-12-26 |
EP1484796A2 (en) | 2004-12-08 |
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