CN1534750A - 连接垫及其制造方法 - Google Patents
连接垫及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 238000000034 method Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000005611 electricity Effects 0.000 claims description 13
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 13
- 239000002002 slurry Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 230000010415 tropism Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 28
- 239000004065 semiconductor Substances 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 6
- 241000218202 Coptis Species 0.000 description 5
- 235000002991 Coptis groenlandica Nutrition 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000010009 beating Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明涉及一种连接垫及其制造方法,适用于一金属导线结构,该连接垫结构通过下列方法制成:首先于上述金属导线结构表面交替形成至少一第一钝态护层及一第二钝态护层;其次,以微影及蚀刻制程定义上述第二钝态护层及上述第一钝态护层,形成露出上述衬垫层表面的一连接垫开口部,其中上述连接垫开口部的侧壁具有连续凹凸表面;最后,于上述连接垫开口部内形成一金属连接垫以电性连接上述金属导线结构,其中上述金属连接垫嵌合于上述连接垫开口部侧壁的连续凹凸表面。利用形成不同蚀刻速率(性质)的钝态护层,以增加钝态护层与连接垫间的接合力,防止连接垫的剥落。
Description
技术领域
本发明涉及半导体领域,更确切地说,涉及一种利用不同蚀刻速率(性质)的钝态护层以形成接合佳的连接垫结构及其制造方法。
背景技术
在半导体制程中,当各种半导体组件已经制备完成之后,会在半导体基底的表面上覆盖保护层,用来防止半导体组件遭受到污染、刮伤与湿气的影响。后续则会利用微影与蚀刻制程于保护层上定义形成一开口,以使设置于保护层底部的金属层表面曝露出来,用来作为一连接垫(bonding pad),使半导体组件得以与外界基板形成电连接。
请参考图1A至1D,其为显示连接垫的制作方法的示意图。如图1A所示,提供一半导体基底10,其包含有制备完成的半导体组件(图中未显示),此半导体基底10尚具有一金属导线结构12及一衬垫层16,而金属导线结构12是在绝缘层14中形成。
接着,仍请参见图1A,于衬垫层16上形成一钝态护层18及一硬罩幕层20。钝态护层18是以低压化学气相沉积或电浆促进化学气相沉积形成未掺杂硅玻璃(USG)层。硬罩幕层20是以低压化学气相沉积或电浆促进化学气相沉积形成氮化硅层。
然后,请参阅图1B,藉由图案定义制程以蚀刻硬罩幕层20及钝态护层18以形成一连接垫的开口22,是利用等向性湿蚀刻制程或非等向性干蚀刻对上述硬罩幕层20及钝态护层18进行回蚀刻。
其次,请参阅图1C,经由连接垫开口22蚀刻衬垫层16至金属导线结构12为止。
再者,请参阅图1D,于连接垫开口22内形成一金属连接垫24,是使用物理或化学气相沉积法性形成一铝连接垫26。而当在后续的制程电镀一金属凸块28及封装打金线30时,由于铝连接垫26与钝态护层18之间的接合力不足易造成连接垫的剥落,如图1E所示。
因此,为了改善连接垫的附着力,以防止封装打金线时造成连接垫的剥落,而影响产品的可靠性,亟待针对上述问题谋求改善之道。
发明内容
本发明的目的在于提供一种连接垫结构及其制造方法,其利用形成不同蚀刻速率(性质)的钝态护层,以增加钝态护层与连接垫间的接合力,防止连接垫的剥落。
为达成上述目的,本发明提出一种连接垫的制造方法,适用于一金属导线结构,包括下列步骤:
于该金属导线结构表面交替形成至少一第一钝态护层及一第二钝态护层;
以微影及蚀刻制程定义该第二钝态护层及该第一钝态护层,形成露出该衬垫层表面的一连接垫开口部,其中该连接垫开口部的侧壁具有连续凹凸表面;以及
于该连接垫开口部内形成一金属连接垫以电性连接该金属导线结构,其中该金属连接垫嵌合于该连接垫开口部侧壁的连续凹凸表面。
所述的连接垫的制造方法,该连接垫由铝构成。
所述的连接垫的制造方法,该第一钝态护层是以低压化学气相沉积或电浆促进化学气相沉积形成未掺杂硅玻璃(USG)层。
所述的连接垫的制造方法,该第二钝态护层是以低压化学气相沉积或电浆促进化学气相沉积形成氮化硅层。
所述的连接垫的制造方法,该第二钝态护层是以低压化学气相沉积或电浆促进化学气相沉积形成氮氧化硅层。
所述的连接垫的制造方法,蚀刻该等钝态护层,是利用等向性湿蚀刻制程对该等钝态护层进行回蚀刻。
所述的连接垫的制造方法,蚀刻该等钝态护层,是利用等向性干蚀刻制程对该等钝态护层进行回蚀刻。
所述的连接垫的制造方法,蚀刻该等钝态护层,是以等向性反应离子蚀刻使用氟基化合物作为蚀刻剂使得该第一钝态护层对于该第二钝态护层的被蚀刻速率的比率为1∶2至1∶50。
所述的连接垫的制造方法,蚀刻该硬罩幕层、该第二钝态护层及该第一钝态护层以形成该连接垫的开口部的步骤,更包括先使用非等向性蚀刻制程以形成该连接垫开口部,再使用等向性蚀刻制程蚀刻该连接垫开口部的侧壁使其成为连续凹凸表面。
一种连接垫结构,适用于一金属导线结构,其特征在于包括:交替形成的至少一第一钝态护层及一第二钝态护层,位于上述金属导线结构表面;一连接垫开口部,形成于上述第二钝态护层及上述第一钝态护层中以露出上述金属导线结构表面,其中上述连接垫开口部的侧壁具有连续凹凸表面;以及一金属连接垫,形成于上述连接垫开口部内以电性连接上述金属导线结构,其中上述金属连接垫嵌合于上述连接垫开口部侧壁之连续凹凸表面。
本发明利用沉积不同蚀刻速率(性质)的钝态护层而于钝态护层中的连接垫开口部的侧壁形成连续凹凸表面以增加后续形成的连接垫的接合力,防止封装打金线时造成连接垫的剥落,而影响产品的可靠性。
附图说明
图1A至1D显示习知的形成连接垫的制程剖面图。
图1E显示习知连接垫在封装打金线时剥落的示意图。
图2A至2D显示本发明实施例的连接垫的制造方法的制程剖面图。
10、100-半导体基底
12、102-金属导线结构
14、104-绝缘层
16、106-衬垫层
18、108、110、112-钝态护层
20、113-硬罩幕层
22、114-开口
24、116-金属连接垫
具体实施方式
为使本发明的目的、特征和优点能更明显易懂,下文特举出较佳实施例,并配合附图,作详细说明如下:
请参考图2A至2D,其为显示本发明连接垫的制造方法的制程剖面图。
首先提供一半导体基底100,此半导体基底100具有一金属导线结构102及一可选择性形成的衬垫层106,如图2A所示,半导体基底100包含有制备完成的半导体组件(图中未显示),此半导体组件为晶体管、二极管或其它任何习知的半导体组件(但未详示于图中,以简化该图示及其后的说明)。金属导线结构102是在绝缘层104中形成,绝缘层104例如是氧化物层,金属导线结构102例如是双镶嵌铜结构。衬垫层106例如是氮化硅层。
接着,仍请参见图2A,于衬垫层106上交替形成一第一钝态护层108、一第二钝态护层110及一第三钝态护层112。为了说明方便,本实施例的多层钝态护层结构以3层钝态护层结构来举例说明。所述钝态护层结构的层数可为2层以上,并无一定的限制,其中第一钝态护层108是与第三钝态护层112为相同材料的薄膜层,例如是以低压化学气相沉积或电浆促进化学气相沉积形成未掺杂硅玻璃(USG)层。其中第二钝态护层110的蚀刻速率(性质)是与第一钝态护层108有显著不同,例如是以低压化学气相沉积或电浆促进化学气相沉积形成氮化硅层或氮氧化硅层。再者,可选择性地于该第三钝态护层112上形成一硬罩幕层113,例如是以低压化学气相沉积或电浆促进化学气相沉积形成氮化硅层。
然后,请参阅图2B,藉由图案定义制程以蚀刻硬罩幕层113、第三钝态护层112、第二钝态护层110及第一钝态护层108以形成一连接垫的开口部114。例如,先使用非等向性蚀刻制程形成连接垫的开口部114,再使用等向性蚀刻制程蚀刻连接垫开口部114的侧壁使其成为连续凹凸表面,此乃由于上述钝态护层间的蚀刻速率(性质)有显著差异,所以连接垫开口部114的侧壁为连续凹凸表面。蚀刻上述钝态护层,例如利用等向性湿蚀刻制程或等向性干蚀刻对上述钝态护层进行回蚀刻。蚀刻上述钝态护层,又例如是以等向性反应离子蚀刻使用氟基化合物作为蚀刻剂使得第一钝态护层108及第三钝态护层112对于第二钝态护层110的被蚀刻速率的比率为1∶2至1∶50。
其次,请参阅图2C,经由连接垫开口部114蚀刻衬垫层106至以露出该金属导线结构102表面。例如利用等向性湿蚀刻制程或等向性干蚀刻对衬垫层106进行回蚀刻。
最后,请参见图2D,于连接垫开口部114内形成一金属连接垫116以电性连接金属导线结构102,其中金属连接垫116嵌合于连接垫开口部114侧壁的连续凹凸表面。金属连接垫116例如使用物理或化学气相沉积法形成一铝连接垫116。
本发明另涉及一种连接垫结构,如图2D所示,适用于一位于半导体基底100上的金属导线结构102,此连接垫结构具有以下组件。第一组件为交替形成的第一钝态护层108、一第二钝态护层110及一第三钝态护层112,位于金属导线结构102表面。为了说明方便,本实施例的多层钝态护层结构以3层钝态护层结构来举例说明。此钝态护层结构的层数可为2层以上,并无一定的限制,其中第一钝态护层108是与第三钝态护层112为相同材料的薄膜层,例如是以低压化学气相沉积或电浆促进化学气相沉积形成未掺杂硅玻璃(USG)层。其中第二钝态护层110的蚀刻速率(性质)是与第一钝态护层108有显著不同,例如是以低压化学气相沉积或电浆促进化学气相沉积形成氮化硅层或氮氧化硅层。
第二组件为一连接垫开口部114,形成于第一钝态护层108、一第二钝态护层110及一第三钝态护层112中以露出金属导线结构102表面,其中连接垫开口部114的侧壁具有连续凹凸表面。
第三组件为一金属连接垫116,形成于连接垫开口部114内以电性连接金属导线结构102,其中金属连接垫116嵌合于连接垫开口部114侧壁的连续凹凸表面。金属连接垫116例如使用物理或化学气相沉积法形成一铝连接垫116。
本发明实施例利用沉积不同蚀刻速率(性质)的钝态护层而于钝态护层中的连接垫开口部的侧壁形成连续凹凸表面以增加后续形成的连接垫的接合力,防止封装打金线时造成连接垫的剥落,而影响产品的可靠性。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此项技艺者,在不脱离本发明的精神和范围内,当可作更动与润饰,因此本发明的保护范围当以权利要求书所界定的范围为准。
Claims (10)
1.一种连接垫的制造方法,适用于一金属导线结构,其特征在于包括下列步骤:
于该金属导线结构表面交替形成至少一第一钝态护层及一第二钝态护层;
以微影及蚀刻制程定义该第二钝态护层及该第一钝态护层,形成露出该衬垫层表面的一连接垫开口部,其中该连接垫开口部的侧壁具有连续凹凸表面;以及
于该连接垫开口部内形成一金属连接垫以电性连接该金属导线结构,其中该金属连接垫嵌合于该连接垫开口部侧壁的连续凹凸表面。
2.根据权利要求1所述的连接垫的制造方法,其特征在于,该连接垫由铝构成。
3.根据权利要求1所述的连接垫的制造方法,其特征在于,该第一钝态护层是以低压化学气相沉积或电浆促进化学气相沉积形成未掺杂硅玻璃(USG)层。
4.根据权利要求1所述的连接垫的制造方法,其特征在于,该第二钝态护层是以低压化学气相沉积或电浆促进化学气相沉积形成氮化硅层。
5.根据权利要求1所述的连接垫的制造方法,其特征在于,该第二钝态护层是以低压化学气相沉积或电浆促进化学气相沉积形成氮氧化硅层。
6.根据权利要求1所述的连接垫的制造方法,其特征在于,蚀刻该等钝态护层,是利用等向性湿蚀刻制程对该等钝态护层进行回蚀刻。
7.根据权利要求1所述的连接垫的制造方法,其特征在于,蚀刻该等钝态护层,是利用等向性干蚀刻制程对该等钝态护层进行回蚀刻。
8.根据权利要求1所述的连接垫的制造方法,其特征在于,蚀刻该等钝态护层,是以等向性反应离子蚀刻使用氟基化合物作为蚀刻剂使得该第一钝态护层对于该第二钝态护层的被蚀刻速率的比率为1∶2至1∶50。
9.根据权利要求1所述的连接垫的制造方法,其特征在于,蚀刻该硬罩幕层、该第二钝态护层及该第一钝态护层以形成该连接垫的开口部的步骤,更包括先使用非等向性蚀刻制程以形成该连接垫开口部,再使用等向性蚀刻制程蚀刻该连接垫开口部的侧壁使其成为连续凹凸表面。
10.一种连接垫结构,适用于一金属导线结构,其特征在于包括:交替形成的至少一第一钝态护层及一第二钝态护层,位于上述金属导线结构表面;一连接垫开口部,形成于上述第二钝态护层及上述第一钝态护层中以露出上述金属导线结构表面,其中上述连接垫开口部的侧壁具有连续凹凸表面;以及一金属连接垫,形成于上述连接垫开口部内以电性连接上述金属导线结构,其中上述金属连接垫嵌合于上述连接垫开口部侧壁之连续凹凸表面。
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US7023090B2 (en) * | 2003-01-29 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding pad and via structure design |
US6806138B1 (en) * | 2004-01-21 | 2004-10-19 | International Business Machines Corporation | Integration scheme for enhancing capacitance of trench capacitors |
-
2003
- 2003-04-01 US US10/405,593 patent/US7247939B2/en not_active Expired - Fee Related
- 2003-07-31 TW TW092120943A patent/TWI225685B/zh not_active IP Right Cessation
-
2004
- 2004-03-30 CN CNU2004200478424U patent/CN2710163Y/zh not_active Expired - Lifetime
- 2004-03-30 CN CNB2004100296952A patent/CN1288732C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI552353B (zh) * | 2014-12-15 | 2016-10-01 | 旺宏電子股份有限公司 | 半導體元件及其製造方法 |
US9449915B2 (en) | 2014-12-24 | 2016-09-20 | Macronix International Co., Ltd. | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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TW200421541A (en) | 2004-10-16 |
US7247939B2 (en) | 2007-07-24 |
US20040198057A1 (en) | 2004-10-07 |
CN1288732C (zh) | 2006-12-06 |
TWI225685B (en) | 2004-12-21 |
CN2710163Y (zh) | 2005-07-13 |
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