CN1200564A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN1200564A
CN1200564A CN98108918A CN98108918A CN1200564A CN 1200564 A CN1200564 A CN 1200564A CN 98108918 A CN98108918 A CN 98108918A CN 98108918 A CN98108918 A CN 98108918A CN 1200564 A CN1200564 A CN 1200564A
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semiconductor device
manufacture method
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wiring layer
aluminium
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小田典明
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Abstract

提供一种制造半导体器件的制造方法,所说器件包括层间绝缘膜,层间绝缘膜是形成在半导体衬底上的氧化膜或由BPSG构成的膜。其中,用腐蚀气体选择腐蚀形成在层间绝缘膜上的铝布线层。然后,将通过选择腐蚀所暴露的层间绝缘膜的表面进行表面改造。此后用CVD方法或其它方法形成氟化非晶碳层。根据改造表面的一个方法,在选择腐蚀铝布线层以后,将腐蚀气体改为含CF4的气体,以在层间绝缘膜的表面进行等离子体处理。根据改造表面的另一个方法,在形成氟化非晶碳之前,在层间绝缘膜的表面进行硅离子注入。由于这种改造,可以保持氟化非晶碳与层间绝缘膜之间的粘附性。

Description

半导体器件的制造方法
本发明涉及制造半导体器件的制造方法,该器件使用含非晶碳化氟的膜作为布线时的层间绝缘膜。本申请基于日本专利申请平9-150408,此处引入其内容作为参考。
最近,在提高半导体器件的集成度的同时,要求其具有减小的尺寸和高速性能。因此,根据规定的设计规则(此后,简单称为0.25μm设计规则),要在硅衬底上形成尺寸小于0.25μm的部件。
为了实现半导体器件的小尺寸和高速性能,除了部件尺寸自身的精细结构之外,重要的是使用连接各部件的多层布线结构。为了实现布线的多层结构,需要用绝缘膜在布线之间提供隔离。
由于部件尺寸为精细结构,为了实现半导体器件的小尺寸化,布线尺寸和布线之间的间隔距离也应为精细结构。例如,在为目前制造提供最精细结构的0.35μm设计规则情况下,布线间距约为1.5μm。在“下一代”0.25μm设计规则情况下,布线间距在0.8μm到1.0μm之间,而在0.18μm设计规则情况下,需要的布线间距约在0.4μm到0.6μm之间。
由于布线尺寸和布线之间的间隔距离变小,所以布线电容变大。由此而来的问题(或缺点)是工作速度和电路的功耗变大。为解决此问题,对于布线的层间材料,需要使用比对应于氧化膜的常规材料有更低介电常数(电容率)的材料。
对于这种低电容率膜的候选材料,可以用碳和氟(此后称为“氟化非晶碳”)构成的绝缘膜。例如,日本专利特许公开5-74960(用“文章1”表示)公开了用上述有低介电常数的绝缘膜来制造半导体器件的常规制造方法的实例,所说低介电常数约为2.5。
下面参照图4A、图4B和图4C说明半导体器件的上述常规制造方法(此后简称为“常规实例1”)。
图4A、图4B和图4C是表示常规实例1的制造工艺顺序的工艺剖面图。
首先,如图4A所示,在硅衬底401上形成膜厚为1μm的由铝构成的第一布线层416。
接着,如图4B所示,常规实例1进行用C2F4作为源气体的等离子体聚合,以淀积氟化非晶碳材料408,形成1μm厚的层。在流量为250sccm、压力为0.1Torr、功率为300W、时间为10分钟的条件下完成上述等离子体聚合。
然后,如图4C所示,常规实例1进行光刻方法,以在氟化非晶碳层408中形成VIA孔409,同时用铝形成将要构图的第二布线层420。在上述条件下,形成介电常数为2.4的氟化非晶碳408。
但是,根据上述半导体器件的常规制造方法,在氧化膜上形成氟化非晶碳层时,问题是粘附性不够好,所以层容易剥落。上述文章1没有提供解决该问题的说明。文章1仅仅说明了在硅衬底上形成氟化非晶碳的实例。
本发明的目的是改进形成在氧化膜上的氟化非晶碳的粘附性,后面将作说明。换句话说,本发明提出一种半导体器件的新的制造方法,通过在铝腐蚀时,改造作为底层的氧化膜的表面来实现上述目的。
下面说明设计用来实现改造氧化膜表面的常规实例。
首先,日本专利特许公开2-278731(用“文章2”表示)公开了半导体器件常规制造方法的一个实例(此后称为“常规实例2”),所提供的方法包括下面步骤:
进行干法刻蚀以对Al膜进行构图,形成Al布线。构图后,用干法刻蚀方法或湿法腐蚀方法清洗Al膜表面。这样可以避免由于Al膜表面存在的残余气体离子而导致VIA孔处接触电阻的增加。
下面参照工艺剖面图5A到图5E来说明上述常规实例2的内容。
首先,如图5A所示,在半导体衬底501上先后形成铝504(对应第一布线层)和硅膜511(用来抗反射)。
接着,如图5B所示,用光刻胶506覆盖图5A所示的半导体器件,并用掩模选择曝光。用铝的腐蚀气体,选择腐蚀硅膜511和铝部分504。
然后,如图5C所示,剥落光刻胶506。然后,用硅膜的腐蚀气体进行腐蚀,去除硅膜511。
如图5D所示,残余气体离子513残留在铝504上。所以用Ar等惰性气体514进行等离子体腐蚀方法,去除残余气体离子513。
接着,如图5E所示,进行等离子体CVD方法(这里“CVD”为“化学汽相淀积”的简写),形成SiNx膜515。另外,在SiNx膜515中形成VIA孔509。再后,在SiNx膜515上用铝形成第二布线层516,使之与VIA孔509接触。
下面说明日本专利特许公开63-287036(用“文章3”表示)公开的半导体器件的制造方法的另一个实例(此后称为“常规实例3”),下面参照工艺剖面图6A到图6D来说明常规实例3的内容。
如图6A所示,在半导体衬底601上先后形成第一层间绝缘膜602、铝604(对应第一布线层)和抗反射硅膜611。用光刻工艺和反应离子刻蚀,选择腐蚀硅膜611和铝604。
接着,如图6B所示,通过腐蚀去除硅膜611。然后,如图6C所示,在铝604上和作为背底(或衬底)的第一层间绝缘膜602的表面进行用氢气的RF溅射腐蚀工艺。
然后,如图6D所示,常规实例3进行第二层间绝缘膜618的淀积。在第二层间绝缘膜618中形成VIA孔609。然后,通过选择腐蚀在第二层间绝缘膜618上形成铝604A作为第二布线层,使之与VIA孔609接触。顺便提及,腐蚀反应产物粘附到作为淀积基底的铝膜的表面。所以在淀积第二层间绝缘膜618之前,常规实例3通过腐蚀来去除腐蚀反应产物。这样可以强化形成在铝膜上的层间绝缘膜的粘附性。
常规制造方法的目的只是改进形成在铝布线上的层间绝缘膜的粘附性。但是这些方法的设计不仅仅考虑层间膜之间的粘附性。此外,常规制造方法在氧化膜上形成氟化非晶碳时没有效果。
在使用非晶碳的层间层的形成方法中,非晶碳直接粘附到氧化膜上,这样形成的非晶碳层没有好的粘附性,容易剥落,这是常规方法不能解决的问题。
因此本发明的目的是提供一种半导体器件的制造方法,它能改进直接粘附到氧化膜上的氟化非晶碳的粘附性的缺陷。
本发明的另一个目的是提供一种制造方法,它能通过降低布线的开路失效和短路失效,以很好的成品率制造半导体器件。
本发明的制造方法用来制造一种半导体器件,这种器件包含层间绝缘膜,该层间绝缘膜即形成在半导体衬底上的氧化膜或由BPSG构成的膜。
首先,用针对形成在层间绝缘膜上的铝布线层的腐蚀气体进行选择腐蚀。然后将用选择腐蚀所暴露的层间绝缘膜的表面进行改造。再后,用CVD方法或其它方法形成氟化非晶碳层。
根据改造表面的一个方法,在选择腐蚀铝布线层以后,将腐蚀气体改为含CF4的气体,以在层间绝缘膜的表面进行等离子体处理。根据改造表面的另一个方法,在形成氟化非晶碳之前,在层间绝缘膜的表面进行硅离子注入。
由于这种改造,可以保持氟化非晶碳与层间绝缘膜之间的粘附性。所以可以降低布线开路和短路失效的出现。
参照附图及下面的说明将更加明白本发明的这些和其它目的。
图1A、图1B、图1C、图1D和图1E是一些工艺剖面图,表示根据本发明例1的制造方法所制造的半导体器件的剖面;
图2是表示比较本发明的实例与常规实例在晶片的氟化非晶碳上发生剥落的点的数目的曲线图;
图3是表示根据本发明例2制造方法所制造的半导体器件的剖面的剖面图;
图4A、图4B、和图4C是一些工艺剖面图,表示根据常规例1制造方法所制造的半导体器件的剖面;
图5A、图5B、图5C、图5D和图5E是一些工艺剖面图,表示根据常规例2制造方法所制造的半导体器件的剖面;
图6A、图6B、图6C、和图6D是一些工艺剖面图,表示根据常规例3制造方法所制造的半导体器件的剖面;
借助本发明实施例说明的半导体器件的制造方法主要由下面工艺构成:
选择腐蚀铝布线。然后,将形成在铝布线下面的氧化膜的表面进行改造。本发明实施例从形成氟化非晶碳开始。
关于改造氧化膜表面的方法,提供下面两种:
第一个方法是:在腐蚀铝后,在氧化膜表面上用含CF4的气体进行等离子体处理。第二个方法是:在形成氟化非晶碳之前进行离子注入。
根据本发明的实施例,将半导体器件的制造方法设计成可以,使得在腐蚀铝布线后,在置于铝布线下面的氧化膜的表面上进行表面改造。这样可以保持氧化膜与氟化非晶碳之间的粘附性。此外,可以避免出现布线的开路失效和短路失效,这些失效发生于置于氟化非晶碳上面的布线和层间膜剥落时。
下面说明本发明例1的半导体器件的制造方法。
图1A到图1E是一些工艺剖面图,表示根据本发明例1制造方法所制造的半导体器件的剖面。
图1A表示要进行本发明例1的制造方法的半导体的剖面。其中,在半导体衬底1上形成约800nm厚的第一层间绝缘膜2。第一层间绝缘膜2由一些如BPSG(简称为“硼磷硅玻璃”)等材料构成。形成接触孔(未示出)的开口后,用溅射方法等在第一层间绝缘膜2上先后形成第一阻挡金属层3、第一铝层4、和第一氮化钛层5。这里,第一铝层4用作第一布线层,而第一氮化钛层5用作后面要进行的光刻工艺的抗反射层。然后用光刻胶6覆盖第一氮化钛层5。用普通的光刻工艺,将光刻胶6构图。此后,例如用Cl2和N2的混合气体(混合比例约在4∶1与5∶1之间),将空气压力设置为约10mTorr,RF功率约100W,在此条件下选择腐蚀第一氮化钛层5、第一铝层4和第一阻挡金属层3。
接着将上述腐蚀气体改为CF4,腐蚀图1A所示的半导体,形成图1B所示的半导体。完成第一阻挡金属层3的腐蚀后,暴露出第一层间绝缘膜2。接着,如图1C所示,在第一层间绝缘膜2的表面上形成多孔损伤层7。这里,在CF4流量为20sccm、RF功率为500W、气体压力为20mTorr的条件下用CF4进行等离子体处理。
然后,如图1D所示,用O2等离子体剥落光刻胶6;然后用等离子体CVD方法形成氟化非晶碳层8。
接着根据下面步骤制造图1E所示的半导体器件:
选择性开出VIA孔9。然后用溅射方法形成第二阻挡金属层3B,使得VIA孔9的内壁被第二阻挡金属3B覆盖。在VIA孔9中掩埋钨17。用溅射方法或其它方法形成第二铝层4B和第二氮化钛层5B,以覆盖半导体的整个表面。这里,第二铝层4B对应第二布线层,而第二氮化钛层5B用作抗反射。然后,用光刻方法和反应离子刻蚀,将先后形成在半导体上的第二氮化钛层5B、第二铝层4B和第二阻挡金属3B构图。此后,形成由氮化硅膜或其它膜构成的覆盖膜10,以全部覆盖上述半导体。
接着,参照图2说明半导体器件的例1的效果。图2表示在一个6英寸晶片上出现剥落的剥落点数目,其中将本发明的实例与常规实例比较。从图2看出,本发明的例1明显优于常规实例。
在常规实例中,晶片的氟化非晶碳上发生剥落的点的数大于“100”。相反,本发明例1的剥落点数几乎为零。
下面参照图3说明本发明的实例2。图3是表示根据本发明例2制造方法所制造的半导体器件的剖面的剖面图。具体地,图3所示的剖面对应根据本发明实例1的制造方法所制造的半导体器件的工艺剖面图的上述图1B的剖面。除了形成多孔损伤层外,实例2的制造方法大致与上述实例1的方法相同。为此,除了图3以外的其它解释实例2的附图都省略。
在实例2中,通过注入硅离子23在第一层间绝缘膜2的表面形成损伤层。这里,用20keV到100keV的能量、和1E16(=1×1016)cm-2到1E17(=1×1017)cm-2的剂量,在此条件下进行Si离子23的注入。
根据形成上述损伤层的方法,可以在第一层间绝缘膜2的表面形成损伤层,该层间绝缘膜2为BPSG等构成的氧化膜等绝缘膜。另外,可以在第一层间绝缘膜的表面上形成含大量硅的区域。该区域能容易地与氟化非晶碳8连接。由此可以进一步改进半导体器件的膜或层之间的粘附性。
如图2所示,在6英寸的晶片上,实例2的剥落点几乎为零。
简单地说,将本发明的实例设计成在铝布线腐蚀后,使置于铝布线层下面的氧化膜的表面制成为多孔。
这样本发明有下面效果:
可以保持氟化非晶碳与作为底层的氧化膜之间的粘附性。另外,可以减少开路失效和短路失效的出现,这些失效是由于布线和置于上述氟化非晶碳上面的层间膜的剥落而引起的。所以,可以显著提高半导体器件制造的可靠性和成品率。
由于在不偏离本发明的精神实质情况下,本发明可以按多种形式来实施,因此本发明的实例是例示性的,不限制本发明,由于本发明的实质限制在附属权利要求书中,而不是在前面说明书中,因此本发明包括所有落入权利要求书所限定范围的所有改变和类似情况。

Claims (15)

1.一种半导体器件的制造方法,包括以下步骤:
选择腐蚀铝布线;
改造置于铝布线下面的氧化膜的表面;
形成有机层间膜。
2.根据权利要求1的半导体器件的制造方法,其特征为,腐蚀铝布线后,改造氧化膜的表面时,用含CF4的气体进行等离子体处理。
3.根据权利要求1的半导体器件的制造方法,其特征为,腐蚀铝布线后,改造氧化膜的表面时,用硅进行离子注入。
4.根据权利要求1的半导体器件的制造方法,其特征为,有机层间膜由氟化非晶碳构成。
5.一种半导体器件的制造方法,包括以下步骤:
选择腐蚀形成在半导体衬底的绝缘膜上的金属布线层;
改造通过腐蚀所暴露的绝缘膜的表面;
形成有机层间膜以覆盖金属布线层和绝缘膜。
6.根据权利要求5的半导体器件的制造方法,其特征为,金属布线层包含铝布线层,而有机层间膜由氟化非晶碳构成。
7.根据权利要求5的半导体器件的制造方法,其特征为,在腐蚀金属布线层后用含CF4的气体在绝缘膜的表面进行等离子体处理,或者在形成由氟化非晶碳构成的有机层间膜之前进行硅离子注入,由此在绝缘膜的表面进行表面改造。
8.一种半导体器件的制造方法,包括以下步骤:
在半导体衬底的绝缘膜上形成铝布线层;
用抗蚀剂作为掩模来干法刻蚀铝布线层,其中抗蚀剂覆盖在铝布线层上并有图形;
用含CF4的气体在由干法刻蚀所暴露的绝缘膜表面形成损伤层;
剥落抗蚀剂;
在半导体器件的整个表面形成氟化非晶碳膜。
9.根据权利要求8的半导体器件的制造方法,其特征为,在干法刻蚀铝布线层后,用硅进行离子注入。
10.一种半导体器件的制造方法,包括以下步骤:
用光刻工艺将覆盖在铝构成的第一布线层上的光刻胶进行构图,其中第一布线层形成在半导体衬底的层间绝缘膜上;
用腐蚀气体选择腐蚀第一布线层;
改造通过选择腐蚀所暴露的层间绝缘膜的表面;
用O2等离子体剥落光刻胶;
用CVD方法形成氟化非晶碳层;
形成穿过氟化非晶碳层的VIA孔;
形成由铝构成的、并通过VIA孔与第一布线层连接的第二布线层。
11.根据权利要求10的半导体器件的制造方法,其特征为,用含CF4的气体进行等离子体处理,以在通过选择腐蚀所暴露的层间绝缘膜的表面形成多孔损伤层,由此实现层间绝缘膜的表面改造。
12.根据权利要求10的半导体器件的制造方法,其特征为,进行硅的离子注入,以在通过选择腐蚀所暴露的层间绝缘膜的表面形成损伤层,由此实现绝缘膜的表面改造。
13.根据权利要求10的半导体器件的制造方法,其特征为,层间绝缘膜由BPSG构成。
14.根据权利要求10的半导体器件的制造方法,其特征为,腐蚀气体为含Cl2和N2的混合气体。
15.根据权利要求10的半导体器件的制造方法,还包括以下步骤:
构图第二布线层;
形成由氮化硅构成的覆盖膜。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101606234B (zh) * 2007-02-09 2011-02-09 东京毅力科创株式会社 蚀刻方法及存储介质
CN104779137A (zh) * 2014-01-10 2015-07-15 北大方正集团有限公司 一种阵列基板及其制备方法
CN108511389A (zh) * 2017-02-28 2018-09-07 东京毅力科创株式会社 半导体制造方法和等离子体处理装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989998A (en) 1996-08-29 1999-11-23 Matsushita Electric Industrial Co., Ltd. Method of forming interlayer insulating film
JP3228183B2 (ja) * 1996-12-02 2001-11-12 日本電気株式会社 絶縁膜ならびにその絶縁膜を有する半導体装置とその製造方法
US6104092A (en) * 1997-04-02 2000-08-15 Nec Corporation Semiconductor device having amorphous carbon fluoride film of low dielectric constant as interlayer insulation material
US6797605B2 (en) * 2001-07-26 2004-09-28 Chartered Semiconductor Manufacturing Ltd. Method to improve adhesion of dielectric films in damascene interconnects
US20040229470A1 (en) * 2003-05-14 2004-11-18 Applied Materials, Inc. Method for etching an aluminum layer using an amorphous carbon mask
US8278139B2 (en) * 2009-09-25 2012-10-02 Applied Materials, Inc. Passivating glue layer to improve amorphous carbon to metal adhesion
US11009162B1 (en) 2019-12-27 2021-05-18 U.S. Well Services, LLC System and method for integrated flow supply line

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6046036A (ja) * 1983-08-23 1985-03-12 Nec Corp 半導体装置の製造方法
JPH0680739B2 (ja) * 1987-05-19 1994-10-12 日本電気株式会社 半導体装置の製造方法
US4843034A (en) * 1987-06-12 1989-06-27 Massachusetts Institute Of Technology Fabrication of interlayer conductive paths in integrated circuits
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
JPH02278731A (ja) * 1989-04-19 1990-11-15 Nec Corp 半導体装置の製造方法
US5282922A (en) * 1989-11-16 1994-02-01 Polycon Corporation Hybrid circuit structures and methods of fabrication
JPH0574960A (ja) * 1991-03-25 1993-03-26 Fujitsu Ltd 半導体装置の製造方法
JP2748864B2 (ja) * 1994-09-12 1998-05-13 日本電気株式会社 半導体装置及びその製造方法及び非晶質炭素膜の製造方法及びプラズマcvd装置
US5804259A (en) * 1996-11-07 1998-09-08 Applied Materials, Inc. Method and apparatus for depositing a multilayered low dielectric constant film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN104779137A (zh) * 2014-01-10 2015-07-15 北大方正集团有限公司 一种阵列基板及其制备方法
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CN108511389A (zh) * 2017-02-28 2018-09-07 东京毅力科创株式会社 半导体制造方法和等离子体处理装置

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