CN1106033C - 层间介电层平坦化制造方法 - Google Patents

层间介电层平坦化制造方法 Download PDF

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CN1106033C
CN1106033C CN98116851A CN98116851A CN1106033C CN 1106033 C CN1106033 C CN 1106033C CN 98116851 A CN98116851 A CN 98116851A CN 98116851 A CN98116851 A CN 98116851A CN 1106033 C CN1106033 C CN 1106033C
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oxide layer
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silicon nitride
dielectric layer
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CN1239318A (zh
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罗吉进
李弘名
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种在半导体元件表面上形成一平坦的层间介电层的制造方法，包括先形成衬底氧化层，在衬底氧化层表面上形成一硼磷硅玻璃层，接着，对硼磷硅玻璃层进行平坦化制造工艺，然后在硼磷硅玻璃层表面上形成上覆氧化层，最后在上覆氧化层表面上形成氮化硅层。

Description

层间介电层平坦化制造方法
技术领域
本发明涉及一种半导体元件的制造方法，特别是涉及一种层间介电层(interlayer dielectric)平坦化的制造方法。
背景技术
层间介电层和金属层间介电层(intermetal dielectric)经常沉积在导电层之上，用来和下一步骤要沉积的导电层做一隔离。层间介电层通常指介于半导体基底和第一金属层之间的绝缘层。金属层间介电层通常指位于两层金属层之间的绝缘层。
现有形成金属层间介电层的步骤包括在金属层之间沉积多层氧化硅层。例如，先沉积一层二氧化硅在金属层上，接着再沉积第一层介电系数低的材料，然后再沉积第二层二氧化硅。介电系数低的材料是用来减少金属线之间的RC延迟时间常数。最后经由黄光制造工艺构成这些多层的氧化硅层，再蚀刻出连结不同导电层之间的层间开口(via hole)。
然而，这些现有技艺所形成的金属层间介电层会有一些问题，例如介电系数低材料的导热性(thermal conductivity)很差，将会降低金属线的可靠度(reliability)，因此需要一种形成层间介电层和金属层间介电层的新方法，不仅可以提高介电层的导热性，还可以保持很小的RC延迟时间常数。
发明概述
本发明的目的在于提供一种层间介电层平坦化的制造方法，步骤包括形成衬底氧化层，在衬底氧化层表面上形成一硼磷硅玻璃层。然后对硼磷硅玻璃层进行全面性平坦化制造过程，，再形成上覆氧化层(cap oxide)于硼磷硅玻璃层的表面，最后在上覆氧化层表面上形成氮化硅层。
本发明的目的是这样实现的，即提供一种层间介电层平坦化的制造方法，该平坦的介电层形成一基底上，该方法包括：形成一衬底氧化层在该基底之上；形成一硼磷硅玻璃在该衬底氧化层之上；对该硼磷硅玻璃进行平坦化制造工艺；形成一上覆氧化层于该硼磷硅玻璃之上；以及形成一氮化硅阻挡层在该上覆氧化硅层之上。
本发明还提供一种在一基底上形成平坦的层间介电层的结构，该结构包括：一衬底氧化层在一基底之上；一硼磷硅玻璃在该衬底氧化层之上；一研磨后的上覆氧化硅层于该硼磷硅玻璃之上；以及一氮化硅阻挡层在该上覆氧化硅层之上。
在本发明中，所使用的“基底”一词，包含半导体晶片、半导体晶片上的元件及/或多层薄膜结构。
附图的简要说明
为让本发明的上述和其它目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合附图作详细说明如下：
图1-图5是本发明一较佳实施例制造过程的剖示图。
优选实施方式的详细描述
请参照图1，在基底100上有数个结构102。基底是指半导体晶片，包括在基底上所形成的主动、被动元件以及基底表面上方的多层薄膜结构。
至于结构102比如可能是金属氧化物半导体场效应晶体管的多晶硅栅极。但是在图1的结构102，可以为半导体的任一元件，不受上例的限制。
根据本发明，第一步骤先在基底100和结构102之上形成衬底氧化层104，比如用化学气相法沉积法沉积一层厚约500-1500埃的二氧化硅。衬底氧化层104主要是覆盖在结构102之上，用于作为高质量绝缘层。
下一步骤，沉积一层硼磷硅玻璃层106在衬底氧化层104之上，沉积方法比如可用化学气相沉积法。硼磷硅玻璃层106的厚度，优选为2000～8000埃。除了硼磷硅玻璃层106之外，也可用其它的类似材料代替，如磷硅玻璃。接着进行全面平坦化制造工艺，优选使用化学机械研磨法。
接下来，沉积一层上覆氧化层108，比如用化学气相沉积法沉积一层厚约1000～4000埃的二氧化硅，上覆氧化层108主要是作为一高质量的绝缘层。
然后沉积一层约300～3000埃厚的阻挡层110在上覆氧化层108之上。阻挡层110的优选材料是氮化硅(SixNy包括Si3N4)，而氮化硅的形成方法比如用化学气相沉积法。
请参考图2，在氮化硅层110之上涂布一层光致抗蚀剂层112，经过构成、显影的步骤，留下开口103。
接着以光致抗蚀剂层112为掩模，依序蚀刻氮化硅层110、上覆氧化层108、硼磷硅玻璃层106以及衬底氧化层104来形成一接触窗口(contacthole)，较常用的方法为各向异性反应性离子蚀刻法(Anisotropic Reactive IonEtch)。由于有氮化硅层110，因此需要用两个步骤、两化学处理(2-step 2-chemistry)的反应性离子蚀刻。这个接触窗口可能和晶体管的漏极或源极相接。
请参考图3，接着用化学气相沉积法在接触窗口形成一金属钨插塞114。然后再形成一层金属铝层116在金属钨插塞114以及整个氮化硅层110之上，金属铝的形成方法比如可用物理气相沉积法。接着对金属铝层进行光刻的蚀刻制造工艺。
为了可以更加清楚了解本发明能够如何应用，请继续参考图4。在铝金属线116和氮化硅层110上面形成第二衬底氧化层402，厚度优选约在500-1500埃之间。再来形成一层介电系数低的介电层404于第二衬底氧化层402之上，厚度优选约为3000-8000埃，此介电层404的材料比如可以是高分子聚合物。
在介电系数低的介电层404之上形成第二上覆氧化层406。第二上覆氧化层406优选为约2000～6000埃厚的二氧化硅。接着用化学机械研磨法研磨第二上覆氧化层406的表面。最后，再沉积第二氮化硅阻挡层408在第二上覆氧化层406之上，比如用化学气相沉积法，厚度优选约为300～3000埃。
请看图5，接着在第二氮化硅阻挡层408、第二上覆氧化层406、介电系数低的介电层404、第二衬底氧化层402之中形成一层间开口410。最后在层间开口410中形成第二金属钨插塞412，并在其上形成第二金属铝线414。
结果发现由衬底氧化层104、硼磷硅玻璃106、上覆氧化层108以及氮化硅层110所组成的层间介电层，具有许多优点。同样的，由第二衬底氧化层402、介电系数低的介电层404、第二上覆氧化层406以及第二氮化硅阻挡层408所组成的金属层间介电层，同样也有优于现有技术的地方。
本发明方法的优点在于：第一、由实验结果指出导电区域414、116的可靠度提高了，主要是因为在其下方的氮化硅层的导热性较好，尤其由电脑模拟的结果可以看出导电区域414、116的温度，确定比现有技术要低；第二、本发明所提出的制造工艺不仅简单而且成本低廉。
虽然以上结合一较佳实施例揭露了本发明，但是其并非限定本发明，本领域技术人员在不脱离本发明的精神和范围内，可作各种的更动与润饰，因此本发明的保护范围应当由所附的权利来要求限定。

Claims (12)

1.一种层间介电层平坦化的制造方法，该平坦的介电层形成于一基底上，该方法包括：
形成一衬底氧化层在该基底之上；
形成一硼磷硅玻璃在该衬底氧化层之上；
对该硼磷硅玻璃进行平坦化制造工艺；
形成一上覆氧化硅层于该硼磷硅玻璃之上；以及
形成一氮化硅阻挡层在该上覆氧化硅层之上。
2.如权利要求1所述的方法，其特征在于，该方法还包括下列步骤，构图并依序蚀刻该氮化硅阻挡层、该上覆氧化硅层、该硼磷硅玻璃、该衬底氧化层至该基底为止，形成一接触窗口。
3.如权利要求1所述的方法，其特征在于，该氮化硅阻挡层的成分为Si3N4。
4.如权利要求2所述的方法，其特征在于，该方法还包括沉积一金属钨插塞于该接触窗口中。
5.如权利要求4所述的方法，其特征在于，该方法还包括形成一导电结构于该金属钨插塞和该氮化硅阻挡层之上。
6.如权利要求5所述的方法，其特征在于，该方法还包括形成一金属层间介电层的步骤，该形成步骤包括：
形成一第二衬底氧化层于该导电结构之上；
形成一介电系数低的介电层于该第二衬底氧化层之上；
形成一第二上覆氧化硅层于该介电系数低的介电层之上；
对该第二上覆氧化硅层进行平坦化制造工艺；
形成一第二氮化硅阻挡层于该第二上覆氧化硅层之上。
7.如权利要求6所述的方法，其特征在于，该方法还包括构图及依序蚀刻该第二氮化硅阻挡层、该第二上覆氧化硅层、该介电系数低的介电层以及第二衬底氧化层直至该导电结构之上，形成一层间开口。
8.一种在一基底上形成平坦的层间介电层的结构，其特征在于，该结构包括：
一衬底氧化层在一基底之上；
一硼磷硅玻璃在该衬底氧化层之上；
一研磨后的上覆氧化硅层于该硼磷硅玻璃之上；以及
一氮化硅阻挡层在该上覆氧化硅层之上。
9.如权利要求8所述的层间介电层的结构，其特征在于，该氮化硅阻挡层为Si3N4。
10.如权利要求8所述的层间介电层的结构，其特征在于，还包括：
穿透该氮化硅阻挡层、该上覆氧化硅层、该硼磷硅玻璃以及该衬底氧化层的一接触窗口；
一金属钨插塞在该接触窗口之中；
一导电结构在该金属钨插塞以及该氮化硅阻挡层之上。
11.如权利要求10所述的结构，其特征在于，该结构还包括一金属层间介电层，其包括：
一第二衬底氧化层于该导电结构之上；
一介电系数低的介电层于该第二衬底氧化层之上；
一平坦的第二上覆氧化硅层于该介电系数低的介电层之上；
一第二氮化硅阻挡层于该第二上覆氧化硅层之上。
12.如权利要求11所述的结构，其特征在于，还包括穿透该第二氮化硅阻挡层、该第二上覆氧化硅层、该介电系数低的介电层以及第二衬底氧化层的一层间开口。
CN98116851A 1998-06-12 1998-08-04 层间介电层平坦化制造方法 Expired - Lifetime CN1106033C (zh)

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