CN1303229A - 薄型集成电阻和电容和电感组件及其制作方法 - Google Patents

薄型集成电阻和电容和电感组件及其制作方法 Download PDF

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CN1303229A
CN1303229A CN00131872A CN00131872A CN1303229A CN 1303229 A CN1303229 A CN 1303229A CN 00131872 A CN00131872 A CN 00131872A CN 00131872 A CN00131872 A CN 00131872A CN 1303229 A CN1303229 A CN 1303229A
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理查德·W·卡彭特
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Abstract

形成薄型电路结构,包括导电电路轨迹、集总电感和集总电阻。第一层叠结构包括导电金属箔,其上有一层可嵌入绝缘材料。第二层叠结构包括导电金属箔,其一侧有一层电阻材料,电阻材料层的厚度薄于可嵌入绝缘材料层。电阻材料层电路化形成电阻块,两个结构被叠层到一起,使电阻块嵌入绝缘材料层中。金属箔层之一被电路化,来提供电路轨迹、可选电感绕组和电容极板。嵌入绝缘叠层中的金属箔为进一步加工结构提供支持。另一金属箔然后电路化,来提供电路轨迹等。一侧的轨迹与电阻材料块连接来提供电阻。

Description

薄型集成电阻和电容和电感组件及其制作方法
本发明涉及薄型电子电路，该电路提供了电阻、电容、互连电路和可选电感，并涉及此类结构的制作方法。
人们一直热衷于印刷电路的小型化。在使用的多数印刷电路中，电路轨迹通过传统方法，特别是光致抗蚀技术印刷。如电容和电阻这类附件通常作为分立元件提供，并由人工或机器人焊接在印刷电路上。这些元件占据印刷电路板上的“不动产”，并且将其安装在电路板上是困难的或昂贵的。
因此，希望通过形成电路工艺实现这样的结构，其中的元件如电阻和/或电容沿电路轨迹安排。这样结构的例子可以在美国专利号5079069,5155655,5161086,5261153,5347258和5466892中找到，它们的每个阐述在这里可作为参考。典型地，许多这样的结构与绝缘材料叠层在一起，形成多层印刷电路板。
本发明关于形成薄型电路叠层结构的方法，该结构提供有电阻、电容和包括电路轨迹及任选电感的导电元件，并且关于由其形成的薄型电路化叠层结构。
根据本发明采用的方法，提供有第一导电金属箔，其上被叠层上有可嵌入绝缘材料层，和第二导电金属箔，其上的一侧覆盖有电阻材料层，第二层金属箔上的电阻材料层具有的厚度小于第一层金属箔上的可嵌入绝缘材料层。电阻材料层被电路化形成电阻材料的分散块。然后，两个结构叠层压到一起带有嵌入到可嵌入绝缘材料层的电阻材料层，但不使电阻材料块接触第一金属箔。此时，或者第一或者第二金属箔被电路化，提供了互连的电路轨迹和可选电路元件如电感。为了支持这一结构，电路化的金属箔被嵌入到绝缘材料中，如填充有玻璃的环氧树脂，即所谓“预浸渍制品”，这种材料在后面的加工中支承该结构。用如此支持的结构，另一金属箔然后被电路化，并且这一侧也可以被嵌入到绝缘材料中。几层这样的结构可以被叠层到一起，形成多层的印刷电路板，这几层可以通过孔以传统方式进行电气互连。
图1显示了其上叠层有一薄层可嵌入绝缘材料的第一金属箔的剖面图。
图2显示了其上沉积有薄层电阻材料的第二金属箔的剖面图。
图3显示了图2所示结构的剖面图，其中第二金属箔上的电阻材料被电路化，形成分散的电阻块。
图4显示了图1所示结构叠层到图3所示的结构的剖面图并带有嵌入到可嵌入绝缘材料层中的电阻材料块。
图5显示了图4所示结构的剖面图，其中第二金属箔层已被电路化。
图6显示了结构的剖面图，其中电路化的第二金属箔层被嵌入绝缘材料中，然后第一金属箔层被电路化。
图1表示的是结构10，包括金属箔层11，其上叠层有一薄层绝缘材料12。图2显示的是结构13，包括金属箔层14，其上沉积有一薄层电阻材料。金属箔层11和14可以是从各种金属和金属合金中选择，尽管铜金属箔是最通常使用的。典型地，金属箔11和14的厚度是大约在3到50μm之间。绝缘材料层12的厚度大约在3到50μm之间。电阻材料层15的厚度大约在0.1到0.5μm之间，但是无论如何要薄，典型地比绝缘材料层12的厚度薄大约2.9至49.5μm之间。
当前用于绝缘材料层12的优选材料是环氧树脂，比如以Dynavin为商标销售的材料。
作为第一步，电阻材料层15被电路化，来形成金属箔14上的离散电阻层块15a，从而在第二金属箔14上形成图3的结构13a(为了简化说明，只画出了一块这样的电阻块15a)。电阻层15的电路化，与形成印刷电路轨迹的传统的形成导电电路非常相似。电阻层15上覆盖有光致抗蚀剂(这里描述的是负性光致抗蚀剂)；光致抗蚀剂通过布线图样被曝光于光化学辐射下；光致抗蚀剂的未曝光部分被冲洗掉，下面的电阻材料层15的暴露部分被蚀刻。
美国专利申请号09/198954的讲授在这里引用为参考，讲授了形成层15的优选电阻材料。这一专利申请讲授了含有相对少量绝缘材料，如氧化硅的铂，根据绝缘材料的含量具有基本的电阻率，绝缘材料的含量典型的区间大约从0.5％到5.0％的百分比重量。一薄层掺杂了氧化硅的铂采用燃烧化学汽相沉积(CCVD)法传统地淀积，这一过程在美国专利号5652021中描述，它的讲授这里引用为参考。CCVD法沉积Pt/SiO2具有实质的多孔性，使其可能从铜箔上去除Pt/SiO2的选择部分，这一过程在上述参考的美国专利申请号09/198954中描述为烧蚀蚀刻。Pt/SiO2层的曝光部分暴露于铜蚀刻剂，如氯化铁中。蚀刻剂通过Pt/SiO2层渗入，腐蚀两层间界面间的铜。发现当下面的铜层被极大地剥蚀前失去粘附力时，Pt/SiO2层被烧蚀掉。铜(或其它金属箔)上的Pt/SiO2层可以以这种方式电路化。作为这一过程的改进，很薄的蚀刻剂敏感层，例如镍，(未示出)在Pt/SiO2层被沉积前，或者通过CCVD法，或者通过电镀法沉积到铜金属箔上。当蚀刻剂通过Pt/SiO2层渗入时，很快地腐蚀蚀刻剂敏感层，促进烧蚀蚀刻过程。
这时，第一金属箔11上具有绝缘材料层12的结构10，通过将电阻材料块15a侧压入绝缘材料12，叠层到结构13a中，将块15a嵌入绝缘材料中，形成图4的结构16。因为由于绝缘材料层12比电阻块15a厚一些，所以块15a通过绝缘材料层12的减薄部分仍与第一金属箔11保持电气绝缘性能。
下面，第二金属箔层14通过传统的光刻电路形成技术被电路化，来形成具有图5所示电路元件20、21和22的结构19(这一过程可以通过首先对第一金属箔11电路化，然后对第二金属箔层14电路化来实现)。元件20代表在电阻块15a相反端的导电连接轨迹。这样电阻电路在连接电路20之间通过电阻块15a形成；这样15a和20作为一个单元形成一个电阻。元件21代表电容的一个导电极板，电容在元件21与然后通过第一金属箔层11形成电路来形成的相似的极板之间组成。元件22代表作为电感的印刷形成的电绕组。
薄绝缘材料层12实质上不具备机械强度。因此，在对结构19进行进一步加工之前，结构19的形成电路侧被嵌入到一层图6所示机械支持结构的叠层绝缘材料26中。然后，将第一金属箔层电路化，来形成电路轨迹、电容极板21和电感绕组22。电路化的侧然后也被嵌入到叠层绝缘材料的另一层中(未画出)。多个这样的结构可以被叠层到一起，形成多层的印刷电路板，其中有以传统的方法形成的通孔和电镀，在多层之间形成电连接。
本发明通过特定的例子更具体地描述。
                            例1
如图1的结构10的形成
50μm厚的铜金属箔被叠层到作为可嵌入的绝缘材料层12的50μm厚的Dynavin薄片上。例2如图2的结构13的形成通过电镀将3.5μm厚的镍层沉积到50μm厚的铜金属箔上。通过CCVD法沉积0到15μm厚的Pt/SiO2层(97.5∶2.5重量比)，在如下的沉淀条件下：溶解制备
1.23g Pt(COD)*
250ml甲苯
0.43g TEOS**(甲苯中Si为1.5％百分比重量)
150g丙烷沉积条件
溶液流量 3ml/min
沉积时间 1h
沉积温度 500℃
 Variac 3.0A
管尖氧气流量 2900ml/min
*联苯-(1,5-环辛二烯)铂Ⅱ**四乙氧基硅烷例3印刷电路的形成
例2中制造的结构的两侧都用Laminar5000光刻胶覆盖。Pt/SiO2侧曝光在具有布线图样的光化学辐射下，并且金属箔侧完全曝光在光化学辐射下。结构然后被2％的碳酸钠溶液在80℃时冲洗，从电阻材料侧去除未曝光的光刻胶层区域。通过曝光的光刻胶层保护铜金属箔，结构被置于在氯化铜溶液中，经过足够长的时间使溶液能够渗透Pt/SiO2，并且充分地剥蚀镍层，使Pt/SiO2的暴露部分被烧蚀掉。然后光刻胶层被NaOH溶液去除。这一蚀刻结构然后被叠层到图1的结构中，将剩余的Pt/SiO2部分嵌入绝缘材料中。
然后两层金属箔层都被光刻胶覆盖。具有Pt/SiO2的金属箔层被曝光在具有布线图样的光化学辐射下；在同一加工过程中另一金属箔层被完全曝光用于保护。如上所述结构被碳酸钠溶液冲洗，一层金属箔层的暴露部分被氯化铁溶液蚀刻形成电路轨迹、电容极板、电阻连线以及电感绕组。然后光刻胶从结构的两侧被去除。
电路化的金属箔层被嵌入叠层绝缘材料中。
然后另一金属箔层如前所述那样被电路化，形成电路轨迹、电容极板和电感绕组。

Claims (14)

1．一种形成包括电路轨迹、集总电阻和集总电容的电子电路的方法，该方法包括：
提供第一叠层结构，该结构包括第一导电金属箔和一层被叠层其上的可嵌入的绝缘材料；
提供第二叠层结构，该结构包括其一侧具有一层电阻材料的第二导电金属箔，所述电阻材料层具有比所述可嵌入绝缘材料层薄的厚度；
将所述电阻材料层电路化，在第二金属箔上制造离散的电阻材料块；
叠层所述第一和第二结构，使所述电阻材料块嵌入到所述可嵌入绝缘材料层中；
将所述金属箔中的一个或另一个电路化，来形成电容极板、电路轨迹、可选电感绕组，和在第二金属箔的电阻连接情况下；
将电路化的金属箔嵌入叠层绝缘材料中，作为下一步加工的支持结构；
将所述金属箔中的另一个电路化，来形成电容极板、电路轨迹、可选电感绕组，和在第二金属箔的电阻连接情况下。
2．权利要求1的方法，还将所述电路化的金属箔中的另一个嵌入叠层绝缘材料中。
3．将一组采用权利要求1方法制造的电子电路叠层到一起，形成多层的印刷电路板。
4．权利要求1的方法，其中所述金属箔层的每一层厚度大约在3到50μm之间。
5．权利要求1的方法，其中所述电阻层的厚度大约在0.1到0.5μm之间；所述可嵌入材料层厚度大约在3到50μm之间，并且所述可嵌入材料层的厚度比所述电阻材料层的厚度厚大约2.9到49.5μm。
6．根据权利要求1的方法，其中所述金属箔是铜。
7．根据权利要求1的方法，其中所述可嵌入的绝缘材料是环氧树脂。
8．根据权利要求1的方法，其中所述电阻材料层材料是掺杂绝缘材料的铂。
9．一种嵌入式电路结构，按顺序包括：
环氧树脂层的嵌入层，
导电材料的第一电路化层，
电阻材料的布线图案层，具有电阻材料块，与所述第一电路化导电层相连，使电阻电路通过所述电阻材料的所述块形成，
绝缘材料层，所述电阻材料块嵌入所述绝缘材料层中，和
导电材料的第二电路化层，所述绝缘材料层将所述第二电路化层与所述电阻材料块隔开，电容电路被设定在通过所述绝缘材料层的所述第一和第二电路化层之间。
10．根据权利要求9的结构，其中所述第二电路化层被嵌入环氧树脂层中。
11．根据权利要求9的结构，其中所述绝缘材料层是环氧树脂。
12．根据权利要求9的结构，其中所述电阻材料层是掺杂绝缘材料的铂。
13．根据权利要求9的结构，其中所述金属箔层的每一层的厚度大约在3到50μm之间。
14．根据权利要求9的结构，其中所述电阻层的厚度大约在0.1到0.5μm之间；所述可嵌入材料层的厚度大约在3到50μm之间；所述可嵌入材料层的厚度比电阻层的厚度大约厚2.9到49.5μm。
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