CN1302455A - 层叠的集成电路封装 - Google Patents
层叠的集成电路封装 Download PDFInfo
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Abstract
提供了一种用于封装集成电路的低成本集成电路封装。在较佳实施例中,该封装包括使用介电粘合剂层叠到加强板的柔性电路,柔性电路上的导电迹线面向加强板但通过粘合剂与此加强板隔开。此导电迹线包括倒装片附着焊接区的阵列。通过诸如蚀刻等在附着焊接区阵列上的加强板中形成窗口。然后,通过激光烧蚀除去该附着焊接区上的粘合剂,但留下焊接区之间适当位置处的粘合剂,从而形成一倒装片附着地点。在较佳实施例中,本发明不需要高分辨率构图的粘合剂,也不需要在倒装片附着地点加上焊接掩模,这是因为剩余的粘合剂起到了防止附着焊接区之间的桥接的焊接掩模的作用。由于在把这些层层叠到加强板期间在柔性电路和粘合剂层中所形成的张力,所以该封装提供了具有高平整度的小片附着地点。TBGA、易折引线和其它封装技术可使用本发明的实施例。
Description
技术领域
本发明涉及半导体封装技术的领域。尤其是,提供一种改进的芯片载体,它有用于焊台(solder bump)或倒装片集成电路的载带网格焊球阵列(TGBA)封装技术。
背景技术
半导体集成电路(这里也叫做“小片”或“芯片”)的尺寸不断减小,从而需要适应互连密度不断提高的互连和封装技术。在不久的将来应用于芯片的预期互连密度将需要封装技术的发展,以把这些芯片连接到其它电路。尤其是,利用焊台以及所谓“倒装片”电路的集成电路包括位于芯片(必须连接到其它电路)有源一侧上的接触焊接区(contact pad)阵列。通常,在集成电路上的接触焊接区与载体或封装上的导电元件之间形成焊接连接。载体上的导电元件把每个接触焊接区耦合到载体结构中的选中地点。载体的目的是把芯片接触焊接区的非常高的密度(及相应的小尺寸)转换到密度较低的载体触点配置。载体触点可采用网格焊球阵列(BGA)的形式,它在本领域内是众所周知的。然后,例如可使用本领域内公知的标准方法把载体连接到印刷电路板。为了芯片的散热(这也可能是许多应用中的基本工程要求)也必须设置载体。倒装片所附着的载体的平整度和热稳定性也是重要的需要,随着芯片变得越来越小以及焊接区(pad)密度变得越来越高,平整度和热稳定性更难于满足。
载体的某些公知类型包括载带网格焊球阵列(TBGA)技术。该技术利用了其上形成导电迹线(trace)的柔性载带。每一迹线从可与一芯片接触焊接区相连(例如通过丝键合或倒装片技术)的点延伸到网格焊球阵列中的一个焊球。通常用粘合剂把TBGA载体附着于一相对硬的加强板(stiffener),这从某种程度上也为封装提供了平整度。为了物理支撑,可把芯片连接到载带或加强板。通常使加强板与芯片接触或位于芯片附近,以有助于移去芯片的热量。对于丝键合的应用,可在载带中央形成一个窗口,且芯片可位于该窗口内,从而芯片上的焊接区(bond pad)(在丝键合应用中,它们通常位于芯片的边缘周围)尽可能靠近将与它们相连的导电迹线。5,663,530号美国专利(引入于此作为参考)更详细地描述了丝键合TBGA封装。′530专利的发明利用绝缘粘合剂,以在迹线与导电加强板位于柔性电路的同一侧时使柔性电路上的导电迹线与导电加强板绝缘。
在某些已有技术的倒装片附着工艺中,已利用各向异性粘合剂。在5,686,703(在这里通过参考而引入)号美国专利中提出了这种粘合剂的一个例子。
5,583,378(在这里通过参考而引入)号美国专利详细地描述了丝键合和倒装片BGA配置。如本说明书的图1所示,在′378号专利中所揭示的倒装片配置中,通过一层粘合剂22把加强板20附着到柔性载带24的一侧,导电迹线26、接触焊接区28和焊球30位于载带24上与加强板20相反的一侧。使用倒装片技术把集成电路芯片32附着到载体接触焊接区28,其中在载体-28与芯片焊接区36之间形成焊接连接34。即使绝缘载带、粘合剂和密封剂诸层可把芯片与加强板分离,但芯片32可足够靠近加强板28,以使加强板在某些应用中起到散热片的作用。
涉及这个和其它已有技术倒装片TBGA配置的问题在于,芯片32必需位于载带(以及加强板20)上与BGA焊球30相同的一侧,从而芯片32在安装时被夹在载体与印刷电路板(PCB)之间,这样阻碍了在必要时在芯片上附装散热片。此方案还需要在倒装片附着区中应用高密度高精度的焊接掩模,这是一个非常困难且费钱的处理步骤。最后,由于芯片尺寸和芯片互连密度的公差变小,所以变得难于在载体上形成足够平整的倒装片附着触点28。即使只有一个接触焊接区充分不共面,也可引起不当附着和封装器件的故障,这一点是公认的。
发明内容
本发明针对已有技术中的缺陷,提供了一种集成电路芯片载体,该载体适用于经预期非常高的倒装片触点密度。本发明提供了一种倒装片封装,其中芯片可位于柔性电路载带的上面,从而在把该封装安装在PC板或其它衬底上时可达到热处理或其它目的。通过把加强板附着于载带并在加强板中形成一窗口,以把用于倒装片连接的载体接触焊接区保持共面排列。该窗口可以通过对加强板材料进行蚀刻来形成。可把芯片附着于通过窗口暴露的柔性电路。此外,通过把加强板与载带之间的粘接层用作使迹线与加强板绝缘以及使倒装片触点相互绝缘的介质,消除了费钱的焊接掩模操作。在倒装片触点所在的位置处,可通过例如激光烧蚀在粘接层中形成通孔。也可在集成电路小片位于载带的上面以及导电迹线位于载带的下面(所谓的“电路在外(circuit out)”结构)时应用本发明的实施例。在此结构中,可通过激光烧蚀或其它方法在载带中形成通孔,以暴露小片附着焊接区。
在本发明的较佳实施例中,柔性电路载带和粘合剂具有比加强板高的热膨胀系数,从而在高温工艺中把该电路层叠到加强板时,当把层叠的组件冷却到室温时,载带和粘合剂将相对于加强板收缩,于是在载带和粘合材料中形成张力。在如这里所述在加强板中切割出窗口时,跨越窗口的载带和粘合剂将绷紧,从而在倒装片连接附近提供非常高的平整度,从而使连接的性能和可靠性与已有技术相比有所提高。在本发明的较佳实施例中,柔性电路的平整度在芯片安装位置处可好于25微米,在板安装位置处可好于6密耳。
本发明还消除了倒装片小片界面(在这里,电路图案位于柔性载带上与集成电路相同的一侧)处的精细间距焊接掩模的需要,这是因为粘合剂覆盖的柔性电路的上侧,而且可通过诸如激光烧蚀等选择性地除去粘合剂而到达柔性电路上的焊接区。可留下焊接区之间的粘合剂,以提供绝缘并防止焊接搭接。在某些实施例中,可相对于柔性电路上的其它迹线而抬高小片附着焊接区,从而可均匀地除去窗口区域(未构图)中的粘合剂,以暴露抬高的焊接区同时仍旧覆盖导电迹线。在这些实施例中,可通过等离子体或化学蚀刻工艺来除去粘合剂。
可在各种应用中使用由所附的权利要求书来限定的本发明的各种实施例。“倒装片”只是本发明可利用的小片连接技术的一个例子。目前公知和以后开发的其它连接方法可得益于本发明。可在本发明中使用各种类型的柔性电路材料和结构。例如,可在本发明中使用多迹线层结构,包括双金属设计和层叠的多层电路。
在一个方面,本发明提供了一种用于集成电路芯片的封装部件,它包括一层柔性介电载带,在其第一侧上形成了选中的导电迹线图案,所述导电迹线具有小片附着焊接区和网格焊球阵列附着焊接区;在所述载带中形成的暴露位于载带第二侧上的所述网格焊球阵列附着焊接区的开口;覆盖载带的所述第一侧且其上形成了导电迹线的一层介电粘合剂;在所述介电粘合剂层中形成的暴露所述小片附着焊接区的开口;以及附着于介电粘合剂层的加强板,在加强板中形成一暴露所述小片附着焊接区的窗口。在某些实施例中,本发明还可包括置于载带的第二侧上的多个焊球,通过在载带中形成的开口把这些焊球附着于网格焊球阵列附着焊接区;以及置于加强板中形成的窗口内并可操作地附着于小片附着焊接区的集成电路。
在另一个方面,本发明提供一种制造用于集成电路的封装部件的方法,它包括提供了一柔性介电载带,其上形成了选中的导电迹线图案,所述导电迹线具有小片附着焊接区和网格焊球阵列附着焊接区;把一层介电粘合剂加到载带的第一侧,覆盖其上形成的导电迹线和小片附着焊接区;使用此粘合剂把一加强板附着于载带,从而加强板覆盖该载带及上形成的导电迹线,而且加强板以介电粘合剂的厚度与导电迹线分离;在所述加强板中形成一窗口,从而暴露载带的一部分以及小片附着焊接区所在处的粘合剂;以及除去覆在所述小片附着焊接区上的粘合剂从而暴露此小片附着焊接区,同时留下小片附着焊接区之间的粘合剂。
在较佳实施例中,为了把载带层叠到加强板上,可通过对载带、粘合剂和加强板的组件加热和加压,或许可通过把组件加热到至少500华氏度且每平方英寸加上至少200磅的压强,从而把加强板层叠到载带上。
在另一个方面,本发明提供了一种用于集成电路芯片的封装部件,它包括一层柔性介电载带,其上形成了选中的导电迹线图案;覆盖载带的第一侧及其上形成的导电迹线的一层介电粘合剂;在所述介电粘合剂层中形成的暴露小片附着焊接区的开口,留下焊接区之间的所述粘合剂;以及一附着于介电粘合剂层的非导电的加强板,在加强板中形成一暴露所述小片附着焊接区的开口。
在再一个方面,本发明提供了一种用于集成电路芯片的封装部件,它包括一层柔性介电载带,其上形成了选中的导电迹线图案;覆盖载带的第一侧及其上形成的导电迹线的一层各向异性导电粘合剂;以及一附着于所述介电粘合剂层的非导电的加强板,在加强板中形成一暴露位于覆在所述小片附着焊接区上的区域中的所述粘合剂的开口。
在又一个方面,本发明提供了一种形成用于半导体小片的封装的方法,该方法包括使用介电粘合剂,在升高的温度和压强下把一柔性电路层叠到一加强板上,该柔性电路具有小片附着功能部件(feature);然后除去靠近所述小片附着功能部件的一部分加强板,以在加强板中形成孔口。
在还有一个方面,本发明提供了一种形成用于半导体器件的封装的方法,该方法包括提供包括一柔性电路、一粘接层以及一通常为平面的加强板的层叠组件;以及在加强板中形成孔口,以暴露下面的粘接层。
本发明可等效地与用于把封装小片安装到PC板或其它衬底上的各种技术相结合地应用。这些技术包括各种类型的网格焊球阵列、网格插针阵列以及悬臂或易折引线方案,这可能涉及诸如焊接、热压、超声波加压等其它导电焊接方法。对于某些附着技术,为了接近安装引线,可穿过加强板蚀刻附加的窗口。可在形成小片附着窗口的同时穿过加强板对这些窗口进行构图和蚀刻。
附图概述
参考附图中所示本发明的实施例,可更特别地描述以上所归纳的本发明,所以这里所述的本发明的优点和特征以及其它将变得明显起来,并可详细地理解。这些附图形成本说明书的一部分。
然而,注意,附图仅示出本发明的示例实施例,因此不把它们作为对本发明范围的限制,因为本发明可容许其它等效实施例。
图1是已有技术的倒装片/TBGA组件的正视图。
图2是本发明的原理部件的分解剖面图。
图3是在加强板中形成一窗口前本发明的原理部件的剖面正视图。
图4是示出在加强板中已形成一窗口后图3的组件。
图5示出在除去粘合剂而暴露小片附着焊接区后图4的组件。
图6是示出依据本发明附着于芯片载体的集成电路和BGA焊球的剖面正视图。
图7A-7E是在完成利用柔性电路上的抬高的小片附着焊接区的实施例的渐进步骤中本发明的一个实施例的剖面图。
图8是依据本发明的芯片载体的一个示例“电路在外”实施例的剖面图。
注意,这些图是示出本发明的各部件关系的示意图,它们不是按比例绘制。
本发明较佳实施例的详述
参考图2-5,在一较佳实施例中,本发明提供了一种TBGA芯片载体,它是包括层叠到加强板52的柔性BGA电路50的集成电路封装的一个部件。为了讨论的目的,将认为柔性电路50在加强板52以下,虽然这一特定方向是任意的。在使用中,把集成电路芯片安装在加强板52中形成的窗口54中柔性电路50的顶部,且可通过一焊接连接阵列把柔性电路连接到PC板或其它衬底,从而通过柔性电路的导电迹线把集成电路的焊接区连到衬底上的导电迹线。在加强板52中设有孔口或窗口54,暴露了柔性电路50的上侧,从而可使用例如本领域内公知的C4倒装片连接技术把集成电路(IC)附着到柔性电路50暴露的小片附着焊接区56上。本发明可与其它技术包括将来可能开发的技术把芯片连到载体一起使用。
在本专利申请中对“倒装片”技术的引用将确定把集成电路小片(其有源表面上具有焊接区)附着到衬底上的导电迹线,其中小片的有源表面面对衬底。倒装片连接方法通常涉及使用焊膏、焊球或焊台在小片32上的焊接区36与衬底20上的相应附着焊接区28之间形成导电连接。在应用于本专利申请中时,术语“倒装片”还将使用热压和其它基于非焊接的连接技术。
在典型的焊台或倒装片IC连接工艺中,把一焊接掩模加到柔性电路50上的小片附着焊接区56的阵列上,以防止离得非常近且容易桥接的连接之间发生焊接桥接。在本发明中,不需要焊接掩模,这是因为用来把柔性电路50层叠到加强板52上的粘合剂层58也起到把小片附着焊接区56(以及芯片小片焊接区)相互隔离的作用,从而防止了焊接桥接。
参考所示较佳实施例中的图2,依据本发明的封装部件包括(ⅰ)柔性电路50,包括其上形成了导电迹线62的柔性介电载带层60,(ⅱ)一层粘合剂58,以及(ⅲ)加强板52。导电迹线62包括载带顶面上的载体焊接区56的阵列,在电路层62中还形成了BGA焊球焊接区64,它们通过载带中形成的通孔66暴露于载带60的底面。使用粘合剂58把加强板52层叠到载带60上。粘合剂可以是不导电的,且用于把电路62与加强板(可能是导电的)隔离并绝缘,还可用于把柔性电路50安全地附着到加强板。
适用于本发明的介电载带60的一个例子是Kapton载带,它的厚度在0.5和5密尔之间,它是由DuPont制造和销售的。该载带可激光蚀刻、具有耐化学性和耐热性,且起到焊接掩模的作用。在本发明中还可使用本领域内公知的其它材料。
在本较佳实施例中,可使用本领域内公知的标准光刻技术(附加或减去)在载带的上表面上形成想要的导电电路图案62。在本较佳实施例中,柔性电路50可通过首先给载带涂敷例如15到35微米的铜来制成。然后,给铜表面涂敷光致抗蚀剂,使用一掩模对抗蚀剂进行曝光而形成想要的金属化图案,对抗蚀剂进行冲洗以露出将要除去的铜层部分。然后,通过蚀刻除去这些铜,把其余抗蚀剂从载带上剥离,留下想要的铜导体62的图案。(也可把载带材料蚀刻成想要的图案)。然后,在必要时可对铜导体进行镀敷。在较佳实施例中,可给铜镀上约60微英寸的镍,接着镀上约20微英寸的金,以提供与导体上所形成的载体小片焊接区56形成倒装片连接的适当表面。可在特殊应用中选择柔性电路导体的冶金术,以适应将要利用的连接技术。本发明中所使用的适当柔性电路是由St.Paul,Minnesota的Minnesota Mining andManufacturing Company以及IBM、Shinko、Ibiden、Nitto Denko、NipponMektron和Sheldahl制造和销售的。3M公司所拥有的5,227,008号美国专利描述了制造可用于本发明的柔性电路的示例工艺,该专利在这里通过参考而引入。
可通过诸如蚀刻、铣削(mill)、激光烧蚀或本领域内公知的其它方法在载带60中形成暴露导电迹线62的选中区域的孔,在载带60的底面上形成BGA连接地点。
在如上所述制备的柔性电路50后,可把它层叠到加强板52上。加强板52可由薄的平面材料制成,它具有足够的硬度来支撑具有获得芯片与小片附着焊接区之间的良好倒装片连接所需的规定平整度的载带组件。根据特殊应用的需要,加强板可以是导电的,也可以是不导电的。在本发明的较佳实施例中,加强板52是由镀敷了厚度为15到35微米的铜的镍制成的。本领域内的技术人员在特殊应用中可选择使用其它材料和尺寸。
对于用来把柔性电路50层叠到加强板52的粘合剂58,最好选择具有良好介电特性并可激光烧蚀,具有耐热性、耐化学性、耐焊接性且适应于用作焊接掩模。粘合剂还应对柔性电路材料(载带60和导电迹线62)和选中的加强板材料具有良好的粘性。所揭示的实施例中所使用的较佳粘合剂是聚酰亚胺粘合剂,它的一个例子是可从Wilmington,Delaware的EI DuPont de Nemours获得的Kapton KJ。该粘合剂的化学组成非常类似于在许多微弯曲(microflex)型电路中所使用的聚酰亚胺电路衬底,因此几乎不存在因离子或扩散效应而沾污微弯曲电路或焊接区的危险。依据本发明,其它粘合剂包括聚酰亚胺、聚酰亚混合物和环氧等也是适用的。本较佳实施例在柔性载带与加强板之间利用50微米的Kapton KJ粘合剂层。导电迹线62可从载带60的表面上抬高约25微米,因此这一数量的粘合剂在迹线与加强板之间提供了由约25微米的介电粘合剂填充的绝缘空间。当然,这些尺寸只是示例性的,而不认为是对本发明的限制,因为本发明是由权利要求书来限定的。为了在载带与加强板之间形成良好的无空隙密封,可在升高的温度和压强下对粘合剂进行固化。
例子:通过把柔性电路50、粘合剂58和加强板52置于预热到400华氏度的压力机中来制造本发明的原型。然后,把温度增加到670°F,同时把每平方英寸150磅(psi)加到这些部件上。在670°F,把压强增加到750psi并保持8分钟,然后冷却到600°F同时保持压强。然后,把压强减小到375psi并把组件冷却到室温。
用于有效的无空隙层叠的特定过程将与为特定应用而选择的粘合剂的要求有关。本领域内的技术人员受益于本发明所揭示的内容,可预想本发明范围内的其它层叠工艺。例如,在高温层叠后,可把压强减小到零来制造层叠的组件,但对于给定的粘合剂通常必须把高温与压强保持较长的时间周期。图3示出层叠的组件。
所述的层叠工艺在层叠组件的柔性载带和粘合剂层中引入了张力。这些层具有比加强板高的热膨胀系数,从而在冷却该组件时,粘合剂层与载带层的收缩程度倾向于比加强板大,但由于这些层相互粘接从而防止这些层的收缩。加强板的强度必须足够大,以防止该组件因这些张力而弯曲或翘曲。
参考图4,可在层叠前在加强板中形成加强板52中的孔口或窗口54,或该孔口或窗口可在层叠工艺完成后形成。在本较佳实施例中,在层叠工艺完成后在加强板52中蚀刻出窗口54。在此方法中,给层叠的组件涂敷光致抗蚀剂(前和后)。使用掩模把待形成窗口的加强板的区域曝光,并冲洗光致抗蚀剂而除去窗口区域中的光致抗蚀剂。(本领域内技术人员应知道,或者也可使用负型抗蚀剂,其中掩蔽窗口而暴露加强板的其余部分。)然后,把该组件暴露于蚀刻剂,从而在已除去光致抗蚀剂的地方穿过加强板蚀刻出窗口。然后通过诸如剥离除去其余的光致抗蚀剂。通过举例,可在130华氏度采用2M HCL与氯化铜的铜蚀刻剂浴来蚀刻铜加强板。如本领域内技术人员所知,对于其它加强板材料可获得适当的蚀刻剂。可适于本领域内公知的其它蚀刻化学处理和配置。一旦把加强板一直蚀刻到粘合剂层,就对该组件进行漂洗,通过本领域内公知剥离工艺除去剩余的抗蚀剂。最好选择可抵抗蚀刻和剥离化学处理的粘合剂。因此,它基本上不受蚀刻工艺的影响,而且它在蚀刻工艺中保护了下面的柔性电路的导电迹线。与此同时,可通过对光致抗蚀剂进行适当的构图而在加强板中蚀刻出附加的开口。例如,如果要使用易折引线压缩技术(见5,489,749和5,536,909号美国专利,这里通过参考而引入)通过操作把芯片载体附着到衬底上,则可在加强板中形成窗口,从而可接近易折引线。
在较佳实施例中,一旦在加强板52中形成窗口,则因层叠工艺期间所施加的应力而使窗口区域中的其余层叠粘合剂/载带组件处于张力下。该应力的有益效果是给小片焊接区附近的柔性电路提供高的平整度。一般,虽然其它公差在所选择的应用中可能是适当的,但为了提供适当的小片附着,想要实现的平整度的变化不超过约25微米或1密尔。
在本发明的另一个实施例中,加强板可设有预先形成的窗口,且在载带/加强板层叠工艺期间,可利用隔板或台板来填充窗口空间,从而保证载带在窗口区域中的平整度。在此实施例中,可把硅酮或其它适当的材料用于隔板。
参考图5,在加强板52中形成窗口54后,可除去覆盖柔性电路50上的小片附着焊接区位置56的粘合剂58,以暴露这些位置处的金属小片附着焊接区材料。在较佳实施例中,这可使用激光烧蚀技术或本领域内公知的其它方法来进行。在除去小片焊接区上的粘合剂后,在必要时可通过诸如等离子体处理等除去组件的残留物。
这样,形成的倒装片TBGA封装可提供适当的平面柔性电路,在其上表面上具有倒装片连接焊接区,在其下表面上有BGA连接地点。在导电迹线位于柔性电路上表面上的实施例中,不需要在顶面上形成焊接掩模层来防止焊接桥接,这是因为层叠粘合剂起到焊接掩模的作用,而且也起到了把柔性电路附着于加强板的介电粘合剂的作用。
参考图6,可使用依据本发明的芯片载体,通过把芯片32上的焊接区36连到柔性电路50的导电迹线62所形成的小片附着焊接区56上(诸如通过焊接)来封装集成电路小片32。这可使用倒装片技术或本领域内公知的其它方法来进行。注意,本发明不需要在小片封装焊接区56附近加上高精度的焊接掩模,这是因为层叠粘合剂起到把小片封装层叠相互隔离的作用,而且还起到防止焊接区之间的焊接桥接的作用。可使用本领域内众所周知的方法通过通孔66把BGA焊球30附着到BGA附着焊接区64上。
为了完成该封装,可嵌入诸如环氧等底层填料,以填充小片32与粘合剂58之间的任何剩余空间,可使用密封剂来填充小片周围的空间并覆盖小片,以防止湿气和其它环境元素到达小片。依据本发明构成的封装的一个优点在于,可在安装时使得集成电路的非有源一侧从PC板面朝外,从而可在需要时使用与小片直接接触或位于小片附近的散热片。
虽然图6未按比例绘出,但它示出芯片-载带连接的密度基本上大于用来把本发明的封装连到印刷电路板的BGA焊球阵列的密度。该封装的一个目的在于使得把集成电路小片的高接触密度转换到印刷电路板的较低接触密度。本领域内技术人员可知道,可设计和制造柔性电路上的导电迹线,以在小片附着焊接区56与BGA焊球30之间形成想要的导电连接。在本发明的另一个实施例中,粘合剂58可以是各向异性的导电粘合剂,它沿垂直方向是导电的,而沿水平方向是绝缘的(如图所示)。(例如,见3M所拥有的5,686,703和5,143,785号美国专利,这里通过参考而引入。)这种粘合剂是如此构成的,从而在热力和压强下压缩该粘合剂而形成粘接时,树脂中所分配的小导电颗粒陷落在小片焊接区与接触焊接区之间,且受压而在小片焊接区与接触焊接区之间形成电气触点。粘合剂固化,从而使颗粒陷落在适当的位置。这种粘接不需要金属回流,继而可在低于界面冶金术的熔点的温度下形成层叠。
在这一实施例中,不需要在小片附着层叠56上的粘合剂58中形成孔,且芯片32与柔性电路之间不需要焊接。取而代之,把芯片32在小片附着焊接区56上对准,并通过粘合剂58固定在适当的位置。粘合剂的各向异性导电特性用于在芯片上的焊接区36与柔性电路上的相应小片附着焊接区56之间形成连接,而在相邻的焊接区之间不形成导电路径。该技术避免了对底层填料的需要,这是因为芯片32与粘合剂58之间没有空间。本领域内技术人员可知道,在本实施例中,加强板52必须是不导电的,否则必须在粘合剂与加强板52之间设置绝缘层,以防止在导电迹线62与加强板52之间形成电流路径。
图7A到7E示出依据本发明制造芯片载体的一个示例方法,其中小片附着焊接区较厚,因此这些焊接区在柔性衬底上的高度比衬底上的导电电路的其余部分高。此结构提供了以下所述的几个优点。
参考图7A,所示的柔性BGA电路70具有其上形成导电迹线62的衬底60,它可以是聚酰亚胺载带。可在载带中形成通孔66,以使位于载带底部的焊球可导电地连接到导电迹线图案62中所形成的焊球焊接区64。可使用本说明书中所述或本领域内公知的方法和材料来形成此柔性电路。在所示的实施例中,形成的小片附着焊接区72较厚,从而其在衬底60上的高度比导电迹线图案62的其它部分高。形成较厚焊接区的一个方法是以普通的方式形成导电迹线,然后添加经构图的光致抗蚀剂,从而仅把小片附着焊接区暴露于附加的金属化工艺(诸如电镀或无电镀敷,但不限于此)。在3,930,857号美国专利中揭示了形成较厚焊接区的另一个方法,该专利在这里通过参考而引入。
在如前一段所述形成柔性电路后,可如图7B所示及以上结合图2和3所述,使用粘合剂层58把该柔性电路层叠到加强板52上。如图7C所示,可在加强板52中形成窗口,以暴露位于柔性电路上的抬高的小片附着焊接区72所在的区域。以上结合图4描述了形成窗口的方法。接着,可从窗口54的区域均匀地除去一部分粘合剂层58,从而暴露了抬高的小片附着焊接区,但其它导电迹线仍旧被粘合剂58所覆盖。例如,可把加强板52用作掩模,通过例如等离子体蚀刻除去粘合剂。由于将要暴露的这部分导电迹线62(小片附着焊接区72)被抬高,所以不必如先前的实施例所述仅仅选择性地除去焊接区上的粘合剂。因而,该实施例以非选择性蚀刻步骤替代了激光烧蚀或其它高精度粘合剂除去步骤,这是因为不必对粘合剂进行构图。此操作提供了图7D所示的结构,而相邻的小片附着焊接区72之间的位置留下粘合剂,以防止回流操作期间的焊接桥接。最后,图7E示出获得的芯片载体结构,集成电路32通过焊球34附着到小片附着焊接区72时,而且BGA焊球30通过通孔66附着到BGA焊接区64上。
参考图8,现在将描述依据本发明构成的“电路在外”芯片载体的一个实施例。在本实施例中,导电迹线位于柔性衬底离加强板的另一侧。在图中,所示的导电迹线82位于柔性载带60的底部。迹线包括焊球84和小片附着焊接区86。在柔性载带60中形成通孔88,从而可使用倒装片方法把集成电路小片附着到小片附着焊接区86上。可通过激光烧蚀、构图蚀刻或本领域内公知的其它方法形成通孔。把焊接掩模层90加到柔性电路的底部,以覆盖导电迹线并使焊球焊接区84相互分离,从而防止回流操作期间的焊接桥接。焊球焊接区84的间距基本上大子小片附着焊接区86的间距,从而可使用常规的方法来加上构图的焊接掩模。
在制造如图8烧蚀的芯片载体期间,可使用粘合剂58把加强板52层叠到柔性电路衬底60上,接着可使用上述方法在加强板52中形成窗口54。可完全或部分地除去窗口54区域中的粘合剂58,或者可留下适当位置处的粘合剂。可形成通孔808,这些通孔808穿透衬底60以及任何剩余的粘合剂58。
鉴于本说明书,本发明的进一步修改和其它实施例将对本领域内技术人员变得明显起来。相应地,将认为本说明书只是示意性的,而且是为了使本领域内的技术人员知道实施本发明的方式。应理解,这里所示和所描述的形式被用作当前的较佳实施例。可对各部件的形状、尺寸和配置进行变化。例如,可使用等效的元件来替代这里所示和所描述的元件,可独立于其它特征的使用而利用本发明的某些特征,这些将对本领域内技术人员(受益于本发明的说明书后)变得明显起来。
Claims (10)
1.一种用于集成电路小片的封装部件,其特征在于包括:
一层柔性介电载带,在其第一侧上形成选中的导电迹线图案,所述导电迹线具有小片附着焊接区和焊球网格阵列附着焊接区;
在所述载带中形成的开口,从而暴露位于载带第二侧上的所述焊球网格阵列附着焊接区;
覆盖载带的所述第一侧及其上形成的导电迹线的一层介电粘合剂;
在所述介电粘合剂层中形成的开口,从而暴露所述小片附着焊接区;以及
附着到这层介电粘合剂的加强板,在所述加强板中形成一窗口,从而暴露所述小片附着焊接区。
2.一种用于集成电路小片的封装部件,其特征在于包括:
一层柔性介电载带,其上形成选中的导电迹线图案;
覆盖载带的第一侧及其上形成的导电迹线的一层介电粘合剂;
在所述介电粘合剂层中形成的开口,从而暴露所述小片附着焊接区,把所述粘合剂留在焊接区之间的适当位置;以及
附着到这层介电粘合剂的加强板,在所述加强板中形成一窗口,从而暴露所述小片附着焊接区。
3.如权利要求1或2所述的封装部件,其特征在于粘合剂层包括聚酰亚胺粘合剂。
4.如权利要求1或2所述的封装部件,其特征在于柔性载带包括聚酰亚胺载带。
5.如权利要求1或2所述的封装部件,其特征在于在介电载带的两侧上形成导电迹线。
6.如权利要求1或2所述的封装部件,其特征在于小片附着焊接区从柔性介电载带比其它导电迹线延伸得更远。
7.如权利要求1或2所述的封装部件,其特征在于介电粘合剂是各向异性粘合剂。
8.一种封装集成电路,其特征在于包括如权利要求1的封装部件,还包括:
置于载带第二侧上的多个焊球,通过载带中形成的开口把这些焊球附着到焊球网格阵列附着焊接区;以及
置于加强板中所形成的窗口内且操作地附着于小片附着焊接区的集成电路小片。
9.如权利要求8所述的封装集成电路,其特征在于使用倒装片技术把集成电路小片附着到小片附着焊接区。
10.一种用于制造集成电路的封装部件的方法,其特征在于包括:
提供一柔性介电载带,其上形成选中的导电迹线图案,所述导电迹线包括小片附着焊接区和焊球网格阵列附着焊接区;
把一层介电粘合剂加到所述载带的第一侧;
使用此粘合剂把一加强板层叠到所述载带;
在所述加强板中形成一窗口,从而暴露小片附着焊接区所在的载带和粘合剂的一部分;以及
除去覆在所述小片附着焊接区上的粘合剂。
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Also Published As
Publication number | Publication date |
---|---|
EP1082762A1 (en) | 2001-03-14 |
JP2003522401A (ja) | 2003-07-22 |
WO1999057764A1 (en) | 1999-11-11 |
US6140707A (en) | 2000-10-31 |
CA2329441A1 (en) | 1999-11-11 |
KR20010072583A (ko) | 2001-07-31 |
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