GB2292003A - Direct chip attach - Google Patents

Direct chip attach Download PDF

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Publication number
GB2292003A
GB2292003A GB9415296A GB9415296A GB2292003A GB 2292003 A GB2292003 A GB 2292003A GB 9415296 A GB9415296 A GB 9415296A GB 9415296 A GB9415296 A GB 9415296A GB 2292003 A GB2292003 A GB 2292003A
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GB
United Kingdom
Prior art keywords
circuit
electronic
electronic circuit
electronic component
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9415296A
Other versions
GB9415296D0 (en
Inventor
Katherine Margaret Medlock
Anthony R Cowburn
Clive Peter Savage
William M Morgan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Havant International Group Ltd
HAVANT INT GROUP Ltd
Seagate Systems UK Ltd
IBM United Kingdom Ltd
Original Assignee
Havant International Group Ltd
HAVANT INT GROUP Ltd
IBM United Kingdom Ltd
Havant International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Havant International Group Ltd, HAVANT INT GROUP Ltd, IBM United Kingdom Ltd, Havant International Ltd filed Critical Havant International Group Ltd
Priority to GB9415296A priority Critical patent/GB2292003A/en
Publication of GB9415296D0 publication Critical patent/GB9415296D0/en
Priority to PCT/GB1995/001784 priority patent/WO1996004681A1/en
Priority to AU31192/95A priority patent/AU3119295A/en
Publication of GB2292003A publication Critical patent/GB2292003A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The area required for wirebond direct chip attach on a flexible substrate 30 is reduced by countersinking the chip 10. A spacer layer 70 or an indentation in a heatsink 20 may be used to recess a chip 10 relative to a flexible substrate 30. This enables shorter wirebonds 40 and less encapsulation 60 to be employed. A protection layer 50 is applied over a wiring pattern carried by the substrate 30. <IMAGE>

Description

DIRECT CHIP ATTACH The present invention relates to the direct attachment of chips or other electronic circuit components to electronic circuits. More specifically the present invention relates to a method of saving space on flexible direct chip attach circuits.
Since the increase in the use of electronic circuits and computers, considerable effort has been directed into optimising the packaging of electronic circuits and components.
US-A-5,173,844 describes a circuit board having a metal substrate.
According to one embodiment, the substrate is made thin by mounting an electronic component in a recessed portion formed on the metal substrate.
In this way, part of the electronic component is contained in an inner portion of the metal substrate. The purpose of this structure is to enable a packaged circuit board to be made thinner. This arrangement depends on having a metal substrate for coping with heat dissipation.
EP-A-101,791 discloses a multi-layer circuit constructed from a metal or alloy substrate having a cavity on one surface. An electronic element is positioned in the cavity and may be connected to a second electronic element on the surface. A dielectric layer covers the first electronic element and a conductive circuit pattern overlies this layer.
This circuit pattern also has a cavity for receiving the second electronic element. This arrangement also incorporates a metal or alloy substrate to aid heat dissipation. With such an arrangement it will be difficult to remove/replace a circuit component which has been totally encapsulated within the multilayer circuit. The components are stacked in this way to reduce the number of interconnections required and also to reduce manufacturing expense.
W0-81/01784 describes a recessed circuit module. The circuit module is a dielectric ceramic substrate with a recess for an electrical device. This arrangement prevents an excessive increase in the thickness of the circuit module and depends on the heat conductivity properties of the ceramic substrate for heat dissipation.
GB-A-1,429,078 discloses-a component wafer for an electrical circuit packaging structure. The component wafer llas a base member of insulating material which is provided with a component receiving cavity.
The component is totally within the base member and is hermetically sealed within the cavity. This technique allows wafers to be stacked.
Wirebond direct chip attach (DCA) technology on flex has been used extensively on dynamic flexible circuits for many years. In the early years this solution was adopted to minimise the space required on the circuit for active devices and maximise their heatsinking. The ever increasing demand for more storage capacity and more compact hardware has pushed the wirebond DCA to its limits. None of the prior art addresses the problem of reducing the amount of "real estate" or area required to connect a chip. Furthermore, the prior art does not refer to the specialised area of flexible circuits.
The present invention discloses a method for reducing the potential area required for wirebond DCA with no impact to the heatsinking capacity of the circuit. This allows chips and components to be mounted closer together without degrading heat dissipation.
Accordingly, viewed from one aspect the present invention provides an electronic circuit comprising: a flexible substrate having an electrically conductive circuit pattern formed thereon; an electronic component attached to the electronic circuit and electrically connected by wirebonds to the circuit pattern on the flexible substrate; a heatsink in thermal connection with the electronic component; characterised in that the electronic component is located in a recess in the electronic circuit thereby reducing the area required for locating and connecting the electronic component on the electronic circuit.
An advantage of the invention is that the wireability of the surrounding circuitry is improved as a result of the reduced surface area requirement for chip and wire. This results in cost reductions due to the simplification of the circuit and improved manufacturability.
Reductions in the level of interconnections, either by reducing the number of circuit layers or by removing the need to eiectricaliy connect a hybrid to a circuit substrate lead to improvements in reliability.
Furthermore the reduction in overall wirebond length could improve electrical performance.
"Countersinking" the chip means that significant space can be saved in the electronic design of a DCA wirebond circuit. By countersinking the chip it is possible to better control the flow of encapsulant over the chip and wirebond structure and to reduce the required wirebond length from about 1.OOmm to 0.5mm or less.
The present invention seeks to solve the problem of restricted space on flexible circuits by reducing the necessary "footprint" i.e.
area required to locate and connect up a component. It allows more space without having to cope with finer circuit lines and without having multilayered circuits (with stacked components).
In order that the invention may be fully understood preferred embodiments thereof will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows an example of wirebond DCA structure in accordance with the prior art; and Figure 2 shows a wirebond DCA structure in accordance with the present invention.
With reference to Figure 1, a chip or other electronic circuit component 10 is attached to a heatsink 20 by adhesive and electrically connected to wire bond pads of a circuit wiring pattern on the flexible substrate 30 by means of wirebonds 40. The wiring pattern may be formed by ethching, printing or any other method of laying down a circuit wiring. A cover layer 50 protects the circuit wiring pattern. The chip and its wirebonds are encapsulated 60 for protection.
The distance "a", shown in Figure 1, is the required distance from the chip wire bond pad to the flex wire bond pad on the circuit wiring pattern. This is made necessary by the design of the bond head on the wirebond tool. A typical minimum measurement of this distance is l.OOmm.
(The dimensions given herein are only examples and should not be used to restrict the scope of the invention).
The distance "b" is the distance from the flex outer lead bond to the edge of the encapsulant. This distance results from the difficulty in controlling the flow of encapsulant over the chip surface around the wirebonds and beyond. The encapsulant is required to mechanically protect the chip and wirebonds for the lifetime of the product. The extent of this flow is generally assumed to be up to 2mm.
This example is typical and the dimensions given are those of a flexible circuit manufactured with a 3.3mm square chip. The encapsulation in this example typically extends to a square having a side of about lOmm.
Figure 2 shows the improvement to the known structure using a "countersunk" chip. The chip 10 (or other circuit component) is adhered to a heatsink 20 which may be made from aluminium or any other material having good heat dissipation characteristics. To retain the flexibility of the circuit, the heatsink covers only the electronic component and not the whole circuit. A spacer layer 70 separates the circuit wiring pattern 30 from the heatsink. Preferably the thickness of the spacer layer is at about the same height of the chip 10. This enables the length of the bonding wires 40 to be kept short. A cover protection layer 50 and encapsulant 60 protect the chip and circuit.
The distances "a" and "b" are as in Figure 1. As can be seen, these distances are significantly smaller than the corresponding ones in Figure 1. The length of the wirebond has been reduced to 0.5mm and the flow of the encapsulant beyond the outer lead bond has been held at 0.25mm.
The improved dimensions have been achieved by countersinking the chip i.e. by adding a spacer between the flex and the heatsink to ensure the chip is ether level with or slightly below the surface of the flex.
This allows wirebonds to be significantly shorter, typically 0.5mm compared to a minimum of l.Omm when the chip stands above the flex circuit.
In accordance with another embodiment of the invention (not shown), an indentation is made in the heatsink and the electronic component is located therein.
Due to the topography of the whole structure the encapsulation flow can also be controlled more easily and accurately. The cover layer of the flexible circuit acts a dam to the encapsulation. Typically the total flow over a 3.3mm square chip using the countersinking technique extends to a glob of approximately 4.8 x 4.8mm square. Whereas prior art techniques have produced a glob of 10 x 10 mm square.

Claims (8)

1. An electronic circuit comprising: a flexible substrate having an electrically conductive circuit pattern formed thereon; an electronic component attached to the electronic circuit and electrically connected by wirebonds to the circuit pattern on the flexible substrate; a heatsink in thermal connection with the electronic component; characterised in that the electronic component is located in a recess in the electronic circuit thereby reducing the area required for locating and connecting the electronic component on the electronic circuit.
2. An electronic circuit as claimed in claim 1 wherein the recess is formed by a spacer layer between the flexible substrate and the heatsink.
3. An electronic circuit as claimed in claim 1 wherein the recess is formed by an indentation in the heatsink.
4. An electronic circuit as claimed in any preceding claim wherein the depth of the recess is substantially equal to the height of the electronic component.
5. An electronic circuit as claimed in any preceding claim wherein the circuit pattern is coated with a non-conductive cover layer.
6. An electronic circuit as claimed in any preceding claim wherein the electronic component is encapsulated with a non-conductive protective material.
7. An electronic circuit substantially as hereinbefore described and with reference to figure 2.
8. A method of manufacturing an electronic circuit comprising: providing a flexible substrate having an electrically conductive circuit pattern formed thereon; attaching an electronic component to the electronic circuit and electrically connecting it, by wirebonds, to the circuit pattern on the flexible substrate; providing a heatsink in thermal connection with the electronic component; characterised by providing a recess in the electronic circuit locating the electronic component in the recess in the electronic circuit thereby reducing the area required for locating and connecting the electronic component on the electronic circuit.
GB9415296A 1994-07-29 1994-07-29 Direct chip attach Withdrawn GB2292003A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9415296A GB2292003A (en) 1994-07-29 1994-07-29 Direct chip attach
PCT/GB1995/001784 WO1996004681A1 (en) 1994-07-29 1995-07-27 Direct chip attach
AU31192/95A AU3119295A (en) 1994-07-29 1995-07-27 Direct chip attach

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9415296A GB2292003A (en) 1994-07-29 1994-07-29 Direct chip attach

Publications (2)

Publication Number Publication Date
GB9415296D0 GB9415296D0 (en) 1994-09-21
GB2292003A true GB2292003A (en) 1996-02-07

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GB9415296A Withdrawn GB2292003A (en) 1994-07-29 1994-07-29 Direct chip attach

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AU (1) AU3119295A (en)
GB (1) GB2292003A (en)
WO (1) WO1996004681A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package

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GB9415296D0 (en) 1994-09-21
WO1996004681A1 (en) 1996-02-15

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