CN1261979C - 下层块金属的阻挡层盖 - Google Patents

下层块金属的阻挡层盖 Download PDF

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Publication number
CN1261979C
CN1261979C CNB021230404A CN02123040A CN1261979C CN 1261979 C CN1261979 C CN 1261979C CN B021230404 A CNB021230404 A CN B021230404A CN 02123040 A CN02123040 A CN 02123040A CN 1261979 C CN1261979 C CN 1261979C
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China
Prior art keywords
layer
solder
metal
barrier
attachable
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Expired - Fee Related
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CNB021230404A
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English (en)
Chinese (zh)
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CN1391261A (zh
Inventor
周洋明
葛以廉
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Advanced Interconnect Technology Ltd
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Advanced Interconnect Technology Ltd
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Publication of CN1391261A publication Critical patent/CN1391261A/zh
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNB021230404A 2001-06-12 2002-06-12 下层块金属的阻挡层盖 Expired - Fee Related CN1261979C (zh)

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US09/878,271 US6413851B1 (en) 2001-06-12 2001-06-12 Method of fabrication of barrier cap for under bump metal

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Families Citing this family (153)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US6303423B1 (en) 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6869870B2 (en) * 1998-12-21 2005-03-22 Megic Corporation High performance system-on-chip discrete components using post passivation process
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
JP2003045877A (ja) * 2001-08-01 2003-02-14 Sharp Corp 半導体装置およびその製造方法
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US6926818B1 (en) * 2001-09-24 2005-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method to enhance the adhesion between dry film and seed metal
US6768210B2 (en) * 2001-11-01 2004-07-27 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
DE10156054C2 (de) * 2001-11-15 2003-11-13 Infineon Technologies Ag Herstellungsverfahren für eine Leiterbahn auf einem Substrat
JP3875077B2 (ja) * 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
US6696356B2 (en) * 2001-12-31 2004-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate without ribbon residue
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
TW518700B (en) * 2002-01-07 2003-01-21 Advanced Semiconductor Eng Chip structure with bumps and the manufacturing method thereof
JP3687610B2 (ja) * 2002-01-18 2005-08-24 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
TW531869B (en) * 2002-02-27 2003-05-11 Advanced Semiconductor Eng Manufacturing process of lead-free soldering bump
US6930032B2 (en) * 2002-05-14 2005-08-16 Freescale Semiconductor, Inc. Under bump metallurgy structural design for high reliability bumped packages
US6596621B1 (en) * 2002-05-17 2003-07-22 International Business Machines Corporation Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
TW558821B (en) * 2002-05-29 2003-10-21 Via Tech Inc Under bump buffer metallurgy structure
TW558809B (en) * 2002-06-19 2003-10-21 Univ Nat Central Flip chip package and process of making the same
US6774026B1 (en) * 2002-06-20 2004-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for low-stress concentration solder bumps
WO2004001837A2 (en) 2002-06-25 2003-12-31 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ｕｂｍ의형성방법
TWI281718B (en) * 2002-09-10 2007-05-21 Advanced Semiconductor Eng Bump and process thereof
TWI291210B (en) * 2002-09-10 2007-12-11 Advanced Semiconductor Eng Under-bump-metallurgy layer
US6750133B2 (en) * 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
US6893799B2 (en) * 2003-03-06 2005-05-17 International Business Machines Corporation Dual-solder flip-chip solder bump
US6858943B1 (en) * 2003-03-25 2005-02-22 Sandia Corporation Release resistant electrical interconnections for MEMS devices
CN1291069C (zh) * 2003-05-31 2006-12-20 香港科技大学 微细间距倒装焊凸点电镀制备方法
US6835580B1 (en) * 2003-06-26 2004-12-28 Semiconductor Components Industries, L.L.C. Direct chip attach structure and method
US20050026416A1 (en) * 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
TWI242866B (en) * 2003-08-21 2005-11-01 Siliconware Precision Industries Co Ltd Process of forming lead-free bumps on electronic component
US7276801B2 (en) * 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
JP2005116632A (ja) 2003-10-03 2005-04-28 Rohm Co Ltd 半導体装置の製造方法および半導体装置
US6933171B2 (en) * 2003-10-21 2005-08-23 Intel Corporation Large bumps for optical flip chips
US20050151268A1 (en) * 2004-01-08 2005-07-14 Boyd William D. Wafer-level assembly method for chip-size devices having flipped chips
TWI254995B (en) * 2004-01-30 2006-05-11 Phoenix Prec Technology Corp Presolder structure formed on semiconductor package substrate and method for fabricating the same
US7910471B2 (en) * 2004-02-02 2011-03-22 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
TWI241001B (en) * 2004-03-26 2005-10-01 Advanced Semiconductor Eng Method of improving adhesive characteristic between photoresist layer and substrate, and bumping process
TW200603698A (en) * 2004-04-13 2006-01-16 Unitive International Ltd Methods of forming solder bumps on exposed metal pads and related structures
JP4327657B2 (ja) * 2004-05-20 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
US8390131B2 (en) * 2004-06-03 2013-03-05 International Rectifier Corporation Semiconductor device with reduced contact resistance
US7678680B2 (en) * 2004-06-03 2010-03-16 International Rectifier Corporation Semiconductor device with reduced contact resistance
TWI313051B (en) * 2004-06-10 2009-08-01 Advanced Semiconductor Eng Method and structure to enhance height of solder ball
US20060003580A1 (en) * 2004-06-30 2006-01-05 Goh Hun S Under bump metallurgy process on passivation opening
US7208830B2 (en) * 2004-06-30 2007-04-24 Intel Corporation Interconnect shunt used for current distribution and reliability redundancy
DE102004032677B4 (de) * 2004-07-02 2008-07-10 Qimonda Ag Verfahren zum Herstellen einer Maske auf einem Substrat
US7226857B2 (en) * 2004-07-30 2007-06-05 Micron Technology, Inc. Front-end processing of nickel plated bond pads
US20060182993A1 (en) * 2004-08-10 2006-08-17 Mitsubishi Chemical Corporation Compositions for organic electroluminescent device and organic electroluminescent device
JP4718809B2 (ja) * 2004-08-11 2011-07-06 ローム株式会社 電子装置およびそれを用いた半導体装置、ならびに半導体装置の製造方法
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7355282B2 (en) 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
DE102004047730B4 (de) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen
TWI252546B (en) * 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP4822694B2 (ja) * 2004-11-22 2011-11-24 京セラ株式会社 半導体素子及び半導体素子実装基板
DE102005004360A1 (de) * 2005-01-31 2006-08-17 Advanced Micro Devices, Inc., Sunnyvale Effizientes Verfahren zum Herstellen und Zusammenfügen eines mikroelektronischen Chips mit Lothöckern
TWI304234B (en) * 2005-03-04 2008-12-11 Int Rectifier Corp Semiconductor package fabrication
JP2006278551A (ja) * 2005-03-28 2006-10-12 Fujitsu Ltd 半導体装置及びその製造方法
US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
CN100428414C (zh) * 2005-04-15 2008-10-22 中芯国际集成电路制造(上海)有限公司 形成低应力多层金属化结构和无铅焊料端电极的方法
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7560813B2 (en) * 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7942182B2 (en) 2005-06-14 2011-05-17 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
KR20060131327A (ko) * 2005-06-16 2006-12-20 엘지전자 주식회사 발광 다이오드의 제조 방법
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7053490B1 (en) * 2005-07-27 2006-05-30 Semiconductor Manufacturing International (Shanghai) Corporation Planar bond pad design and method of making the same
US8148822B2 (en) 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
US8399989B2 (en) * 2005-07-29 2013-03-19 Megica Corporation Metal pad or metal bump over pad exposed by passivation layer
US8063495B2 (en) * 2005-10-03 2011-11-22 Rohm Co., Ltd. Semiconductor device
US7205673B1 (en) * 2005-11-18 2007-04-17 Lsi Logic Corporation Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US8143722B2 (en) * 2006-10-05 2012-03-27 Flipchip International, Llc Wafer-level interconnect for high mechanical reliability applications
TWI360211B (en) * 2006-10-05 2012-03-11 Flipchip Int Llc Wafer-level interconnect for high mechanical relia
JP4980709B2 (ja) * 2006-12-25 2012-07-18 ローム株式会社 半導体装置
JP2008159948A (ja) * 2006-12-25 2008-07-10 Rohm Co Ltd 半導体装置
US7670874B2 (en) * 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
US7713860B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump on I/O pad
US7952207B2 (en) * 2007-12-05 2011-05-31 International Business Machines Corporation Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening
US8304909B2 (en) * 2007-12-19 2012-11-06 Intel Corporation IC solder reflow method and materials
US8232655B2 (en) * 2008-01-03 2012-07-31 International Business Machines Corporation Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack
US20100032194A1 (en) * 2008-08-08 2010-02-11 Ibiden Co., Ltd. Printed wiring board, manufacturing method for printed wiring board and electronic device
TWI473221B (zh) * 2008-09-05 2015-02-11 欣興電子股份有限公司 封裝基板及其製法
US20100096750A1 (en) * 2008-10-21 2010-04-22 Phoenix Precision Technology Corporation Packaging substrate
FR2940521B1 (fr) 2008-12-19 2011-11-11 3D Plus Procede de fabrication collective de modules electroniques pour montage en surface
US7915741B2 (en) * 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure
US8689437B2 (en) * 2009-06-24 2014-04-08 International Business Machines Corporation Method for forming integrated circuit assembly
US9543262B1 (en) 2009-08-18 2017-01-10 Cypress Semiconductor Corporation Self aligned bump passivation
US8445375B2 (en) 2009-09-29 2013-05-21 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component
TWI445147B (zh) * 2009-10-14 2014-07-11 日月光半導體製造股份有限公司 半導體元件
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
US8569887B2 (en) * 2009-11-05 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect with oxidation prevention layer
JP2011165862A (ja) * 2010-02-09 2011-08-25 Sony Corp 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
US8993431B2 (en) * 2010-05-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure
US8405199B2 (en) * 2010-07-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar for semiconductor substrate and method of manufacture
TWI478303B (zh) 2010-09-27 2015-03-21 日月光半導體製造股份有限公司 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
IT1402530B1 (it) 2010-10-25 2013-09-13 St Microelectronics Srl Circuiti integrati con retro-metallizzazione e relativo metodo di produzione.
TWI451546B (zh) 2010-10-29 2014-09-01 日月光半導體製造股份有限公司 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US8298930B2 (en) * 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
US20120175772A1 (en) * 2011-01-07 2012-07-12 Leung Andrew K Alternative surface finishes for flip-chip ball grid arrays
JP2012204788A (ja) * 2011-03-28 2012-10-22 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8564030B2 (en) 2011-06-10 2013-10-22 Advanced Micro Devices Self-aligned trench contact and local interconnect with replacement gate process
US8716858B2 (en) 2011-06-24 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure with barrier layer on post-passivation interconnect
US8716124B2 (en) 2011-11-14 2014-05-06 Advanced Micro Devices Trench silicide and gate open with local interconnect with replacement gate process
US9613914B2 (en) 2011-12-07 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure
CN103531529B (zh) * 2012-07-04 2016-02-03 颀邦科技股份有限公司 半导体工艺
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
JP6155571B2 (ja) 2012-08-24 2017-07-05 Tdk株式会社 端子構造、並びにこれを備える半導体素子及びモジュール基板
JP6015240B2 (ja) 2012-08-24 2016-10-26 Tdk株式会社 端子構造及び半導体素子
JP6326723B2 (ja) 2012-08-24 2018-05-23 Tdk株式会社 端子構造及び半導体素子
EP2709160B1 (en) * 2012-09-14 2016-03-30 ATOTECH Deutschland GmbH Method for metallization of solar cell substrates
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US9620468B2 (en) * 2012-11-08 2017-04-11 Tongfu Microelectronics Co., Ltd. Semiconductor packaging structure and method for forming the same
CN103094428A (zh) * 2013-01-30 2013-05-08 合肥彩虹蓝光科技有限公司 Led自对准粗化制程方法
KR20140100144A (ko) * 2013-02-05 2014-08-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9837291B2 (en) 2014-01-24 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer processing method and apparatus
TWI551199B (zh) * 2014-04-16 2016-09-21 矽品精密工業股份有限公司 具電性連接結構之基板及其製法
US9576827B2 (en) 2014-06-06 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for wafer level bonding
US9520375B2 (en) * 2015-04-30 2016-12-13 International Business Machines Corporation Method of forming a solder bump on a substrate
CN105140140B (zh) * 2015-07-16 2018-07-13 北京工业大学 一种晶圆级焊锡微凸点的制作方法
CN105097576B (zh) * 2015-07-16 2018-07-06 北京工业大学 一种高可靠性晶圆级焊锡微凸点制作方法
US9780052B2 (en) * 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
TWI572257B (zh) * 2015-10-19 2017-02-21 欣興電子股份有限公司 柱狀結構及其製作方法
US9875979B2 (en) * 2015-11-16 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive external connector structure and method of forming
DE102016103585B4 (de) * 2016-02-29 2022-01-13 Infineon Technologies Ag Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt
JP6713809B2 (ja) * 2016-03-31 2020-06-24 株式会社荏原製作所 基板の製造方法及び基板
KR102601553B1 (ko) 2016-12-08 2023-11-15 삼성전자주식회사 반도체 발광 소자
CN108695289B (zh) * 2017-04-05 2020-04-10 中芯国际集成电路制造(北京)有限公司 一种半导体器件及其制作方法、电子装置
US11244918B2 (en) * 2017-08-17 2022-02-08 Semiconductor Components Industries, Llc Molded semiconductor package and related methods
US11011483B2 (en) * 2018-02-21 2021-05-18 Texas Instruments Incorporated Nickel alloy for semiconductor packaging
JP7430481B2 (ja) * 2018-05-31 2024-02-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2020047775A (ja) * 2018-09-19 2020-03-26 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法および半導体装置
CN111508919A (zh) 2019-01-31 2020-08-07 联华电子股份有限公司 半导体装置及半导体装置的制作方法
CN109979834A (zh) * 2019-03-29 2019-07-05 颀中科技（苏州）有限公司 用于半导体封装的凸块制造方法
WO2021163823A1 (en) * 2020-02-17 2021-08-26 Yangtze Memory Technologies Co., Ltd. Hybrid wafer bonding method and structure thereof
US11302537B2 (en) * 2020-04-01 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with conductive adhesive layer and method for forming the same
CN111938635B (zh) * 2020-08-10 2024-11-05 中国科学院上海微系统与信息技术研究所 脑电极后端连接用凸点、测试板的制备方法及测试结构
CN114823353A (zh) * 2022-04-12 2022-07-29 中国电子科技集团公司第二十研究所 一种玻璃基板的bga工艺器件制作方法
CN116313834B (zh) * 2023-05-24 2023-09-12 江西兆驰半导体有限公司 晶圆级封装方法及晶圆级封装结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3152796B2 (ja) * 1993-05-28 2001-04-03 株式会社東芝 半導体装置およびその製造方法
US5393697A (en) * 1994-05-06 1995-02-28 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US5851911A (en) * 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
FI962277A0 (fi) * 1996-05-31 1996-05-31 Elcoteq Network Oy Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar
KR100219806B1 (ko) * 1997-05-27 1999-09-01 윤종용 반도체장치의 플립 칩 실장형 솔더 범프의 제조방법, 이에 따라 제조되는 솔더범프 및 그 분석방법
US5990547A (en) * 1998-03-02 1999-11-23 Motorola, Inc. Semiconductor device having plated contacts and method thereof
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US6175160B1 (en) * 1999-01-08 2001-01-16 Intel Corporation Flip-chip having an on-chip cache memory
US6085968A (en) * 1999-01-22 2000-07-11 Hewlett-Packard Company Solder retention ring for improved solder bump formation
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal

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