CN1186801C - 在电镀的控制熔塌芯片连接焊料突头存在下改进的钛钨合金腐蚀方法 - Google Patents

在电镀的控制熔塌芯片连接焊料突头存在下改进的钛钨合金腐蚀方法 Download PDF

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CN1186801C
CN1186801C CNB981236731A CN98123673A CN1186801C CN 1186801 C CN1186801 C CN 1186801C CN B981236731 A CNB981236731 A CN B981236731A CN 98123673 A CN98123673 A CN 98123673A CN 1186801 C CN1186801 C CN 1186801C
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solution
scolder
metal
substrate
value
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CN1221808A (zh
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L·D·戴维
L·A·范提
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International Business Machines Corp
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International Business Machines Corp
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Abstract

一种有被保护金属存在时金属薄膜的化学湿法腐蚀方法及腐蚀剂溶液。所述的腐蚀溶液的pH值范围约为2.7-4.0。所述的腐蚀溶液包含过氧化氢、硫酸钾和乙二胺四乙酸钾，所述溶液减少或消除了耐蚀金属的出现，同时又不使被保护金属受损害。

Description

在电镀的C4焊料突头存在下改进的 钛-钨合金腐蚀方法
本发明涉及在半导体应用方面，通常是带有伸出部件的情况下，化学湿法腐蚀金属薄膜的方法。具体地说，本发明描述了一种腐蚀溶液的pH值范围，所述的溶液可在半导体基片或晶片上存在有电镀的C4型焊料突点时，完成对金属薄膜的均匀一致的腐蚀。所述的金属薄膜可由钛钨合金(TiW)制成。
可控的塌落芯片连接(C4)是一种先进的微电子芯片封装及连接技术。C4也以“焊料突点”技术和“倒装法”为人所知。C4的基本思路是用位于组件两表面间的焊球，实现芯片、芯片组件或其它类似组件间的连接。这些细小且导电的焊料球可将需连接的组件上对应成对的金属焊点间的间隙连接起来。每一个焊点在另一组件表面上存在一相对应的焊点，因此，焊点的布置是镜象的。当各组件排列对齐并置于高于焊料熔点的环境时，第一个组件焊点上的焊球熔化并和第二个组件上的对应焊点(无焊球)连接，从而实现了相应的焊点间的永久连接。
C4中，焊球通常是在组件一个表面上的金属焊点上直接形成。各焊料突点相互间被每个焊球周围的绝缘材料绝缘开来。基片可以是未掺杂的硅或其它某种材料。焊球的底部与集成电路为导电连接。当焊球与位于组件另一表面的金属焊点对齐并软熔时，液态的焊料突点会润湿此焊点。冷却时，就形成应力相对低的焊点。此技术可在一步内完成所有待连接处的连接，即使组件的表面有细微的差异也能完成。
C4的一个主要应用之处是将半导体微型芯片(集成电路)连接到芯片组件上。芯片可以矩阵列的形式分布在硅的单晶片，即“晶片”中，所述的晶片是一个通常为直径几英寸的薄圆片。每个晶片上可形成许多芯片。随后，晶片被切割成各个单独的芯片，并且这些芯片被封装在大到易以操纵的组件中。芯片仍以晶片形式存在时将C4型焊球置于芯片上。
晶片可做得尽可能大，以减少加工成一定数目的芯片所需晶片的数量。出于同样考虑以及其他原因，芯片可做得尽可能小。所以，最好的C4制造系统是能制备数以千计很小、间隔很近的焊球，其中，每个焊球可精确地置于一个大的区域上。
C4允许一个非常高密度的电互连。不象较早的技术，是围绕一个芯片或一个芯片组件的周边进行连接，C4允许芯片或组件的一个或更多的表面通过焊点进行封接。C4可能的连接数目大致是周边连接法可能连接数目的平方。因为C4焊球可做的相当小，其直径在百分之一英寸以下。C4连接点的表面密度可达每平方英寸上千个的水平。
电气工程师不断地在一个芯片中集成越来越多的电路，以改进性能和降低成本。随着芯片上电路数目的增加，所需的连接点数目也增加，与任何其它技术相比，C4允许在一个小空间存在更多的连接点，故其在商业上是重要的。
除使面间连接成为可能外，C4也可与周边连接技术如载带自动键接(TAB)一起使用。在TAB中，芯片上的焊球在粘附于芯片组件的塑料基片上的金属薄膜电路图案进行压制。这些应用也具有重要的商业价值。
C4焊料突头必须牢牢固定于基片上，否则，热应力作用下，焊料突头会失效，而热应力的产生是常规设备工作时的典型特征。一台复杂的设备如计算机可有数十个芯片以及成百上千个C4焊球接点。只要一个焊球失效，整台设备将毫无用处。因此C4焊球的固定需仔细设计。为此，各种经仔细选择的薄层被置于焊球与焊球所固定于其上的基片或晶片之间。这些面间薄层的组成和特性，通常称为焊球约束冶金(Ball LimitingMetallurgy)即BLM，在确保焊料突头与芯片间可靠的机械粘结上起主要作用。此外，这些薄层经常会在焊料与芯片上由铝和/或铜构成的冶金材料之间起扩散屏蔽作用。没有一个足够好的扩散屏障，焊料将侵蚀芯片布线并使其功能受到破坏。
有几种形成焊料突头和BLM金属的方法，其中之一是真空沉积法，此法中焊料和BLM金属在真空室里被蒸发。金属蒸汽在真空室中的所有物体上都镀覆了一薄层被蒸发金属。为在晶片或基片上形成金属焊点和焊料突点，使蒸汽从覆盖在基片上的一个金属掩模上的孔通过。蒸汽通过孔到达冷表面时凝结，形成分离的焊料突点。此方法需要一个高真空室以放置基片、掩模和闪光蒸发器。
此方法中，掩模上特别加工有高精度的孔，即“通道”，以便为焊料突头定位。当被释放进入真空室的热金属蒸汽在掩模上凝结时，该掩模将被加热。为避免出现由热膨胀引起的通道错排，掩模可由特殊金属制成，并通过几何补偿来获取最佳排列。即便采取这一措施，真空工艺也有局限。焊料沉积后，金属掩模冷却并发生热收缩。必须小心将模去掉但又不使焊点受损。所以，此方法不能在包含有许多芯片的极大型晶片上应用。
制备焊料突头的另一个方法是电解沉积，也称为电化学镀或电镀。此方法也使用一个掩模而且焊料突头只在选定的部位形成，但此法与蒸发法不同之外在于：掩模是用光学加工的方法制成。此外，此法要求第一步要制备出一个粘附于绝缘基片上导电的连续金属“底层”。底层是用来传导沉积焊料所需电流的。该底层通常由几种金属层构成，以实现额外的BLM这一冶金目的。
此方法中所用底层中的第一层包括铬(Cr)、钛钨合金(TiW)或其它任何可与现有基片牢固粘结的金属。这一金属层，其作用是作为底层的一部分实现焊球的电解沉积，其厚度可在千分之十毫米量级。第一层上面可沉积第二层金属，此金属层可以是一种铬铜合金(CrCu)或镍钒合金(NiV)。最上面是第三层，通常是纯铜，沉积于其它金属层之上。沉积层的厚度可以改变，主要是保证应力—厚度关系、扩散性能及机械完整性达到最佳。
底层制备好后，第二个基本步骤是用照相平板印刷术形成一个掩膜。一层光致抗蚀剂铺在底层上并暴露于光下，光可固化被暴露的光致抗蚀剂。未暴露的光致抗蚀剂则未被固化，故其可被冲洗掉。已固化的光致抗蚀剂则作为掩模留下来，这样制得的掩模是完整的，此完整的掩模上有成排的孔，焊料突点即沉积于此。
第三步即是将铅或其它焊料合金电解沉积(电镀)于掩模孔中。电解沉积焊料突点可高达0.25mm且含有少量锡(Sn)，这样，就能与底层中最上部的铜层牢固粘结。软熔处理时，铜和锡反应得到一种“金属间化合”层，CuxSny(如Cu3Sn)，这就在焊料与BLM间形成了一层坚硬的界面。应该指出的是，电镀过程不受与蒸发过程相同的尺寸限制，可用于尺寸很大的晶片。
焊料突头形成后，应去掉固化的光致抗蚀剂掩膜。那么，覆盖在基片上的是连续的底层和数目众多的焊料突头。
在基片上沉积完底层及形成C4突头后，应去掉处于焊料突头间的底层以保证突头间的绝缘。此去除过程可采用化学腐蚀、电化学腐蚀、或等离子腐蚀的方法完成。底层的去除使得焊料突头间相互绝缘，但仍与基片牢固连接。不管用何种方法去除底层，焊料突头始终保护其下面的金属层在处理过程中不受影响。这样，焊料突头下面的相互绝缘的BLM焊点得以制备出。最后，通过熔化或软熔就可形成焊球，进而就能将其连接到待连接的基片上。
钛钨合金(TiW，钨也称为“Wolfram”)在已有的技术中已被用作“屏蔽层”，以保护用途广泛的各种芯片。TiW是金属性的且导电。薄的TiW膜可通过采用包括溅射在内的各种传统微电子技术来获得。正如上讨论的那样，电镀法制备C4过程中，TiW作为第一层使用就是这样一个应用实例。如果使用TiW，就需要在制备中的某个阶段将其去掉。这一问题在几个专利中已有述及。
美国专利No.5,130,275阐述了半导体芯片的后制作工艺。此方法是将芯片与TAB组件焊接连接，所述的焊料是通过流动而不是压碎来实现这种连结的。此法使用一个屏蔽金属层，其含有10％Ti和90％W(重量比)，所述的屏蔽层被覆在铝(Al)或金(Au)的互连焊点上和SiO2钝化层上。铜或金的底层覆盖在所述屏蔽层上。通过将铜或金的突头电解沉积至光致抗蚀剂掩模的孔中可增加焊点上的金属层的厚度。含有锡的焊料沉积在铜或金的上面。随后，首先是底层，其次是屏蔽层被腐蚀掉，只留下制备好的焊点以备焊接使用。
底层如果由金制成，可用10％的氰化钾溶液化学腐蚀掉。所述的腐蚀剂也侵蚀突头，但该公开认为造成的突点的损害是可接受的，并证实这一损害很轻微，因为突头的厚度是25微米而底层只有0.3微米。
下一步是在浓度为30％的过氧化氢水溶液中将TiW屏蔽层腐蚀掉。该公开指出(见第37行，第8列)，过氧化物腐蚀铜/金突头顶上的焊珠。为防止这一腐蚀发生，可将溶液的pH值调整至9-11(碱性)。优选的溶液包含为7％的氧化的过硫酸铵和1％-2％的过氧化氢，通过加入氢氧化铵可将pH值调整至9-11。此腐蚀剂当然仍对铝有腐蚀。
美国专利No.5,041,191给出了一个10％Ti和90％W的屏蔽层。使用TiW层的目的是阻止当金、铜或铝接触时形成的不需要的金属间化合物直接沉积于镍-铬合金薄膜电阻器上。所述的TiW腐蚀剂为：5g的硫酸铜(CuSO4)、10ml的氢氧化铵(NH4OH)、100ml的甘油和125ml的去离子水。
依据此公开所述，此腐蚀液对镍铬合金无影响。但同前述公开5,130,275所述的腐蚀剂一样，该溶液仍是碱性的并会侵蚀铝。
美国专利No.4,671,852给出了一种腐蚀剂，用来去除一层由10％-30％钛(重量比)和90％-60％钨(重量比)组成的厚为0.05-0.10微米的薄膜，所述的腐蚀剂包括有过氧化氢、乙二胺四乙酸(EDTA)和氢氧化铵。要腐蚀的器件为具有化学敏感性的硅栅场效应晶体管(SGFET)结构，其内部有一空腔，腐蚀剂被引入此空腔，该空腔也包含一种贵金属(铂)和氧化铝或氧化硅的“过渡”层。此腐蚀剂目的是实现有选择去除TiW膜。
所述腐蚀剂为0.1摩尔的EDTA，30％的过氧化氢和浓的氢氧化铵，按各自的体积比10∶3∶2混合在一起。该公开要求溶液的pH值应小于11(不要太碱性)。除EDTA外，该公开指出还可使用其它络合剂如羧酸盐、联吡啶等，但有关这些化学试剂的配方或其它细节并未给出。此发明中的腐蚀剂也对铝有侵蚀。
美国专利No.4,814,293也给出了一种10％钛和90％钨的化学腐蚀剂。此发明指出，过氧化氢会引起不均匀腐蚀，尤其当TiW膜以层状形式处于其它金属之间时，部件会受到不规则的钻蚀或欠腐蚀。通常用的搅动法对减小这种不均匀结果毫无作用。该发明提倡使用滞止的液态腐蚀剂。将过氧化物溶液缓冲至pH值在1-6间(酸性)，优选的缓冲化合物是乙酸和乙酸铵。柠檬酸和氢氧化钠也可使用，但腐蚀速率随pH大小而变。此项发明中的溶液会严重侵蚀铅锡合金(PbSn)如焊料。而且此发明未述及存在PbSn时对TiW的选择性腐蚀。
美国专利No.4,554,050描述了制造波导管时钛腐蚀剂的使用。所述的腐蚀剂是由EDTA、水、过氧化氢和氢氧化铵组成。给出的一个配方为：2.5g的乙二胺四乙酸二钠加入100ml去离子水中(浓度0.067M)，此外还含有10g过氧化氢和4.2g氢氧化氨，其pH值约为10。
腐蚀速率可通过改变OH-浓度和温度来控制。对所述的腐蚀液分别在20℃(室温)和60℃进行了试验。此专利也指出，所述的腐蚀液腐蚀铝，并且也侵蚀PbSn。
美国专利No.5,462,638公开了用以去掉TiW薄膜的化学腐蚀剂及制备所述腐蚀剂的方法。可去掉的优选合金是沉积于基片上的10％钛和90％钨合金。铬和铜底层沉积于所述的TiW层上并形成C4焊料突头。
此处公开的腐蚀剂包含有1-2份(重量比)浓度30％的过氧化氢水溶液；1-2份浓度在15-40g/l的EDTA水溶液，此外，每升这种混合液中要加入100-200g的盐。据说所述盐的加入是通过形成保护性涂层来使所要保护的金属钝化，这样，所保护的金属就不会受到腐蚀剂的侵蚀。
前述的各种用于去除C4应用中的TiW底层的腐蚀剂成分及方法均遇到了困难，如晶片上金属的残留和焊点下严重的钻蚀。图2A和2B反映的是一个晶片2上的C4焊料突头4有残留金属12，并存在过度钻蚀区20的情形。此外，一定条件下，欲去掉的金属膜的某些部位可能变得耐腐蚀，这样不能腐蚀掉的部分金属膜就残留下来。更长的腐蚀时间也无益于这些残留物的去除。这些不足之处已妨碍了硅晶片的有效制备，或者造成其无法使用。因此，有必要提出一种能克服传统腐蚀技术之不足的改进的工艺过程。
为满足这方面以及其它方面的需要，并考虑到本发明之目的，本发明提出了一种溶液及相应的工艺过程，以实现在有需保护金属存在时，对其它金属层的化学湿法腐蚀，本腐蚀液的pH值约在2.7-4.0之间。一个优选的实施方案是在存在C4焊料突头的情况下使用所述的腐蚀剂溶液和腐蚀工艺过程。需要了解的是不论前面的一般性介绍，还是下面的具体描述都是示范性的，而本发明决不受此限制。
阅读下面的详细描述时参照相应的附图可对本发明有深入了解。需强调的是，遵循一般的作法，附图中的各个部件并未按比例绘制。相反，为使图表看起来更清楚，图中各部件的尺寸进行了随意的放大或缩小。如下各图包括在本发明附图中。
图1A是依据本发明对金属叠层腐蚀前的晶片和C4焊料突头的侧视图；
图1B是依据本发明对金属叠层中较下面金属层腐蚀前的晶片和C4焊料突头的侧视图；
图1C是依据本发明对金属叠层中较下面金属层腐蚀后的晶片和C4焊料突头的侧视图；
图2A是展示晶片上有残留金属的晶片和C4型焊料突头的侧视图；
图2B是展示金属上有钻蚀时的晶片和C4焊料突头的侧视图；
图3A是展示根据本发明所得到的均匀腐蚀的晶片和C4焊料突头的顶视图；
图3B是展示有晶界腐蚀的晶片与C4焊料突头的顶视图。
一个典型的C4结构示于图1A-1C中，各图中所反映的均是有要保护的金属存在时金属膜的去除。这一结构的构成是焊料突头(或焊点)4，它位于一个硅器件或晶片2上，中间插入一个属于料球约束冶金(BLM)的金属叠层3。焊料突头4通常包含铅/锡合金。各种各样的金属组合可用于金属叠层3，最普通的是Cr/Cu/Au。采用电镀法制备C4焊料突头时，优选的金属叠层3是一种由TiW/CrCu/Cu组成的三层叠层。C4应用中的TiW层作为金属叠层3的一部分有几个令人满意的特性，包括其粘附性能、屏蔽性能、应力特性以及与电腐蚀过程的相容性。
如上所述，C4焊料突头的制备方法有使焊料通过金属(如钼)掩模的蒸发法，电镀法或其它一些方法。如图1A-1C所示，电镀法制备C4过程中，金属叠层可沉积于一个功能硅晶片上2。所述的金属叠层3既作为通过光掩模进行焊料电沉积时的导电底层，又作为最终BLM结构的基底。金属叠层3优选包含TiW层6、CrCu层8和Cu层10。焊料的电解沉积和光掩模的去除完成后，处于焊点间的TiW/CrCu/Cu金属叠层3必须去掉，以实现互连线间的电绝缘以及形成BLM。上面的Cu层10和CrCu层8可用电化学法有效去除，只余下一薄层TiW膜6。这最后的TiW层6可用一种含过氧化氢、硫酸钾和乙二胺四乙酸钾的溶液腐蚀掉。
正如前面所指出的那样，在有PbSn的C4焊料突头存在的情况下，以前尝试采用过氧化物、硫酸钾和乙二胺四乙酸钾湿法腐蚀金属如TiW已遇到一些困难。为制备出可靠的器件和避免焊点间的短路，C4突头之间的TiW层须完全去掉。此外，TiW层腐蚀程度不能超过焊点以下4μm。已证明过度钻蚀会引起C4焊料突头及其相应器件的过早疲劳失效。
如图2A和2B所示，在传统的腐蚀过程中，不仅有残存金属12而且过度钻蚀缺陷20也经常出现。这可用酸的预先清洗以清除表面氧化物的办法加以部分补救。但是，不论在滞止的还是循环的环境介质中腐蚀晶片都无助于这些缺陷的改善。晶片与晶片间结果的巨大差异经常出现。这妨碍生产的批量进行。此外，单个晶片经常是腐蚀不足区和腐蚀过度区同时存在。
用传统的处理工艺加工芯片的成品率不高于99％。此外，如上所讨论的，“耐蚀的TiW”，一种由位于局部区域不能腐蚀掉的金属组成的缺陷，在传统方法中是经常存在的。如图3A和3B所示，本发明已确定“耐蚀的TiW”的存在可归因于钨的氧化物在金属表面的吸附。这些氧化物对TiW表面的附着使腐蚀机理发生变化，由所希望的均匀腐蚀16(见图3A)变成不希望发生的晶界腐蚀18(见图3B)。
采取额外增加时间对晶片再腐蚀的办法也无助于此类缺陷的改善，并且还会引起严重的TiW的钻蚀。未腐蚀的金属与所述残存金属12有本质不同，如图2A所示，残存金属的出现是因腐蚀时间短或物质交换不足所致。不是既薄又连续的金属，残存金属厚且不连续，呈现不完整的六角几何形状。在不同的pH值范围进行实验时，此类缺陷或出现或消失。表明在不同的pH值范围内，TiW腐蚀机理不同，尽管测定的腐蚀速率大致相同。
一种有电镀的C4(PbSn)焊料突头存在时可用于TiW湿法腐蚀的溶液含有过氧化氢、硫酸钾和乙二胺四乙酸钾。过氧化氢的含量主要影响整体腐蚀速率，而硫酸钾的含量控制着腐蚀过程中PbSn表面的钝化程度。乙二胺四乙酸钾则是一种螯合剂，可粘附于金属包括铜和钛上，以阻止此类金属在焊料突头表面的再沉积，以及防止腐蚀液本身的催化分解。
所述溶液中优选的过氧化氢浓度介于160-180g/l之间，以产生所希望的腐蚀速率，该速率应足够慢以使铅能发生钝化。但又足够快使TiW得以去除，而又不会因硫酸钾中自由硫酸盐离子造成铅过多转化成硫酸铅。此外，在实际生产环境中这一浓度能够得以维持不变。溶液中硫酸钾的含量在150-210g/l之间，以保证PbSn焊料突头的快速钝化。溶液中也含有缓冲能力在0.08-0.12间的EDTA。缓冲能力定义为使1ml的腐蚀液pH值从4.0升至5.0所需的滴定剂的克当量。EDTA的存在可阻止由自由金属引起的腐蚀液中过氧化物的快速、无控制的降解。而且，所加的EDTA的量也能够在生产环境中得以切实维持。
在上述公开的溶液组成范围内，腐蚀液pH值可做调整(添加硫酸或其它pH调整剂)，以改善腐蚀机制和获得所需要的结果。如果溶液的pH值大致在4.0以下，TiW的腐蚀均匀(见图3A)，这样膜的减薄均匀一致，整个金属膜的去除就无麻烦而言。相反，如果所述溶液的pH值大致在4.0以上，腐蚀液会使TiW表面钝化并侵蚀金属膜的晶界(参见图3B)。结果，单个晶粒被蚀刻出并进入腐蚀液中。该腐蚀机制的非均质性会TiW的去除极不均匀，经常残存有不可腐蚀的区域。
已证实所述溶液的pH值处于2.7-4.0间时腐蚀结果令人满意。在这一范围内，TiW不会变得不可腐蚀。此pH值范围腐蚀性能改善是因为Ti与过氧化氢和EDTA反应形成一种可溶性钛的铬合物。钨与过氧化氢反应生成H2WO4和水。pH值很高时，钨的腐蚀加速，并使钨在溶液中以WO4 2-形式存在。pH值很低时，钨以难溶的钨酸H2WO4形式存在。pH值适中时，钨可形成多钨酸盐，已知其存在形式非常多。其它的络合物，如钨酸铅(PbWO4)也是腐蚀过程中的副产物。一定的pH值范围内，这些副产物可成为凝胶体覆盖于TiW表面，从而阻止其腐蚀。
钛络合物的形成也与pH值有关。pH值很低时，EDTA会发生质子化并丧失化其螯合金属的能力。相反，pH值很高时，氢氧化物可置换EDTA或分解过氧键，使络合物受到破坏。
这样，所述的腐蚀液的pH值介于2.7-4.0之间时，既可获得加工C4器件时所要求的效率，又消除了腐蚀TiW时易产生的大部分缺陷。要获得这一结果，尤其应优选pH值范围为3.4-3.9。
本发明决非仅限于有C4焊点时TiW的腐蚀，它也可广泛应用于其它具有金属/基片/镀液这类结构的场合。尤其可用于那些有可腐蚀部件存在时进行腐蚀的场合。
尽管此处的说明和描述均参考特定的实施方案，但本发明决非受此所示细节所限。相反，在本权利要求的范围内，对具体内容可做各种各样的改进而不偏离本发明的精神。

Claims (13)

1.一种在基片上有被保护金属存在情况下湿法腐蚀金属膜的方法，该方法包括将所述金属膜与腐蚀剂溶液相接触，其中，所述的腐蚀剂溶液包括过氧化氢、硫酸钾和乙二胺四乙酸钾，并且所述腐蚀剂溶液的pH值介于2.7～4.0之间。
2.根据权利要求1的方法，特征在于所述基片是半导体，并且还带有焊料突头。
3.根据权利要求1的方法，特征在于所述基片是半导体，并且还带有C4焊料突头。
4.根据权利要求1的方法，特征在于：(a)所述腐蚀剂溶液含有160-180g/l的过氧化氢和150-210g/l的硫酸钾，以及(b)所述腐蚀剂溶液中乙二胺四乙酸钾的缓冲能力为0.08-0.12。
5.根据权利要求1的方法，特征在于所述金属膜是钛/钨合金(TiW)，并且所述被保护的金属至少是CrCu、Cu和PbSn中之一。
6.根据权利要求1的方法，特征在于所述腐蚀剂溶液的pH值在3.4-3.9之间。
7.根据权利要求1的方法，其中所述基片为带有C4焊料突头的半导体基片，所述的腐蚀剂溶液包含160-180g/l的过氧化氢，150-210g/l的硫酸钾和缓冲能力为0.08-0.12的乙二胺四乙酸钾，并且所述的被保护金属至少是CrCu、Cu和PbSn三种材料之一种，所述腐蚀剂溶液的pH值范围在3.4-3.9之间。
8.一种在基片上有被保护金属存在时湿法腐蚀金属膜的溶液，该溶液包含过氧化氢、硫酸钾和乙二胺四乙酸钾，其中，所述溶液的pH值介于2.7-4.0之间。
9.根据权利要求8的溶液，特征在于所述基片是半导体并且带有焊料突头。
10.根据权利要求8的溶液，特征在于所述基片是半导体并且带有C4焊料突头。
11.根据权利要求8的溶液，特征在于：(a)该溶液含有160-180g/l的过氧化氢和150-210g/l的硫酸钾，以及(b)所述溶液中含有的乙二胺四乙酸钾的缓冲能力为0.08-0.12。
12.根据权利要求8的溶液，特征在于所述溶液的pH值为3.4-3.9。
13.根据权利要求8的溶液，其中所述基片为带有C4焊料突头的半导体基片，该溶液包括：
浓度160-180g/l的过氧化氢；
浓度150-210g/l的硫酸钾；以及
缓冲能力为0.08-0.12的乙二胺四乙酸钾，其中，所述溶液的pH值介于3.4-3.9之间。
CNB981236731A 1997-10-30 1998-10-30 在电镀的控制熔塌芯片连接焊料突头存在下改进的钛钨合金腐蚀方法 Expired - Fee Related CN1186801C (zh)

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Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6238589B1 (en) * 1998-08-21 2001-05-29 International Business Machines Corporation Methods for monitoring components in the TiW etching bath used in the fabrication of C4s
US6258627B1 (en) * 1999-01-19 2001-07-10 International Business Machines Corporation Underfill preform interposer for joining chip to substrate
US6358788B1 (en) * 1999-08-30 2002-03-19 Micron Technology, Inc. Method of fabricating a wordline in a memory array of a semiconductor device
EP1100120B1 (en) * 1999-11-10 2009-01-07 The Boeing Company Method for fabricating thin film devices
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6346750B1 (en) * 2000-04-28 2002-02-12 Micron Technology, Inc. Resistance-reducing conductive adhesives for attachment of electronic components
US6876052B1 (en) * 2000-05-12 2005-04-05 National Semiconductor Corporation Package-ready light-sensitive integrated circuit and method for its preparation
US6293457B1 (en) 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
US6468413B1 (en) 2000-10-26 2002-10-22 International Business Machines Corporation Electrochemical etch for high tin solder bumps
KR100379824B1 (ko) * 2000-12-20 2003-04-11 엘지.필립스 엘시디 주식회사 식각용액 및 식각용액으로 패턴된 구리배선을 가지는전자기기용 어레이기판
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
US6740427B2 (en) 2001-09-21 2004-05-25 Intel Corporation Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
JP4811756B2 (ja) * 2001-09-28 2011-11-09 Ｄｏｗａメタルテック株式会社 金属−セラミックス接合回路基板の製造方法
US6749760B2 (en) * 2001-10-26 2004-06-15 Intel Corporation Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead
US7208396B2 (en) * 2002-01-16 2007-04-24 Tegal Corporation Permanent adherence of the back end of a wafer to an electrical component or sub-assembly
TW556293B (en) * 2002-02-21 2003-10-01 Advanced Semiconductor Eng Bump process
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
WO2004001837A2 (en) * 2002-06-25 2003-12-31 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
US20040112868A1 (en) * 2002-12-13 2004-06-17 Phipps Peter Beverley Powell Etchant solution for removing a thin metallic layer
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7244671B2 (en) * 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
US7129182B2 (en) * 2003-11-06 2006-10-31 Intel Corporation Method for etching a thin metal layer
CN100421216C (zh) * 2003-12-18 2008-09-24 悠立半导体股份有限公司 蚀刻液及应用该蚀刻液选择性去除阻障层的导电凸块制造方法
EP1571704A1 (en) * 2004-03-04 2005-09-07 Interuniversitair Microelektronica Centrum Vzw Method for depositing a solder material on a substrate in the form of a predetermined pattern
JP2006202969A (ja) * 2005-01-20 2006-08-03 Taiyo Yuden Co Ltd 半導体装置およびその実装体
US8553364B1 (en) 2005-09-09 2013-10-08 Magnecomp Corporation Low impedance, high bandwidth disk drive suspension circuit
US7829793B2 (en) * 2005-09-09 2010-11-09 Magnecomp Corporation Additive disk drive suspension manufacturing using tie layers for vias and product thereof
US20080083611A1 (en) * 2006-10-06 2008-04-10 Tegal Corporation High-adhesive backside metallization
US20080119056A1 (en) * 2006-11-16 2008-05-22 International Business Machines Corporation Method for improved copper layer etching of wafers with c4 connection structures
KR101512490B1 (ko) 2007-11-22 2015-04-17 삼성전자주식회사 범프 하부 도전층 식각용 조성물 및 이를 이용한 도전성 범프 구조물의 형성 방법
US20090246385A1 (en) * 2008-03-25 2009-10-01 Tegal Corporation Control of crystal orientation and stress in sputter deposited thin films
US8808513B2 (en) * 2008-03-25 2014-08-19 Oem Group, Inc Stress adjustment in reactive sputtering
US8482375B2 (en) * 2009-05-24 2013-07-09 Oem Group, Inc. Sputter deposition of cermet resistor films with low temperature coefficient of resistance
US9425146B2 (en) * 2010-09-28 2016-08-23 Infineon Technologies Ag Semiconductor structure and method for making same
US8415243B1 (en) * 2012-01-18 2013-04-09 Chipbond Technology Corporation Bumping process and structure thereof
JP5917346B2 (ja) * 2012-09-07 2016-05-11 株式会社東芝 エッチング方法、およびエッチング装置
CN103236415B (zh) * 2012-12-31 2015-12-23 中国电子科技集团公司第四十一研究所 一种薄膜混合集成电路电镀方法
CN104791734B (zh) * 2015-04-21 2018-02-23 乐健科技（珠海）有限公司 带嵌入式线路的散热体的制造方法、led模组的制造方法
US10734348B2 (en) * 2018-09-21 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded semiconductor devices and methods of forming the same
CN115995444A (zh) * 2021-10-19 2023-04-21 群创光电股份有限公司 电子组件及其制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491860A (en) * 1982-04-23 1985-01-01 Signetics Corporation TiW2 N Fusible links in semiconductor integrated circuits
US4554050A (en) * 1984-07-16 1985-11-19 At&T Bell Laboratories Etching of titanium
US4671852A (en) * 1986-05-07 1987-06-09 The Standard Oil Company Method of forming suspended gate, chemically sensitive field-effect transistor
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
NL8701184A (nl) * 1987-05-18 1988-12-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US4787958A (en) * 1987-08-28 1988-11-29 Motorola Inc. Method of chemically etching TiW and/or TiWN
US5041191A (en) * 1989-11-13 1991-08-20 Rockwell International Corporation Diffusion barrier for thin film hybrid circuits
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
US5211807A (en) * 1991-07-02 1993-05-18 Microelectronics Computer & Technology Titanium-tungsten etching solutions
US5462638A (en) * 1994-06-15 1995-10-31 International Business Machines Corporation Selective etching of TiW for C4 fabrication
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5486282A (en) * 1994-11-30 1996-01-23 Ibm Corporation Electroetching process for seed layer removal in electrochemical fabrication of wafers
US5800726A (en) * 1995-07-26 1998-09-01 International Business Machines Corporation Selective chemical etching in microelectronics fabrication

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