CN1191392A - 多层镀层引线架 - Google Patents

多层镀层引线架 Download PDF

Info

Publication number
CN1191392A
CN1191392A CN98104431A CN98104431A CN1191392A CN 1191392 A CN1191392 A CN 1191392A CN 98104431 A CN98104431 A CN 98104431A CN 98104431 A CN98104431 A CN 98104431A CN 1191392 A CN1191392 A CN 1191392A
Authority
CN
China
Prior art keywords
plating layer
lead frame
layer
plating
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN98104431A
Other languages
English (en)
Other versions
CN1125491C (zh
Inventor
金重道
白铃昊
福京纯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Haesung DS Co Ltd
Original Assignee
Samsung Aerospace Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Aerospace Industries Ltd filed Critical Samsung Aerospace Industries Ltd
Publication of CN1191392A publication Critical patent/CN1191392A/zh
Application granted granted Critical
Publication of CN1125491C publication Critical patent/CN1125491C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/023—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提出了一种多层镀层引线架。该引线架的结构具有顺序地形成在一铁合金衬底上的一第一贵金属镀层,一中间镀层和一第二贵金属镀层。该引线架在所有特性如连线键合性,抗腐蚀和可焊接性上均有改善。

Description

多层镀层引线架
本发明涉及引线架，更具体地说，涉及一种多层镀层引线架，其中镀层的结构得到了改善，以使一个预镀层架(PPF)过程施加到铁合金的衬底上。
半导体引线架是半导体封装中的和半导体晶片一起的一个重要元件。引线架把半导体封装的内部和外部相连，并支持半导体晶片。通常，这样的半导体引线架由模压或蚀刻方法制造。
按照模压方法，用压模设备把一个薄金属板材料制成一个预定形状。这样的模压方法主要用于批量生产引线架。
而蚀刻方法是一种化学腐蚀，在这种方法中，用化学物质将材料的预定部分腐蚀掉，这种方法用于少量生产引线架。
根据引线架在衬底上的安装类型，由上述方法制造的半导体引线架有各种各样的结构。图1表示一种半导体引线架的一般结构。
在图1中，该引线架包括模盘11用于安装并固定存储晶片，内引线12通过连线键合连接到晶片上，外引线13用于连接外部电路。
具有上述结构的半导体引线架通过与半导体的其它部件组合例如存储晶片就形成一个半导体封装。
为了改善半导体晶片与引线架内引线12之间的连线键合，模盘11和内引线12被镀上金属。另外，为了改善焊接性，焊料层涂敷在外引线13的预定部分上。
然而，在焊料层涂敷过程中，涂敷液经常侵占内引线12的区域，所以，需要一个清除该不需要的涂敷液的额外步骤。
为解决该问题，曾提出一种预镀层架(PPF)方法。根据该预镀层架方法，一种具有优良焊接湿润性的材料在半导体封装处理前涂在衬底上，以形成一个镀层。由上述方法获得的镀层结构示于图2，3和4中。
参照图2，一镍(Ni)镀层22，和一钯(Pd)或Pd/Ni合金镀层23，顺序地形成在铜(Cu)衬底21上，形成了一个多层镀层。
图3的引线架包括一Ni镀层32，一Pd/Ni合金镀层33，一Ni镀层34，和一Pd镀层35，其中的镀层32，33，34和35顺序地形成在Cu衬底31上。
根据图4中的引线架，一Ni镀层42和一Pd或金(Au)镀层43，顺序地形成在Cu衬底41上。另外，一Pd/Ni合金镀层44，一Pd或Au镀层43′和一Pd镀层45形成在Pd或Au镀层43上。
然而，从图2到图4的引线架，通过用铜或铜合金作为衬底材料，根据一预镀层架过程制造，并且，把用于形成图2到图4中引线架的预度层架过程实施到合金42制成的衬底上是困难的。这里，合金42由Ni、Fe和少量其它元素组成，并被广泛地用作引线架衬底材料。然而，合金42被盐性环境的组装过程严重腐蚀。这是由于在合金42的Fe和镀层的Pd之间的电化学电势上的巨大差别导致的电化腐蚀引起的。
为解决上述问题，本发明的目的在于提供一种引线架，通过改善其中的镀层结构，该引线架具有优良的抗蚀性，以及良好的焊接和连线键合性。
为完成上述目的，此提供一多层镀层引线架包括：一铁合金的衬底，和顺序地形成在衬底上的一第一贵金属镀层，一中间镀层，以及一第二贵金属镀层。
较好地，中间镀层包括一铜(Cu)镀层和一镍(Ni)镀层。
通过参照附图对本发明最佳实施例的详细描述，本发明的上述目的和优点将会更加明了，附图中：
图1是一般引线架结构的平面图；
图2、3和4是表示传统引线架的镀层结构的剖视图；
图5是埃万斯(Evans)图；以及
图6是表示根据本发明的一个引线架镀层结构的剖视图。
本发明的特点在于铁合金的衬底在初始时镀以贵金属或其合金。在形成这样的贵金属镀层后，形成一中间镀层和一最外镀层，来完成镀层。这里，一钯(Pd)镀层可形成在中间镀层和最外镀层之间。此处，含有Pd的镀层改善中间镀层和最外镀层之间的粘合性，以及减小镀层的表面粗糙度，由此改善可焊接性和连线键合。
本发明的原理将参照瓦格纳(Wagner)的混合分子电极理论进行描述。
在电化学领域里，通常金属的腐蚀率可用下述等式(1)表述。
i＝ioexp(ΔE/β)    ……(1)这里的io为交换电流密度，β为达菲尔(Tfel)常数，ΔE为氧化反应电势和还原反应电势之差。
根据混合分子电极理论，腐蚀反应由氧化反应和还原反应构成，并且，当氧化反应率和还原反应率相等时，腐蚀反应率就可以确定了。
金属的腐蚀反应特性可以用图5中的Evans图容易地表示，其中，等式(1)的ΔE和电流密度i之间的关系表示为半对数型。
一般地，具有原子价v的金属M的腐蚀通过下面的氧化还原反应发生。
氧化反应(在引线架和镀层的介面处)：
M＝Mv++ve-
还原反应(在镀层和外围大气的介面处)：
该金属的腐蚀率可以在“ΔE对logi”氧化反应曲线和“ΔE对logi”还原反应曲线的交点上确定。
为了降低金属的腐蚀率，氧化反应率和还原反应率都必须减小。然而，当氧化还原反应在中性和盐性环境中时，还原反应是固定的。因此，为了降低金属的腐蚀率，改变金属的还原反应是必需的。
如前面所述，金属氧化反应主要发生在引线架和第一金属镀层之间的介面处。因此，确定第一镀层的电化学电势的数值变得非常重要。腐蚀率随着引线架和第一镀层之间的电化学电势差的降低而降低。
例如，如图5中所示，金属的电化学电势以Mn，Fe，Cu，和Pd的顺序增加。并且，金属的整体腐蚀率以Mn，Fe，Cu和Pd的顺序大大地降低。
在本发明中，根据上述原理，通过在铁引线架上镀一贵金属如钯(Pd)的层预镀(strike layer)来降低氧化反应率。由此来减缓腐蚀率。
下面，参照图6，对根据本发明最佳实施例的引线架结构进行描述。
第一贵金属镀层62由从下面一组中选出的金属形成即钯(Pd)，金(Au)，铂(Pt)，铑(Rh)，银(Ag)，钌(Ru)和其合金，并形成在铁合金衬底61上。这里，衬底的厚度最好为0.01～5mm。
用于形成第一贵金属镀层的合金包括：一种Pd-Au合金，含有50％或少于此重量的Au；一种Pd-Co合金，含有50％或少于此重量的Co；一种Pd-W合金，含有50％或少于此重量的钨(W)；一种Pd-Ti合金，含有50％或少于此重量的钛(Ti)；一种Pd-Sn合金，含有50％或少于此重量的锡(Sn)；一种Pd-Ni合金，含有50％或少于此重量的镍(Ni)；以及一种Pd-Mo合金，含有50％或少于此重量的钼(Mo)。上述的百分比基于合金的重量。第一贵金属镀层减小了氧化还原间的电化学电势差，如上所述，借此就可以改善抗腐蚀性。另外，较好地是，第一贵金属层的厚度为0.01～10μm。
铜镀层63形成在第一贵金属镀层62上，铜镀层63由铜或合铜金形成，该合金包括作为主要元素的铜和基于整个合金重量的50％或多于此重量的其它金属。另一种金属从下列组中选出，即Sn，Ni，Mo，Mn和Co。较好地是，铜镀层63的厚度为0.01～10μm。
铜镀层63改善了第一贵金属镀层62和Ni镀层64之间的粘合性，并阻止了金属原子从衬底的扩散。
Ni镀层64形成为中间层以阻止活化铜生成物的出现，例如氧化铜或铜硫化物，活化铜生成物通过和扩散到最外层表面的铜原子的反应获得。Ni镀层64由Ni或Ni合金形成，Ni合金包括作为主要元素的Ni和基于整个合金重量的50％或多于此重量的其它金属。另一种金属从下列组中选出，即Cu、Sn、Mn、Co和W。较好地是，Ni镀层64的厚度为0.01～10μm。
一Pd镀层65形成在Ni镀层64上，Pd镀层由Pd或Pd合金形成，Pd合金包括作为主要元素的Pd和基于整个合金重量的50％或多于此重量的金属。另一种金属从下列组中选出，即Mo、W、Ti、Sn、Ni、Ag和Co。Pd镀层65的厚度为0.01～10μm。Pd镀层65复盖住Ni镀层64上的细孔，以平滑Ni镀层64的表面粗糙度。相应地，能够在后续步骤中形成均匀的最外层的厚度。
上述的Pd镀层65显著地减小了在盐性环境中的局部腐蚀，增加了Ni镀层64和作为最外镀层的第二贵金属镀层62′之间的键合力。相应地，在安装半导体晶片到引线架的基座上之后的调整和成形步骤中，裂缝的产生和扩宽可以减到最小。结果是，通过阻止Ni从含有Ni的镀层64上的扩散而改善了可焊接性和连线键合性，以及抗腐蚀性。
第二贵金属镀层62′形成在Pd镀层65上，贵金属镀层62′由从下列组中选出的金属形成即Pd、Au、Pt、Ag、Ru、Rh及其合金。作为最外镀层，Pd镀层65保护下面的镀层并阻止其它所有镀层的氧化，以及改善可焊接性和连线键合性。
此处，较好地是，第二贵金属镀层62′的厚度为0.01～10μm。
在具有上述结构的引线架中，一连线键合区，或包括该连线键合区的整个引线架被镀以金属层。
下面，将参照例子对本发明详细描述。
但是，本发明并不局限于下述例子。
<例子>
在Fe-Ni衬底上完成预处理后，一个Pd预镀层形成到约为3μ英寸。在用Cu镀完Pd镀层到约厚2μm，具有Cu镀层的组合结构被接着镀以Ni和Ni-Pd合金，厚度分别为约1μm厚和约3μ英寸厚。然后，厚度约为3μ英寸的Pd镀层形成在已镀的Ni-Pd合金镀层上。Mo.GL-2(S)(德格萨公司Degussa Co.)用于镀Pd和镀Ni-Pd，焦磷酸铜溶液(勃昂温化学制品公司Poong Won Chemical CO.)用于镀铜，以及Mo.6450(Deguss Co.)用于镀Ni。
<对比例子1>
在完成合金42制造的衬底上的预处理后，衬底被顺序地镀以Cu、Ni和Pd，由此完成一个具有三层镀层结构的引线架。
<对比例子2>
在完成合金42制造的衬底上的预处理后，衬底被顺序地镀以Ni，Cu，Ni和Pd，由此来完成一个具有4层镀层结构的引线架。
然后，可焊接性测试(美国军用标准883D，方法2003.7MIL-STD-883D，Method 2003.7)，用于评价在盐性环境中抗腐蚀性的盐水喷洒测试(MIL-STD-883D，Method 1009.8)以及连线键合测试，实施在通过例子和对比例子1及2制造的多层镀层引线架上。结果示在表1中。
                  表1
    举例   可焊接性   连线键合性   抗腐蚀
例子     好   12.01gf(优)     好
对比例子1     差   4.61gf(差)     差
对比例子2     差  8.40gf(一般)     差
从表1中看到，由例子制造的引线架与对比例子1及2相比具有较好的可焊接性、连线键合性及抗腐蚀性。
如上所述，根据本发明的引线架在所有特性上如连线键合，抗腐蚀和可焊接性，都有改善。因此，可以期望在半导体封装过程中有高的成品率，故提高了生产率。

Claims (8)

1.一种多层镀层引线架，包括一个铁合金衬底，和顺序地形成在衬底上的一个第一贵金属镀层，一个中间镀层和一个第二贵金属镀层。
2.根据权利要求1所述的多层镀层引线架，其中，中间镀层包括一铜(Cu)镀层和一镍(Ni)镀层。
3.根据权利要求2所述的多层镀层引线架，其中，Cu镀层由Cu或Cu合金形成，该Cu合金至少包括一种从下列组中选出的金属，即锡(Sn)，镍(Ni)，钼(Mo)，锰(Mn)及钴(Co)。
4.根据权利要求2所述的多层镀层引线架，其中，镍镀层由镍或镍合金形成，该镍合金至少包括一种从下列组中选出的金属，即铜(Cu)，锡(Sn)，钼(Mo)，锰(Mn)及钨(W)。
5.根据权利要求2所述的多层镀层引线架，进一步地包括一在Ni镀层和第二贵金属镀层之间的钯(Pd)镀层。
6.根据权利要求2所述的多层镀层引线架，其中，Pd镀层由Pd或Pd合金形成，该Pd合金至少包括一种从下列组中选出的金属，即钼(Mo)，钨(W)，钛(Ti)，锡(Sn)，镍(Ni)，银(Ag)，金(Au)及钴(Co)。
7.根据权利要求1所述的多层镀层引线架，其中，第一贵金镀层由从下列组中选出的至少一种金属形成，即钯(Pd)，金(Au)，铂(Pt)，铑(Rh)，钌(Ru)，银(Ag)，及其合金。
8.根据权利要求1所述的多层镀层引线架，其中，第二贵金属镀层由从下列组中选出的至少一种金属形成，即钯(Pd)，金(Au)，铂(Pt)，铑(Rh)，钌(Ru)，银(Ag)，及其合金。
CN98104431A 1997-02-20 1998-02-13 多层镀层引线架 Expired - Fee Related CN1125491C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR5102/1997 1997-02-20
KR5102/97 1997-02-20
KR1019970005102A KR100231828B1 (ko) 1997-02-20 1997-02-20 다층 도금 리드프레임

Publications (2)

Publication Number Publication Date
CN1191392A true CN1191392A (zh) 1998-08-26
CN1125491C CN1125491C (zh) 2003-10-22

Family

ID=19497498

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98104431A Expired - Fee Related CN1125491C (zh) 1997-02-20 1998-02-13 多层镀层引线架

Country Status (7)

Country Link
US (1) US6150711A (zh)
JP (1) JP4489193B2 (zh)
KR (1) KR100231828B1 (zh)
CN (1) CN1125491C (zh)
GB (1) GB2322475B (zh)
SG (1) SG60204A1 (zh)
TW (1) TW369689B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392850C (zh) * 2006-05-29 2008-06-04 朱冬生 一种引线框架以及具有所述引线框架的半导体器件
CN102575369A (zh) * 2009-06-29 2012-07-11 Om产业股份有限公司 电气元件的制造方法和电气元件
CN105283582A (zh) * 2013-06-13 2016-01-27 东洋钢钣株式会社 镀钯覆盖材料及镀钯覆盖材料的制造方法
CN106676593A (zh) * 2016-12-13 2017-05-17 上海航天设备制造总厂 不锈钢表面钯铜镍钼合金膜层及其制备方法
CN111525314A (zh) * 2020-05-05 2020-08-11 富士康(昆山)电脑接插件有限公司 导电端子
CN113471163A (zh) * 2021-07-23 2021-10-01 重庆平创半导体研究院有限责任公司 一种晶圆互连结构及工艺
CN114094373A (zh) * 2020-06-22 2022-02-25 华为技术有限公司 导电端子、电连接器和电子设备

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011048A1 (en) * 1999-03-19 2003-01-16 Abbott Donald C. Semiconductor circuit assembly having a plated leadframe including gold selectively covering areas to be soldered
US6469386B1 (en) * 1999-10-01 2002-10-22 Samsung Aerospace Industries, Ltd. Lead frame and method for plating the same
JP2001185670A (ja) * 1999-12-10 2001-07-06 Texas Instr Inc <Ti> リードフレームとその製法
JP4232301B2 (ja) * 1999-12-14 2009-03-04 ソニー株式会社 リードフレームの製造方法、及び、半導体装置の製造方法
US6545344B2 (en) * 2000-06-27 2003-04-08 Texas Instruments Incorporated Semiconductor leadframes plated with lead-free solder and minimum palladium
KR100371567B1 (ko) * 2000-12-08 2003-02-07 삼성테크윈 주식회사 Ａｇ 선도금을 이용한 반도체 패키지용 리드프레임
US6538325B2 (en) * 2001-03-06 2003-03-25 Delphi Technologies, Inc. Multi-layer conductor system with intermediate buffer layer for improved adhesion to dielectrics
US7692277B2 (en) 2003-01-16 2010-04-06 Panasonic Corporation Multilayered lead frame for a semiconductor light-emitting device
KR100998042B1 (ko) * 2004-02-23 2010-12-03 삼성테크윈 주식회사 리드 프레임 및 이를 구비한 반도체 패키지의 제조방법
JP2005129970A (ja) * 2005-02-08 2005-05-19 Matsushita Electric Ind Co Ltd 半導体装置用リードフレーム
DE102005006281B4 (de) * 2005-02-10 2014-07-17 Infineon Technologies Ag Hochfrequenzleistungsbauteil mit Goldbeschichtungen und Verfahren zur Herstellung desselben
JP2006269903A (ja) * 2005-03-25 2006-10-05 Shinko Electric Ind Co Ltd 半導体装置用リードフレーム
KR100819800B1 (ko) * 2005-04-15 2008-04-07 삼성테크윈 주식회사 반도체 패키지용 리드 프레임
KR100702956B1 (ko) * 2005-04-26 2007-04-03 삼성테크윈 주식회사 반도체 팩키지용 리드프레임 및 그 제조 방법
JP4820616B2 (ja) * 2005-10-20 2011-11-24 パナソニック株式会社 リードフレーム
TWM302192U (en) * 2006-06-06 2006-12-01 I Chiun Precision Ind Co Ltd Terminal device for miniature motor
JP2008091818A (ja) * 2006-10-05 2008-04-17 Matsushita Electric Ind Co Ltd 光半導体装置用リードフレームおよびこれを用いた光半導体装置、並びにこれらの製造方法
KR101128974B1 (ko) * 2006-11-07 2012-03-27 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
TWM339117U (en) * 2007-12-24 2008-08-21 Hon Hai Prec Ind Co Ltd Electrical connector and contacts thereof
US7704884B2 (en) 2008-04-11 2010-04-27 Micron Technology, Inc. Semiconductor processing methods
JP2010090402A (ja) * 2008-10-03 2010-04-22 Hitachi Chem Co Ltd めっき析出物
KR101064755B1 (ko) 2008-12-24 2011-09-15 엘지이노텍 주식회사 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법
CN102782189A (zh) * 2010-12-01 2012-11-14 吉坤日矿日石金属株式会社 Pd或以Pd为主成分的合金的表面处理剂、和铜表面的表面皮膜层构造
JP5762081B2 (ja) * 2011-03-29 2015-08-12 新光電気工業株式会社 リードフレーム及び半導体装置
CN108866585B (zh) * 2017-05-08 2021-01-05 永保科技(深圳)有限公司 一种表面具有电镀层的难熔金属或不锈钢，以及一种难熔金属或不锈钢表面的电镀工艺
CN110265376A (zh) 2018-03-12 2019-09-20 意法半导体股份有限公司 引线框架表面精整
US11735512B2 (en) 2018-12-31 2023-08-22 Stmicroelectronics International N.V. Leadframe with a metal oxide coating and method of forming the same
CN111304654B (zh) * 2020-04-10 2022-03-18 扬州工业职业技术学院 一种钢带表面镀铂方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5030587B1 (zh) * 1969-07-02 1975-10-02
US4141029A (en) * 1977-12-30 1979-02-20 Texas Instruments Incorporated Integrated circuit device
US5001546A (en) * 1983-07-27 1991-03-19 Olin Corporation Clad metal lead frame substrates
EP0335608B1 (en) * 1988-03-28 1995-06-14 Texas Instruments Incorporated Lead frame with reduced corrosion
US4911798A (en) * 1988-12-20 1990-03-27 At&T Bell Laboratories Palladium alloy plating process
US4917967A (en) * 1989-01-13 1990-04-17 Avon Products, Inc. Multiple-layered article and method of making same
US5138431A (en) * 1990-01-31 1992-08-11 Vlsi Technology, Inc. Lead and socket structures with reduced self-inductance
KR920000127A (ko) * 1990-02-26 1992-01-10 미다 가쓰시게 반도체 패키지와 그것을 위한 리드프레임
JPH0590465A (ja) * 1991-09-27 1993-04-09 Mitsui High Tec Inc 半導体装置
DE4311872C2 (de) * 1993-04-10 1998-07-02 Heraeus Gmbh W C Leiterrahmen für integrierte Schaltungen
US5360991A (en) * 1993-07-29 1994-11-01 At&T Bell Laboratories Integrated circuit devices with solderable lead frame
US5436082A (en) * 1993-12-27 1995-07-25 National Semiconductor Corporation Protective coating combination for lead frames
US5650661A (en) * 1993-12-27 1997-07-22 National Semiconductor Corporation Protective coating combination for lead frames
US5454929A (en) * 1994-06-16 1995-10-03 National Semiconductor Corporation Process for preparing solderable integrated circuit lead frames by plating with tin and palladium
US5675177A (en) * 1995-06-26 1997-10-07 Lucent Technologies Inc. Ultra-thin noble metal coatings for electronic packaging
JPH09232493A (ja) * 1995-12-20 1997-09-05 Seiichi Serizawa リードフレーム
US5994767A (en) * 1997-04-09 1999-11-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package and method of manufacturing the same
TW448204B (en) * 1997-04-09 2001-08-01 Jeng Wu Shuen A method for catalytic depolymerization of polyethylene terephthalate

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392850C (zh) * 2006-05-29 2008-06-04 朱冬生 一种引线框架以及具有所述引线框架的半导体器件
CN102575369A (zh) * 2009-06-29 2012-07-11 Om产业股份有限公司 电气元件的制造方法和电气元件
CN102575369B (zh) * 2009-06-29 2015-08-05 Om产业股份有限公司 电气元件的制造方法和电气元件
CN105283582A (zh) * 2013-06-13 2016-01-27 东洋钢钣株式会社 镀钯覆盖材料及镀钯覆盖材料的制造方法
US10087528B2 (en) 2013-06-13 2018-10-02 Toyo Kohan Co., Ltd. Palladium plate coated material and method of producing palladium plate coated material
CN106676593A (zh) * 2016-12-13 2017-05-17 上海航天设备制造总厂 不锈钢表面钯铜镍钼合金膜层及其制备方法
CN111525314A (zh) * 2020-05-05 2020-08-11 富士康(昆山)电脑接插件有限公司 导电端子
CN114094373A (zh) * 2020-06-22 2022-02-25 华为技术有限公司 导电端子、电连接器和电子设备
CN113471163A (zh) * 2021-07-23 2021-10-01 重庆平创半导体研究院有限责任公司 一种晶圆互连结构及工艺
CN113471163B (zh) * 2021-07-23 2023-06-20 重庆平创半导体研究院有限责任公司 一种晶圆互连结构及工艺

Also Published As

Publication number Publication date
KR100231828B1 (ko) 1999-12-01
SG60204A1 (en) 1999-02-22
GB2322475A (en) 1998-08-26
JP4489193B2 (ja) 2010-06-23
KR19980068487A (ko) 1998-10-26
GB9803365D0 (en) 1998-04-15
US6150711A (en) 2000-11-21
CN1125491C (zh) 2003-10-22
GB2322475B (en) 2001-09-05
JPH10237691A (ja) 1998-09-08
TW369689B (en) 1999-09-11

Similar Documents

Publication Publication Date Title
CN1125491C (zh) 多层镀层引线架
KR0183645B1 (ko) 다층 구조의 도금층을 구비한 반도체 리드 프레임
US5436082A (en) Protective coating combination for lead frames
JP2543619B2 (ja) 半導体装置用リ―ドフレ―ム
JP3760075B2 (ja) 半導体パッケージ用リードフレーム
US6037653A (en) Semiconductor lead frame having multi-layered plating layer including copper-nickel plating layer
CN102349153A (zh) 引线框架及其制造方法
WO2017179447A1 (ja) リードフレーム材およびその製造方法
US6706561B2 (en) Method for fabricating preplated nickel/palladium and tin leadframes
EP1037277B1 (en) Lead frame and method of fabricating a lead frame
KR20190096964A (ko) 리드 프레임재 및 이의 제조 방법 및 반도체 패키지
JPH1022434A (ja) 集積回路用リードフレーム及びその製造方法
JPH07326701A (ja) 電気電子部品用導電材、リードフレ−ム及びそれを使用した半導体集積回路
US7432584B2 (en) Leadframe for use in a semiconductor package
US20030137032A1 (en) Pre-finished leadframe for semiconductor devices and method fo fabrication
KR100378489B1 (ko) 은 또는 은 합금도금을 이용한 반도체 패키지용 리드프레임 및 그 제조방법
JPH10251860A (ja) 金／ニッケル／ニッケル３層めっき銅合金電子部品およびその製造方法
KR0183652B1 (ko) 반도체 리드프레임
KR100189819B1 (ko) 팔라듐이 도금된 반도체 리드프레임
KR100209264B1 (ko) 반도체 리드 프레임
KR100203334B1 (ko) 다층도금 리드프레임
KR20030063835A (ko) 다층도금 리드프레임 및 이 리드프레임의 제조방법
KR100225778B1 (ko) 리드 프레임을 이용한 반도체 팩키지
KR100294911B1 (ko) 반도체리드프레임
KR100254268B1 (ko) 다층 구조의 도금층을 갖는 반도체용 리드프레임

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: MDS CO., LTD.

Free format text: FORMER OWNER: SAMSUNG AEROSPACE INDUSTRIES, LTD.

Effective date: 20140704

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20140704

Address after: Gyeongnam Changwon City, South Korea

Patentee after: MDS Co., Ltd.

Address before: Gyeongnam, South Korea

Patentee before: Samsung Aerospace Industries, Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20031022

Termination date: 20150213

EXPY Termination of patent right or utility model