CN1189930C - 机械性增强的焊接区界面及其方法 - Google Patents

机械性增强的焊接区界面及其方法 Download PDF

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Publication number
CN1189930C
CN1189930C CNB001309676A CN00130967A CN1189930C CN 1189930 C CN1189930 C CN 1189930C CN B001309676 A CNB001309676 A CN B001309676A CN 00130967 A CN00130967 A CN 00130967A CN 1189930 C CN1189930 C CN 1189930C
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welding region
conductive welding
layer
insulating barrier
stacked
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CN1305224A (zh
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斯科特·K·鲍兹德尔
托马斯·S·科巴亚西
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

提供耐在用探针探测或封装操作期间会施加的外力的复合焊盘。复合焊盘包括在半导体衬底(100)上形成的非自钝化导电焊盘(134)。然后在导电焊盘上形成绝缘层(136)。去除部分绝缘层使该层有穿孔而露出一部分导电焊盘。留下的部分形成叠置在焊盘上的支撑结构(138)。然后在焊盘结构上面形成自钝化导电封顶层(204),在这场合下绝缘层中的穿孔可以供封顶层和在下面的焊盘露出部分之间电接触用。支撑结构(138)构成保护封顶层和焊盘之间界面的机械阻挡层。

Description

机械性增强的焊接区界面及其方法
技术领域
本发明一般地涉及集成电路而更详细地涉及在集成电路内应用的在机械上加固的焊接区界面。
背景技术
本申请涉及1999年10月4日归档并授于名称“半导体器件和制作方法”(“Semiconductor Device and Method of Formation”)的美国专利申请No.09/411,266,美国专利申请No.09/411,266被委托给申请代理人而在本申请说明书中由参考文献引用。
在半导体衬底上采用形成电路元件的许多不同的工艺操作制成集成电路。为了使进出线路与半导体衬底相联系,在集成电路上形成焊接区。焊接区提供经由探针、焊线、导电凸出部等从芯片和到芯片输送电信号和电源的手段。
一般由例如铝、铜或其一些合金制成焊接区。因为与铝比较起来铜改善电磁性和提高承受较高电流密度的能力,所以铜常常用于集成电路里的金属层。然而,铜是非自钝化的金属,当芯片暴露于大气或者没有密闭封装而使潮气与铜焊接区相互作用时能够发生铜焊接区的氧化或腐蚀。对于焊接区来说,这种腐蚀会降低焊接导线或凸出部的能力而且也会使焊接损坏而引起工作时间范围内的故障。相反,铝是自钝化的,而所以是更耐由暴露大气引起的剥蚀的。因此,一般用铝制作焊接区。
为了获得铝的自钝化性质的优点和铜的优良电特性,在集成电路设计中可以采用复合的焊接区结构。在复合焊接区(焊盘)结构中,铜用于与集成电路中其他薄层面接的在上面的焊接区薄层。在铜部分的顶部制作耐腐蚀的铝封顶层,以形成保护铜部分免于暴露大气的气密封。在考虑到电连通性时为了在物理上使复合焊接区中的铜部分和铝部分隔离,可以在界面上形成比较薄的阻挡金属层。
发明内容
本发明的目的是提供一种制造半导体器件的方法及半导体器件,可防焊接区损坏。
根据本发明一方面,一种制作半导体器件的方法,其特征在于包括步骤:在半导体衬底上形成导电焊接区;在导电焊接区上形成绝缘层;去除部分绝缘层,其中绝缘层的去除部分形成叠置在导电焊接区上的多个支撑结构,并且其中绝缘层的去除部分使一部分导电焊接区露出;形成叠置在多个支撑结构上的导电封顶层,其中导电封顶层电接触一部分导电焊接区;和在导电焊接区内形成绝缘柱,其中至少一部分支撑结构叠置在一部分绝缘柱上。
一种制作半导体器件的方法,其特征在于包括步骤:在半导体衬底上形成导电焊接区;在导电焊接区上形成绝缘层;去除部分绝缘层,其中绝缘层的去除部分形成叠置在导电焊接区上的多个支撑结构,并且其中绝缘层的去除部分使一部分导电焊接区露出;形成叠置在多个支撑结构上的导电封顶层,其中导电封顶层电接触一部分导电焊接区;和其中许多支撑结构与绝缘层的未去除部分互连。
一种制作半导体器件的方法,其特征在于包括步骤:在半导体衬底上形成导电焊接区;在导电焊接区上形成绝缘层;去除部分绝缘层,其中绝缘层被去除的部分形成叠在导电焊接区上的多个支撑结构,而且绝缘层被去除的部分暴露一部分导电焊接区;在多个支撑结构上形成导电封顶层,其中导电封顶层电接触一部分导电焊接区;和在导电封顶层和导电焊接区之间,形成阻挡层,其中所述阻挡层叠在所述多个支撑结构之上。
根据本发明另一方面,一种半导体器件,其特征在于包括:在半导体衬底上的导电焊接区;在导电焊接区上的绝缘层;叠置在导电焊接区上的多个支撑结构;叠置在多个支撑结构上的导电封顶层,其中导电封顶层电接触一部分导电焊接区;和在导电焊接区中的绝缘柱,其中多个支撑结构中至少之一的至少一部分叠置在一部分绝缘柱上。
一种半导体器件,其特征在于包括:在半导体衬底上的导电焊接区;在导电焊接区上的绝缘层;叠置在导电焊接区上的多个支撑结构;叠置在多个支撑结构上的导电封顶层,其中导电封顶层电接触一部分导电焊接区;和其中多个支撑结构中的至少一部分与绝缘层的未去除部分互连。
一种半导体器件,其特征在于包括:在半导体衬底上的导电焊接区;在导电焊接区上的绝缘层;叠置在导电焊接区上的多个支撑结构;叠置在多个支撑结构上的导电封顶层,其中导电封顶层电接触一部分导电焊接区;和在导电焊接区下面至少一层绝缘层具有小于50吉帕斯卡的杨氏模量。
一种半导体器件,其特征在于包括:在半导体衬底上的导电焊接区;在导电焊接区上的绝缘层;叠置在导电焊接区上的多个支撑结构;叠置在多个支撑结构上的导电封顶层,其中导电封顶层电接触一部分导电焊接区;和在导电封顶层和导电焊接区之间的阻挡层,其中所述阻挡层叠在所述多个支撑结构之上。
当进行测试操作和用探针探测操作时在复合焊接区结构中会出现一些问题。为了获得与焊接区的良好的连续性,像探针之类的元件必须施加会损坏或移动焊接区表面部分的力。因此,用像这样一些元件的物理接触会损坏组成复合焊接区结构的各种金属之间的界面。如果在下面的铜层和铝封顶层之间阻挡层被破坏,那么产生的损伤会引起金属间化合物的生成。铝铜金属间化合物含有包括降低机械强度和增加电阻不希望有的特性。此外如果探针使下面的铜暴露于外部环境条件,则就可能损坏铜。
在焊接区结构涉及通过探针元件对焊接区施加传送到集成电路内基于物理连接的下面薄层的机械力的情况下会出现另一问题。在下面的低杨氏模量绝缘材料不能承受像这样由力传送引起的应力。由于拉得很长的互连的杠杆作用引起的施加力增大可以导致在例如通路到金属界面等等的集成电路内半导体器件的机械故障和可能发生的电故障。像这样由增大的施加力引起的破坏一般发生在界面上。当更柔软的绝缘材料(具有较低的杨氏模量或倔服强度)包围被加压力的元件时也可能增大由施加的力引起的破坏。
所以,对复合焊接区结构有机械上加固的需要,以致用探针探测操作或封装操作期间施加的力没有引起焊接区的损坏或没有传送到可能发生其他不希望有的影响的集成电路内部部分。
附图说明
用例子而不局限附图的方法说明本发明,在附图中,相同的标记表示同样的元件,并且在附图中:
图1、举例说明包括根据本发明特定实施例形成部分的复合焊接区的一部分半导体芯片的横截面图;
图2、举例说明包括根据本发明特定实施例的复合焊接区的半导体芯片的横截面图;
图3、举例说明根据本发明的另一实施例所完成的复合焊接区的横截面图;
图4、图解说明图3所举例说明的焊接区的自表面向下的视图;
图5、举例说明相当于与一些根据本发明的复合焊接区对应的一些潜在支撑结构图形的一些自表面向下的视图;和
图6、举例说明根据本发明特定实施例制作复合焊接区的方法流程图。
具体实施方式
精通技术的人知道,为了简单和清楚地用图解说明图中的一些元件而不一定按比例绘图。例如,为了有助于提高对本发明实施例的理解,图中某些元件的尺寸可能相对于其他元件被放大了。
概括来说,本发明提供耐在用探针探测操作、封装操作或利用焊接区的其他类似的后制作操作期间可能施加的外力的复合焊接区。复合焊接区包括在半导体衬底上形成的非自纯化导电焊接区。然后在导电焊接区上形成绝缘层。去除部分绝缘层以使绝缘层成为有穿孔的而露出部分导电焊接区。剩余的绝缘层形成覆盖焊接区的支撑结构。然后形成叠加在焊接区结构上的自钝化导电封顶层,此外绝缘层中的穿孔可以供封顶层和在下面的焊接区的暴露部分之间电接触之用。支撑结构构成保护封顶层和焊接区之间界面的机械阻挡层。当支撑结构仍然与绝缘层的未去除部分连接时,因为被支撑结构缓冲的力是分布在绝缘层二旁边而不是集中在焊接区位置上,所以获得额外的机械强度。
在用探针探测的操作中,支撑结构防止像针之类的探针元件穿透封顶层而扰乱封顶层和导电焊接区(bond pad)之间的界面。如果探针终于还是使大量的封顶层移动,则因为导电材料保留在绝缘层的穿孔里所以焊接线之间或者其他封装结构之间的电接触还是可以保持的。除了这些优点外,通过使穿孔的绝缘层构形以使施加于封顶层的力分布在绝缘层二旁边的较大表面面积,大大地减小由于施力点引起的集成电路内部损坏的潜在可能。
在一种替代的实施例中,通过采用包在复合焊接区中的导电焊接区部分(镶嵌的金属部分)内的绝缘柱获得额外的机械支撑。像这样的柱栓在抛光操作期间通常用于缓解表面凹陷(不平整金属去除)的技术。当把柱栓设置在穿孔的绝缘层支撑结构下方时进一步改进额外的机械支撑。在某些情况下,柱栓也可以增强封顶层与在下面的焊接区结构的粘结作用。
参阅图1-6能够更好地理解本发明。图1包括一部分半导体器件的横截面图的图解说明。半导体器件包括半导体衬底100、场隔离区102和在半导体衬底内形成的掺杂区104。栅绝缘层106覆盖在部分半导体器件衬底100上面,而栅电极110覆盖在栅绝缘层106上面。邻近栅电极层104的侧壁形成垫圈108。使第一层间绝缘层(IDL)116构成图形而形成被填满粘结层112(可选的)和接触填料114的接触孔。粘结层112一般是难熔金属、难熔金属氮化物或者难熔金属或其氮化物的混合物。接触填料114一般包括钨、多晶硅或诸如此类。在沉积粘结层112和接触填料114以后,抛光衬底,以去除没有夹在接触孔当中的粘结层112和接触填料114的部分而形成导电针形接点111。
然后形成叠置在层间绝缘(ILD)层116和导电针形接点111上面的第一层面互连120。采用开槽和抛光工艺方法的配合或者换个办法采用构成图形和蚀刻工艺方法的配合能够形成第一层面互连120。如果采用铜形成第一层面互连120,则可以邻接第一层面互连120形成阻挡层(未表示出)以减少铜进入到周围材料的迁移。
根据同一实施例,使第一层面互连120形成为单镶嵌结构。因此,通过先沉积一部分第二ILD 118,然后蚀刻第二ILD 118而形成构槽,在构槽中沉积第一层面互连120的材料。只要发现第一层面互连120沉积,便用抛光工艺方法去除剩留在被形成的构槽外面的多余材料。
假定第一层面互连120已形成为单镶嵌结构,则继抛光步骤之后形成第二ILD 118的剩余部分。然后在第二ILD 118内形成能包括导电粘结/阻挡薄膜122和铜材料124的互连126。粘结/阻挡薄膜122一般是难熔金属、难熔金属氮化物或者难熔金属或其氮化物的混合物。铜填料124一般是铜或者铜含量至少为90原子百分比的铜合金。铜能够与镁、硫、碳或诸如此类合金化以改进互连的粘结、电迁移或其他性能。虽然在本实施例中图解说明互连126为双镶嵌互连,但是精通技术的人知道用另一种方法能够使互连126形成为与单镶嵌互连或者平版印刷构成图形和蚀刻的互连配合的导电针形接点。在沉积粘结/阻挡薄膜122和铜填料124以后,抛光衬底以去除没有夹在双镶嵌孔之中的粘结/阻挡薄膜122和铜填料124而形成图1中所示的双镶嵌互连。
然后在第二ILD 118和双镶嵌互连126上形成第三ILD 130。第三ILD 130和任何其他在下面的绝缘层可以包含像四乙基原硅酸盐(TEOS)、氮化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)之类材料、像干凝胶、气凝胶、聚酰亚胺、聚对苯二亚甲基、双环丁烷(biscyclobutenes)、碳氟化合物、聚芳基乙醚基料、旋涂玻璃、聚硅氧烷、硅倍半烷(silsesquioxanes)、含碳氧化硅、含碳和氢的氧化硅或其混合物之类的低介电常数材料。第三LID 130和任何其他在下面的绝缘层可以包含具有杨氏模量小于大约50吉帕的材料。在其他的实施例中,可以由其他具有较低屈服强度而所以是更柔韧的材料组成第三ILD 130。虽然图1中用举例所说明的半导体器件部分包含三层面互连层,但是许多互连间能间置在器件层和用来设置通向半导体器件的入口的焊接区的最顶层之中。在图1用举例所说明的实施例中,在最上面的(第三)ILD 130内制作焊接区。
然后在第三ILD 130内以类似于第二ILD 118内用来形成互连126的方法形成包括导电焊接区134的最上面的互连层133。一般来说,最上面的互连层133主要包含铜,但是在其他一些实施例中,可以采用像铝之类的自钝化材料。像互连126的铜填料的情况一样,可以用导电的粘结/阻挡薄膜132使用来形成最上面的互连层133的填料和第三ILD130隔离。根据同一实施例,使导电焊接区134位置控制在离用来接触互连126的通路(层间互连)某个距离。在图1中图解所说明的距离x表示这个距离。
然后在最上面的互连层133和导电焊接区134上形成绝缘(钝化)层136。一般说来,由含氮化合物组成绝缘层。换言之,绝缘层能够包含氧化硅、氮氧化硅、含氢和碳的氧化硅或诸如此类。去除一些绝缘层部分以在绝缘层内形成包括许多支撑结构138的穿孔区域。使穿孔区域构成叠置在形成复合焊接区的面积内的导电焊接区134上以致露出一部分导电焊接区134。在一些实施例中,大多数支撑结构138保持与没有被去除的绝缘层134部分连接。
在图2中继续形成复合焊接区结构。图2举例说明图1中用举例说明的半导体器件部分在后续工艺处理步骤以后的横截面图。根据同一实施例,在绝缘层136的穿孔部分内形成可以包括钽、钛、钨、铬或这些材料的氮化物的阻挡层202。然后在大多数支撑结构138上形成导电封顶层204。一般来说,导电封顶层204包含像铝之类的自钝化材料。导电封顶层204也可以包含镍或钯。接着可以把导电封顶层204连接到导线接头或者在半导体器件封装期间使导电封顶层204与导电凸出部电连接。
绝缘层136中的穿孔使组成封顶层204的自钝化材料和导电焊接区134之间电接触成为可能。然而,支撑结构138构成封顶层204和导电焊接区134之间形成的界面的机械保护罩。注意到如果使支撑结构138与绝缘层136的未去除部分互连,则获得半导体器件对外力的附加保护罩。这是因为施加在复合焊接区中的封顶层204上的外力将分布在绝缘层136的两旁边。该外力可以是由用探针探测、导线焊接、碰撞、封装等等引起的。
为了为在半导体器件和用于与半导体器件连接的封装材料之间的应力消除创造条件,在完成复合焊接区结构以后在半导体器件上可以形成聚酰亚胺层206。包裹聚酰亚胺层206是视使用的特定制造工艺过程而定的可选择的步骤。
图3图解说明在复合焊接区结构中的导电焊接区部分134内包括许多绝缘柱302的发明替代实施例。如图解所说明的那样,一般把绝缘柱302设置在绝缘层136中的穿孔部分内支撑结构138正下方。把绝缘柱302设置在支撑结构138正下方增强支撑结构138构成的机械支撑以便提高复合焊接区结构的坚固性。坚固性的提高是由于力从支撑结构138通过绝缘柱302传递到第三ILD 130所造成的。在支撑结构138下方配置绝缘柱302也有助于不减少为封顶层204和导电焊接区134间界面提供的接触面积。
图4图解说明图3中的复合焊接区结构的自顶向下视图(为了图解说明假定封顶层是透明的)。如图解所说明的那样,绝缘柱302被包在复合焊接区结构内呈阵列格式。包含在绝缘层136的穿孔部分内的支撑结构138呈现为横穿焊接区结构长度的绝缘材料条。虽然一般把图4中的焊接区结构表示成正方形,但是可以做成各种各样形状的焊接区结构,这对于精通技术的人来说是显而易见的。
图5图解说明可以应用于对这些复合焊接区结构中的两个部分之间的界面提供一定程度的机械隔离同时使封顶层与复合焊接区结构中的焊接区部分电连接的许多替代的穿孔图形。每个不同的图形可能对不同的实施例蕴含最理想的优点。穿孔排列图形510构成封顶层和焊接区部分间通路连接阵列。因为在穿孔排列图形510中大部分钝化(绝缘)层被原封不动保留,所以在使用这样的图形时的力容许极限会相对地大于图解说明中的其他图形。
浮置网格图形520设置一种有效地浮动而没有与剩留的绝缘层部分物理连接的游离支撑结构部分。浮置网格图形520相对于可能施加于封顶层的垂直应力提供附加的强度。然而,从保持与剩留的绝缘层部分连接状态的那些图形中减少了分布施加力的面积。
变密度网格结构530可以提供在使探针或其他的测试装置调整到焊接区结构中的特定部分方面的优点。实现上述的优点归因于绝缘材料的有无会造成金属层参差不齐的构形。支撑结构之间的大间隙可以允许金属以能够在较大间隙内保留较少金属材料而所以保持金属填满间隙而不增高到绝缘支撑结构的较浅构形的不平坦方式沉积。一般说来,设计成在复合焊接区结构的中心部分或其他所希望的部位上形成凹坑的图案,因此探针会移向这样的凹陷处。
浮置自由端网格图案540在保持与总体绝缘层物理连接时可以提供由浮置网格图案520相对于垂直应力构成的一些优点。因此,虽然垂直应力强度与浮置网格图形520的垂直应力强度不一样大,但是使施加力的分布保持在较宽的面积上。
变密度人字形网格550可以提供一种用于使探针或类似的测试装置转向焊接区结构上特定位置的替代图形。在变密度人字形网格550的情况中,通过形成沟槽即定向的金属材料道获得变密度人字形网格550以使探针将接触结构而通过沟槽对准焊接区中的特定区域。
图6举例说明用于形成包括复合焊接区结构在内的半导体器件的方法流程图。该方法从在半导体衬底上形成导电焊接区的步骤602开始。一般来说,导电焊接区在组分上主要是铜。导电焊接区的制作包括在导电焊接区内形成绝缘柱。正如对图3所描述的那样,绝缘柱可以对焊合焊接区结构提供附加的机械支撑。
在步骤604时,在导电焊接区上形成绝缘层(钝化层)。在步骤606时,去除部分绝缘层而形成许多叠置在焊接区上面的支撑结构。一般说来,通过蚀刻绝缘层来完成去除该部分的步骤。去除部分绝缘层并且使允许电连接的一部分焊接区露出。
在步骤608时形成在许多支撑结构上面的导电封顶层。导电封顶层电接触一部分焊接区,电接触发生在已被去除第一绝缘层而露出焊接区的部位。导电封顶层可以包括铝,或者也可以由像镍或铂之类的材料构成导电封顶层。
正如对图2中的横截面所描述的那样,用阻挡层可以使封顶层和导电焊接区隔离。一般是,由像钽、钛、钨、铬或者这些材料的氮化物组成阻挡层。在步骤610时蚀刻封顶层而形成复合焊接区结构。
通过把穿孔的绝缘层夹入封顶层和复合焊接区结构中的焊接区之间,在导电结构之间设置一些物理隔离层面时保持焊结区结构中的导电层之间的电连通性。因此,避免由在先技术的焊接区结构中可能由于探针对封顶层和焊接区间界面的损坏所造成的问题。此外,用自钝化材料形成封顶层保证使由于侵蚀或其他外界引起的影响所造成的破坏减到最低程度。穿孔的绝缘层中的支撑结构还有助缓冲外力而因此避免半导体器件损坏。
在以上的详细说明中,参照具体的实施例描述了发明。然而,精通技术的人知道在没有脱离如在下面的权利要求书中所陈述的本发明范围情况下能够作各种各样的变换和变化。因此,说明书和附图是被看成一种图解说明而不是一种限制性的断定,而意在使所有像这样的变换包括在本发明的范围内。
以上按照具体的实施例描述了益处、其他优点和问题的解决。然而,一些益处、优点、问题的解决和可以使任一益处、优点或解决办法被发现或变得更明确的基本原理不被认作是任一或者所有的权利要求中的关键性要求或者基本的细节或要素。正如在本说明书中采用的措词包括或其任何别的变形那样,意在覆盖非排他的包含,以使包括说明的元件的工艺过程、方法、制品或设备不仅包括这些元件而且可以包括没有特意说明的或者是这样的工艺过程、方法、制品或设备所固有的其他元件。

Claims (12)

1.一种制作半导体器件的方法,其特征在于包括步骤:
在半导体衬底(100)上形成导电焊接区(134);
在导电焊接区(134)上形成绝缘层(136);
去除部分绝缘层(136),其中绝缘层(136)的去除部分形成叠置在导电焊接区(134)上的多个支撑结构(138),并且其中绝缘层(136)的去除部分使一部分导电焊接区(134)露出;
形成叠置在多个支撑结构(138)上的导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
在导电焊接区(134)内形成绝缘柱(302),其中至少一部分支撑结构(138)叠置在一部分绝缘柱(302)上。
2.根据权利要求1所述的方法,其特征在于导电焊接区(134)主要包括铜,并且其中导电封顶层(204)包括铝。
3.根据权利要求1的所述方法,其特征在于导电封顶层(204)包括镍或钯。
4.根据权利要求1所述的方法,其特征在于每个所述绝缘柱位于多个支撑结构中一个之下。
5.一种制作半导体器件的方法,其特征在于包括步骤:
在半导体衬底(100)上形成导电焊接区(134);
在导电焊接区(134)上形成绝缘层(136);
去除部分绝缘层(136),其中绝缘层(136)的去除部分形成叠置在导电焊接区(134)上的多个支撑结构(138),并且其中绝缘层(136)的去除部分使一部分导电焊接区(134)露出;
形成叠置在多个支撑结构(138)上的导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
其中许多支撑结构(138)与绝缘层(136)的未去除部分互连。
6.根据权利要求5所述的方法,其中形成的导电焊接区(134)进一步包括在至少一层具有杨氏模量小于50吉帕斯卡的绝缘层(130、118、116)上形成的导电焊接区(134)。
7.一种半导体器件,其特征在于包括:
在半导体衬底(100)上的导电焊接区(134);
在导电焊接区(134)上的绝缘层(136);
叠置在导电焊接区(134)上的多个支撑结构(138);
叠置在多个支撑结构(138)上的导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
在导电焊接区中的绝缘柱(302),其中多个支撑结构(138)中至少之一的至少一部分叠置在一部分绝缘柱(302)上。
8.根据权利要求7所述的半导体器件,其特征在于:所述绝缘柱位于多个支撑结构中一个之下。
9.一种半导体器件,其特征在于包括:
在半导体衬底(100)上的导电焊接区(134);
在导电焊接区(134)上的绝缘层(136);
叠置在导电焊接区(134)上的多个支撑结构(138);
叠置在多个支撑结构(138)上的导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
其中多个支撑结构(138)中的至少一部分与绝缘层(136)的未去除部分互连。
10.一种半导体器件,其特征在于包括:
在半导体衬底(100)上的导电焊接区(134);
在导电焊接区(134)上的绝缘层(136);
叠置在导电焊接区(134)上的多个支撑结构(138);
叠置在多个支撑结构(138)上的导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
在导电焊接区(134)下面至少一层绝缘层(130、118、116)具有小于50吉帕斯卡的杨氏模量。
11.一种制作半导体器件的方法,其特征在于包括步骤:
在半导体衬底(100)上形成导电焊接区(134);
在导电焊接区(134)上形成绝缘层(136);
去除部分绝缘层(136),其中绝缘层(136)被去除的部分形成叠在导电焊接区(134)上的多个支撑结构(138),而且绝缘层(136)被去除的部分暴露一部分导电焊接区(134);
在多个支撑结构(138)上形成导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
在导电封顶层(204)和导电焊接区之间,形成阻挡层(202),其中所述阻挡层叠在所述多个支撑结构之上。
12.一种半导体器件,其特征在于包括:
在半导体衬底(100)上的导电焊接区(134);
在导电焊接区(134)上的绝缘层(136);
叠置在导电焊接区(134)上的多个支撑结构(138);
叠置在多个支撑结构(138)上的导电封顶层(204),其中导电封顶层(204)电接触一部分导电焊接区(134);和
在导电封顶层和导电焊接区之间的阻挡层(202),其中所述阻挡层叠在所述多个支撑结构之上。
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Families Citing this family (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566249B1 (en) * 1998-11-09 2003-05-20 Cypress Semiconductor Corp. Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US7381642B2 (en) 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6495442B1 (en) 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US7405149B1 (en) 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US6936531B2 (en) 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
JP3329380B2 (ja) 1999-09-21 2002-09-30 日本電気株式会社 半導体装置およびその製造方法
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US7271489B2 (en) 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US6727593B2 (en) * 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US7096581B2 (en) * 2002-03-06 2006-08-29 Stmicroelectronics, Inc. Method for providing a redistribution metal layer in an integrated circuit
TW539621B (en) * 2002-04-03 2003-07-01 Benq Corp Ink jet printer with independent driving circuit for preheat and heat maintance
JP3612310B2 (ja) * 2002-06-18 2005-01-19 株式会社東芝 半導体装置
US6909196B2 (en) * 2002-06-21 2005-06-21 Micron Technology, Inc. Method and structures for reduced parasitic capacitance in integrated circuit metallizations
US7692315B2 (en) * 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
KR100448344B1 (ko) * 2002-10-22 2004-09-13 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 제조 방법
US6818996B2 (en) * 2002-12-20 2004-11-16 Lsi Logic Corporation Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps
JP4170103B2 (ja) * 2003-01-30 2008-10-22 Necエレクトロニクス株式会社 半導体装置、および半導体装置の製造方法
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
US6982493B2 (en) 2003-04-03 2006-01-03 International Business Machines Corporation Wedgebond pads having a nonplanar surface structure
DE10337569B4 (de) * 2003-08-14 2008-12-11 Infineon Technologies Ag Integrierte Anschlussanordnung und Herstellungsverfahren
US6960831B2 (en) * 2003-09-25 2005-11-01 International Business Machines Corporation Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad
US6960836B2 (en) * 2003-09-30 2005-11-01 Agere Systems, Inc. Reinforced bond pad
US7372153B2 (en) * 2003-10-07 2008-05-13 Taiwan Semiconductor Manufacturing Co., Ltd Integrated circuit package bond pad having plurality of conductive members
US7459790B2 (en) 2003-10-15 2008-12-02 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7394161B2 (en) 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US6998335B2 (en) * 2003-12-13 2006-02-14 Chartered Semiconductor Manufacturing, Ltd Structure and method for fabricating a bond pad structure
US7629689B2 (en) * 2004-01-22 2009-12-08 Kawasaki Microelectronics, Inc. Semiconductor integrated circuit having connection pads over active elements
US7777223B2 (en) * 2004-03-16 2010-08-17 Pansonic Corporation Semiconductor device
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
TWI283443B (en) 2004-07-16 2007-07-01 Megica Corp Post-passivation process and process of forming a polymer layer on the chip
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7355282B2 (en) * 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) * 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7521805B2 (en) * 2004-10-12 2009-04-21 Megica Corp. Post passivation interconnection schemes on top of the IC chips
JP4777899B2 (ja) * 2004-10-29 2011-09-21 スパンション エルエルシー 半導体装置
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
JP4674522B2 (ja) * 2004-11-11 2011-04-20 株式会社デンソー 半導体装置
JP4517843B2 (ja) * 2004-12-10 2010-08-04 エルピーダメモリ株式会社 半導体装置
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
US7482258B2 (en) * 2005-04-28 2009-01-27 International Business Machines Corporation Product and method for integration of deep trench mesh and structures under a bond pad
TWI269420B (en) 2005-05-03 2006-12-21 Megica Corp Stacked chip package and process thereof
JP4713936B2 (ja) * 2005-05-09 2011-06-29 株式会社東芝 半導体装置
TWI330863B (en) 2005-05-18 2010-09-21 Megica Corp Semiconductor chip with coil element over passivation layer
JP2007019473A (ja) * 2005-06-10 2007-01-25 Nec Electronics Corp 半導体装置
JP2007027400A (ja) * 2005-07-15 2007-02-01 Kawasaki Microelectronics Kk 半導体装置の製造方法及び半導体装置
CN1901161B (zh) 2005-07-22 2010-10-27 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
JP4761880B2 (ja) * 2005-08-09 2011-08-31 パナソニック株式会社 半導体装置
AT502764B1 (de) * 2005-09-12 2010-11-15 Semperit Ag Holding Mischung und verfahren zur herstellung eines vernetzten elastomers sowie vorrichtung zur herstellung eines tauchartikels
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
US7473999B2 (en) 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
US7952206B2 (en) * 2005-09-27 2011-05-31 Agere Systems Inc. Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
US7429795B2 (en) * 2005-09-27 2008-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure
US20070090541A1 (en) * 2005-10-21 2007-04-26 Chih-Chung Tu Bonding pad and display panel
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US7385297B1 (en) * 2005-11-14 2008-06-10 National Semiconductor Corporation Under-bond pad structures for integrated circuit devices
US8552560B2 (en) * 2005-11-18 2013-10-08 Lsi Corporation Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing
JP4995455B2 (ja) * 2005-11-30 2012-08-08 ルネサスエレクトロニクス株式会社 半導体装置
US7947978B2 (en) * 2005-12-05 2011-05-24 Megica Corporation Semiconductor chip with bond area
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
US8344524B2 (en) * 2006-03-07 2013-01-01 Megica Corporation Wire bonding method for preventing polymer cracking
US7808117B2 (en) * 2006-05-16 2010-10-05 Freescale Semiconductor, Inc. Integrated circuit having pads and input/output (I/O) cells
US8420520B2 (en) * 2006-05-18 2013-04-16 Megica Corporation Non-cyanide gold electroplating for fine-line gold traces and gold pads
US7598620B2 (en) * 2006-05-31 2009-10-06 Hebert Francois Copper bonding compatible bond pad structure and method
US8022552B2 (en) 2006-06-27 2011-09-20 Megica Corporation Integrated circuit and method for fabricating the same
US8421227B2 (en) 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
US8592977B2 (en) * 2006-06-28 2013-11-26 Megit Acquisition Corp. Integrated circuit (IC) chip and method for fabricating the same
WO2008015499A1 (en) * 2006-08-01 2008-02-07 Freescale Semiconductor, Inc. Method and apparatus for improving probing of devices
JP5208936B2 (ja) * 2006-08-01 2013-06-12 フリースケール セミコンダクター インコーポレイテッド チップ製造および設計における改良のための方法および装置
US7812448B2 (en) * 2006-08-07 2010-10-12 Freescale Semiconductor, Inc. Electronic device including a conductive stud over a bonding pad region
US7960825B2 (en) * 2006-09-06 2011-06-14 Megica Corporation Chip package and method for fabricating the same
TWI370515B (en) 2006-09-29 2012-08-11 Megica Corp Circuit component
US8193636B2 (en) 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
US7566648B2 (en) * 2007-04-22 2009-07-28 Freescale Semiconductor Inc. Method of making solder pad
JP4522435B2 (ja) * 2007-06-05 2010-08-11 富士通テン株式会社 高周波回路装置、及びレーダ装置
US7652379B2 (en) * 2007-07-23 2010-01-26 National Semiconductor Corporation Bond pad stacks for ESD under pad and active under pad bonding
TWI368286B (en) 2007-08-27 2012-07-11 Megica Corp Chip assembly
US20090079082A1 (en) * 2007-09-24 2009-03-26 Yong Liu Bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
EP2568498A3 (en) * 2007-10-31 2013-04-24 Agere Systems Inc. Bond pad support structure for semiconductor device
KR100933685B1 (ko) * 2007-12-18 2009-12-23 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
US7968975B2 (en) * 2008-08-08 2011-06-28 International Business Machines Corporation Metal wiring structure for integration with through substrate vias
TWI373653B (en) * 2008-09-01 2012-10-01 Au Optronics Corp Conducting layer jump connection structure
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
US8084858B2 (en) * 2009-04-15 2011-12-27 International Business Machines Corporation Metal wiring structures for uniform current density in C4 balls
US8610283B2 (en) 2009-10-05 2013-12-17 International Business Machines Corporation Semiconductor device having a copper plug
KR101051551B1 (ko) * 2009-10-30 2011-07-22 삼성전기주식회사 요철 패턴을 갖는 비아 패드를 포함하는 인쇄회로기판 및 그 제조방법
US8766436B2 (en) * 2011-03-01 2014-07-01 Lsi Corporation Moisture barrier for a wire bond
US8409979B2 (en) 2011-05-31 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
US8742598B2 (en) * 2011-10-05 2014-06-03 Infineon Technologies Ag Semiconductor structure and method for making same
US8766357B2 (en) * 2012-03-01 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for high voltage MOS transistor
US8810024B2 (en) 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US9837303B2 (en) * 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9230852B2 (en) * 2013-02-25 2016-01-05 Texas Instruments Incorporated Integrated circuit (IC) having electrically conductive corrosion protecting cap over bond pads
US9437574B2 (en) 2013-09-30 2016-09-06 Freescale Semiconductor, Inc. Electronic component package and method for forming same
US9515034B2 (en) 2014-01-03 2016-12-06 Freescale Semiconductor, Inc. Bond pad having a trench and method for forming
US10340203B2 (en) * 2014-02-07 2019-07-02 United Microelectronics Corp. Semiconductor structure with through silicon via and method for fabricating and testing the same
US9245846B2 (en) * 2014-05-06 2016-01-26 International Business Machines Corporation Chip with programmable shelf life
US11257774B2 (en) 2014-08-31 2022-02-22 Skyworks Solutions, Inc. Stack structures in electronic devices including passivation layers for distributing compressive force
JP2016111084A (ja) * 2014-12-03 2016-06-20 トヨタ自動車株式会社 半導体装置とその製造方法
US9960130B2 (en) 2015-02-06 2018-05-01 UTAC Headquarters Pte. Ltd. Reliable interconnect
US10833119B2 (en) 2015-10-26 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for front side illuminated image sensor
US9859213B2 (en) * 2015-12-07 2018-01-02 Dyi-chung Hu Metal via structure
US9768135B2 (en) * 2015-12-16 2017-09-19 Monolithic Power Systems, Inc. Semiconductor device having conductive bump with improved reliability
US9761548B1 (en) * 2016-05-19 2017-09-12 Infineon Technologies Ag Bond pad structure
US9852985B1 (en) * 2016-06-27 2017-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive terminal on integrated circuit
KR102627991B1 (ko) * 2016-09-02 2024-01-24 삼성디스플레이 주식회사 반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법
CN106601715A (zh) * 2016-12-21 2017-04-26 成都芯源系统有限公司 集成电路芯片及其制作方法
CN108269776A (zh) * 2016-12-30 2018-07-10 应广科技股份有限公司 焊垫下电路结构及其制造方法
US10192837B1 (en) 2017-12-20 2019-01-29 Nxp B.V. Multi-via redistribution layer for integrated circuits having solder balls
US11616046B2 (en) * 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11282744B2 (en) * 2019-09-30 2022-03-22 Systems On Silicon Manufacturing Co. Pte. Ltd. Enhanced intermetal dielectric adhesion
US11462501B2 (en) * 2019-10-25 2022-10-04 Shinko Electric Industries Co., Ltd. Interconnect substrate and method of making the same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4723197A (en) * 1985-12-16 1988-02-02 National Semiconductor Corporation Bonding pad interconnection structure
US5719448A (en) 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
JP2916326B2 (ja) * 1992-06-11 1999-07-05 三菱電機株式会社 半導体装置のパッド構造
US5248903A (en) 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
JPH08213422A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置およびそのボンディングパッド構造
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
KR0170316B1 (ko) 1995-07-13 1999-02-01 김광호 반도체 장치의 패드 설계 방법
JP3457123B2 (ja) * 1995-12-07 2003-10-14 株式会社リコー 半導体装置
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
US5942448A (en) * 1997-02-24 1999-08-24 Sarnoff Corporation Method of making contacts on an integrated circuit
JPH1167763A (ja) * 1997-08-21 1999-03-09 Sony Corp 半導体装置およびその製造方法
JPH1197525A (ja) * 1997-09-19 1999-04-09 Hitachi Ltd 半導体装置およびその製造方法
JPH11186434A (ja) 1997-12-18 1999-07-09 Kyocera Corp 多層配線基板
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
JPH11330121A (ja) * 1998-05-14 1999-11-30 Sanyo Electric Co Ltd 半導体装置とその製造方法
US6187680B1 (en) * 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
US6156660A (en) * 1999-02-05 2000-12-05 Taiwan Semiconductor Manufacturing Company Method of planarization using dummy leads
US6197613B1 (en) * 1999-03-23 2001-03-06 Industrial Technology Research Institute Wafer level packaging method and devices formed
US6703286B1 (en) * 1999-07-29 2004-03-09 Taiwan Semiconductor Manufacturing Company Metal bond pad for low-k inter metal dielectric
US6191023B1 (en) 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion

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US6803302B2 (en) 2004-10-12
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