CN1619809A - 具有纳米管状孔隙的工程绝缘材料的互连结构 - Google Patents
具有纳米管状孔隙的工程绝缘材料的互连结构 Download PDFInfo
- Publication number
- CN1619809A CN1619809A CNA2004100835214A CN200410083521A CN1619809A CN 1619809 A CN1619809 A CN 1619809A CN A2004100835214 A CNA2004100835214 A CN A2004100835214A CN 200410083521 A CN200410083521 A CN 200410083521A CN 1619809 A CN1619809 A CN 1619809A
- Authority
- CN
- China
- Prior art keywords
- insulating material
- interconnection
- interconnection structure
- path
- hard mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/683,333 | 2003-10-10 | ||
US10/683,333 US7268432B2 (en) | 2003-10-10 | 2003-10-10 | Interconnect structures with engineered dielectrics with nanocolumnar porosity |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1619809A true CN1619809A (zh) | 2005-05-25 |
CN100555620C CN100555620C (zh) | 2009-10-28 |
Family
ID=34422719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100835214A Expired - Fee Related CN100555620C (zh) | 2003-10-10 | 2004-10-09 | 具有纳米管状孔隙的工程绝缘材料的互连结构及其制造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7268432B2 (zh) |
CN (1) | CN100555620C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101982879A (zh) * | 2010-10-15 | 2011-03-02 | 复旦大学 | 一种低介电常数介质与铜互连的结构及其集成方法 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060022342A1 (en) * | 2001-10-16 | 2006-02-02 | Canon Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
US7268432B2 (en) * | 2003-10-10 | 2007-09-11 | International Business Machines Corporation | Interconnect structures with engineered dielectrics with nanocolumnar porosity |
US7517637B2 (en) * | 2004-03-19 | 2009-04-14 | International Business Machines Corporation | Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same |
US7192878B2 (en) * | 2005-05-09 | 2007-03-20 | United Microelectronics Corp. | Method for removing post-etch residue from wafer surface |
KR100685734B1 (ko) * | 2005-06-07 | 2007-02-26 | 삼성전자주식회사 | 다공성 스핀 온 글래스 조성물, 이의 제조 방법 및 이를이용한 다공성 실리콘 산화막 제조 방법 |
GR1006890B (el) * | 2005-09-16 | 2010-07-19 | Ευαγγελος Γογγολιδης | Μεθοδος για την κατασκευη επιφανειων μεγαλου επιφανειακου λογου και μεγαλου λογου ασυμμετριας σε υποστρωματα. |
US7348280B2 (en) * | 2005-11-03 | 2008-03-25 | International Business Machines Corporation | Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions |
US7488661B2 (en) * | 2006-03-07 | 2009-02-10 | International Business Machines Corporation | Device and method for improving interface adhesion in thin film structures |
JP2007300012A (ja) * | 2006-05-02 | 2007-11-15 | Seiko Epson Corp | 金属配線形成方法、アクティブマトリクス基板の製造方法、デバイス及び電気光学装置並びに電子機器 |
US7396757B2 (en) * | 2006-07-11 | 2008-07-08 | International Business Machines Corporation | Interconnect structure with dielectric air gaps |
US7569469B2 (en) * | 2006-08-03 | 2009-08-04 | International Business Machines Corporation | Dielectric nanostructure and method for its manufacture |
JP2009094378A (ja) * | 2007-10-11 | 2009-04-30 | Panasonic Corp | 半導体装置及びその製造方法 |
US7828986B2 (en) * | 2007-10-29 | 2010-11-09 | International Business Machines Corporation | Forming surface features using self-assembling masks |
US8216909B2 (en) | 2009-03-11 | 2012-07-10 | International Business Machines Corporation | Field effect transistor with air gap dielectric |
US8647977B2 (en) * | 2011-08-17 | 2014-02-11 | Micron Technology, Inc. | Methods of forming interconnects |
JP6068123B2 (ja) * | 2012-12-14 | 2017-01-25 | 上村工業株式会社 | プリント配線基板の製造方法およびその方法により製造されたプリント配線基板 |
US10345702B2 (en) | 2017-08-24 | 2019-07-09 | International Business Machines Corporation | Polymer brushes for extreme ultraviolet photolithography |
US10968522B2 (en) * | 2018-04-02 | 2021-04-06 | Elwha Llc | Fabrication of metallic optical metasurfaces |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5869880A (en) * | 1995-12-29 | 1999-02-09 | International Business Machines Corporation | Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers |
JP3328931B2 (ja) * | 1999-02-05 | 2002-09-30 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP3946471B2 (ja) * | 2001-07-24 | 2007-07-18 | シャープ株式会社 | 半導体装置の製造方法 |
JP3778045B2 (ja) * | 2001-10-09 | 2006-05-24 | 三菱電機株式会社 | 低誘電率材料の製造方法および低誘電率材料、並びにこの低誘電率材料を用いた絶縁膜および半導体装置 |
US7268432B2 (en) * | 2003-10-10 | 2007-09-11 | International Business Machines Corporation | Interconnect structures with engineered dielectrics with nanocolumnar porosity |
US8358011B1 (en) * | 2007-09-07 | 2013-01-22 | International Business Machines Corporation | Interconnect structures with engineered dielectrics with nanocolumnar porosity |
US7408206B2 (en) * | 2005-11-21 | 2008-08-05 | International Business Machines Corporation | Method and structure for charge dissipation in integrated circuits |
-
2003
- 2003-10-10 US US10/683,333 patent/US7268432B2/en not_active Expired - Lifetime
-
2004
- 2004-10-09 CN CNB2004100835214A patent/CN100555620C/zh not_active Expired - Fee Related
-
2012
- 2012-06-23 US US13/531,518 patent/US8901741B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101982879A (zh) * | 2010-10-15 | 2011-03-02 | 复旦大学 | 一种低介电常数介质与铜互连的结构及其集成方法 |
Also Published As
Publication number | Publication date |
---|---|
US20050079719A1 (en) | 2005-04-14 |
US7268432B2 (en) | 2007-09-11 |
US8901741B2 (en) | 2014-12-02 |
US20120261823A1 (en) | 2012-10-18 |
CN100555620C (zh) | 2009-10-28 |
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