CN1309074C - 衬底上的电互连结构及其制作方法 - Google Patents
衬底上的电互连结构及其制作方法 Download PDFInfo
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- CN1309074C CN1309074C CNB2004100549212A CN200410054921A CN1309074C CN 1309074 C CN1309074 C CN 1309074C CN B2004100549212 A CNB2004100549212 A CN B2004100549212A CN 200410054921 A CN200410054921 A CN 200410054921A CN 1309074 C CN1309074 C CN 1309074C
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
步骤 | 条件 |
旋涂 | 粘附促进剂 |
热板烘烤 | 310℃/90秒 |
旋涂 | 第一ILD层(SiLK) |
热板烘烤 | 310℃/2min. |
旋涂 | CMP保护层(HOSP BESt) |
热板烘烤 | 310℃/2min |
烘焙 | 炉子-415℃/60min. |
CVD沉积 | 碳化硅 |
Claims (47)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/628,925 | 2003-07-28 | ||
US10/628,925 US7071539B2 (en) | 2003-07-28 | 2003-07-28 | Chemical planarization performance for copper/low-k interconnect structures |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1577830A CN1577830A (zh) | 2005-02-09 |
CN1309074C true CN1309074C (zh) | 2007-04-04 |
Family
ID=34103488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100549212A Expired - Fee Related CN1309074C (zh) | 2003-07-28 | 2004-07-21 | 衬底上的电互连结构及其制作方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7071539B2 (zh) |
JP (1) | JP4709506B2 (zh) |
KR (1) | KR100612064B1 (zh) |
CN (1) | CN1309074C (zh) |
TW (1) | TWI339873B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102810508A (zh) * | 2012-08-16 | 2012-12-05 | 上海华力微电子有限公司 | 改善刻蚀形貌并提升可靠性的铜互连制备方法 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
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US6919636B1 (en) * | 2003-07-31 | 2005-07-19 | Advanced Micro Devices, Inc. | Interconnects with a dielectric sealant layer |
US6992003B2 (en) * | 2003-09-11 | 2006-01-31 | Freescale Semiconductor, Inc. | Integration of ultra low K dielectric in a semiconductor fabrication process |
US7282148B2 (en) * | 2003-10-30 | 2007-10-16 | International Business Machines Corporation | Porous silicon composite structure as large filtration array |
US7695897B2 (en) * | 2006-05-08 | 2010-04-13 | International Business Machines Corporation | Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer |
US20090079072A1 (en) * | 2007-09-21 | 2009-03-26 | Casio Computer Co., Ltd. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
TWI419268B (zh) * | 2007-09-21 | 2013-12-11 | Teramikros Inc | 半導體裝置及其製造方法 |
US8587124B2 (en) | 2007-09-21 | 2013-11-19 | Teramikros, Inc. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
JP2009117743A (ja) * | 2007-11-09 | 2009-05-28 | Panasonic Corp | 半導体装置及びその製造方法 |
JP4666028B2 (ja) * | 2008-03-31 | 2011-04-06 | カシオ計算機株式会社 | 半導体装置 |
US20100176513A1 (en) * | 2009-01-09 | 2010-07-15 | International Business Machines Corporation | Structure and method of forming metal interconnect structures in ultra low-k dielectrics |
JP2010171064A (ja) * | 2009-01-20 | 2010-08-05 | Panasonic Corp | 半導体装置及びその製造方法 |
US8617986B2 (en) | 2009-11-09 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the integrated circuits |
US8889544B2 (en) * | 2011-02-16 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric protection layer as a chemical-mechanical polishing stop layer |
US9260571B2 (en) | 2012-05-24 | 2016-02-16 | Lawrence Livermore National Security, Llc | Hybrid polymer networks as ultra low ‘k’ dielectric layers |
US9330989B2 (en) | 2012-09-28 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for chemical-mechanical planarization of a metal layer |
US8980740B2 (en) | 2013-03-06 | 2015-03-17 | Globalfoundries Inc. | Barrier layer conformality in copper interconnects |
JP6302644B2 (ja) * | 2013-11-11 | 2018-03-28 | 株式会社ディスコ | ウェーハの加工方法 |
KR102165266B1 (ko) | 2014-04-03 | 2020-10-13 | 삼성전자 주식회사 | 반도체 소자 및 반도체 패키지 |
CN107758607A (zh) * | 2017-09-29 | 2018-03-06 | 湖南大学 | 一种高深宽比高保形纳米级正型结构的制备方法 |
US10573808B1 (en) * | 2018-08-21 | 2020-02-25 | International Business Machines Corporation | Phase change memory with a dielectric bi-layer |
CN109768121A (zh) * | 2018-12-29 | 2019-05-17 | 浙江师范大学 | 用氧化钨对单晶硅表面进行钝化的方法 |
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US20010004550A1 (en) * | 1999-12-13 | 2001-06-21 | Stmicroelectronics S.A. | Damascene-type interconnection structure and its production process |
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US5470802A (en) * | 1994-05-20 | 1995-11-28 | Texas Instruments Incorporated | Method of making a semiconductor device using a low dielectric constant material |
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US6265780B1 (en) * | 1998-12-01 | 2001-07-24 | United Microelectronics Corp. | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
JP3657788B2 (ja) * | 1998-10-14 | 2005-06-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
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- 2004-07-09 KR KR1020040053467A patent/KR100612064B1/ko not_active IP Right Cessation
- 2004-07-19 TW TW093121459A patent/TWI339873B/zh not_active IP Right Cessation
- 2004-07-21 CN CNB2004100549212A patent/CN1309074C/zh not_active Expired - Fee Related
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CN102810508A (zh) * | 2012-08-16 | 2012-12-05 | 上海华力微电子有限公司 | 改善刻蚀形貌并提升可靠性的铜互连制备方法 |
Also Published As
Publication number | Publication date |
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CN1577830A (zh) | 2005-02-09 |
KR20050013492A (ko) | 2005-02-04 |
JP4709506B2 (ja) | 2011-06-22 |
US7071539B2 (en) | 2006-07-04 |
TWI339873B (en) | 2011-04-01 |
TW200515534A (en) | 2005-05-01 |
US7407879B2 (en) | 2008-08-05 |
KR100612064B1 (ko) | 2006-08-14 |
US20050023689A1 (en) | 2005-02-03 |
JP2005051214A (ja) | 2005-02-24 |
US20060166012A1 (en) | 2006-07-27 |
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