CN101573787B - 制造互连结构的方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000010949 copper Substances 0.000 claims abstract description 53
- 229910052802 copper Inorganic materials 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000010936 titanium Substances 0.000 claims abstract description 12
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 109
- 239000000463 material Substances 0.000 claims description 43
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 28
- 239000003361 porogen Substances 0.000 claims description 22
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- 238000000354 decomposition reaction Methods 0.000 claims description 11
- 238000012797 qualification Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 239000004088 foaming agent Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- 241000784732 Lycaena phlaeas Species 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 150000001252 acrylic acid derivatives Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
描述了采用铜填充工艺来填充沟槽(12)的镶嵌工艺。铜填充(20)开始于包括铜和钛的沉积种子层(52)。在铜填充工艺中,一些钛迁移至表面。在氮气环境下对该结构进行退火,这在铜填充(20)的表面上产生自对准的TiN阻挡(24)。可以在同一退火工艺中产生空气间隙(26)。该工艺可以被用来形成多层结构。
Description
技术领域
本发明涉及一种制造互连结构的方法,具体来讲涉及(但非排他性的)一种多层互连结构,以及一种通过这种方法形成的结构。
背景技术
集成电路芯片的特征尺寸不断减小,随着这种发展,这些芯片的性能更加取决于互连的性能,具体地讲是传输延迟。另外,这些芯片的不断增大的复杂性和小尺寸增大了对多层互连的需要。
采用所谓的“镶嵌”工艺可以制造这种互连。形成电介质层,然后,蚀刻掉要形成互连的地方,以留下沟槽的图案。然后,沉积互连金属,互连金属填充了沟槽,但留下了不平坦的表面以及在表面上留下了过量的互连金属。然后,采用化学机械抛光(CMP)步骤来使该结构平坦,以去除表面上过量的互连金属,并提供用于进一步处理的合适的平坦表面。
通常,由交替的互连层和通路层逐步建立多层结构。互连层包括水平互连,并且通路层提供了多互连层的不同层之间和到达下面的半导体芯片的垂直连接。
单个镶嵌工艺对每个层分别形成图案,而双镶嵌工艺在单个步骤序列中形成互连层和下面的通路层的图案并填充互连层和下面的通路层。双镶嵌工艺更有效率,并可以提供成本相对较低的方案。
传输延迟通常取决于互连的电阻和电容。出于这个原因,作为低电阻材料的铜(Cu)越来越受到人们的青睐。可以将铜与具有较低介电常数的绝缘材料(已知为低k材料)结合起来,来提供具有良好性能的互连。
为了更进一步地改善性能,可以采用空气间隙来包围这些互连。由于空气具有为1的介电常数k,这可以提供被低k电介质(其通常具有3左右的介电常数k)所包围的互连的改善的性能。在EP1,577,940中指出了一种制造具有空气间隙的多层互连的方法。由于铜可以很容易地通过硅并扩散到较小范围的二氧化硅,需要在铜的周围采用阻挡层。否则,铜可以扩散,并“毁掉”这个晶体管。通常,在铜互连的底部和侧面采用TaN/Ta或TiN阻挡层,并在铜互连的顶部采用SiC(N)或SiN层,来避免铜扩散。遗憾的是,SiC(N)或SiN层具有相对较高的介电常数,在SiC(N)的情况下大约是5。这对于互连电容有着显著的贡献。另外一个难题是在铜和SiC(N)之间的交界处会出现铜电子迁移(EM),这降低了产品的寿命。
发明内容
根据本发明,提供了一种形成铜互连结构的方法,包括:
(a)形成图案限定层;
(b)在该图案限定层中蚀刻出沟槽;
(c)在该沟槽侧壁上沉积阻挡材料;
(d)在阻挡材料上沉积铜和钛的种子层;
(e)沉积铜来填充这些沟槽;
(f)执行化学机械抛光步骤;以及
(g)在周围为氮气的环境下对该结构进行退火,使钛在铜的暴露表面与氮气进行反应,来在该铜上形成自对准的TiN阻挡。
周围的氮气环境应当是基本上没有氧气的。以这种方式形成自对准的TiN阻挡,避免了对形成单独的SiC(N)覆盖层的需要。这减少了工艺步骤的数量,而且还减小了最终产品中的互连的互连电容。
优选地,在周围为氮气的环境下对该结构进行退火的步骤(g)使该图案限定层在沟槽中的铜之间形成了空气间隙。以这种方式,该空气间隙还有助于减小互连电容。
为了实现这个目的,图案限定层可以包括分解温度在350℃以上的致孔剂材料,而且,可以在该致孔剂材料的分解温度或高于该温度的条件下执行该退火步骤(g)。
图案限定层还可以包括在该致孔剂材料上的该图案限定层的上表面处的硬掩模层。
该方法可以被用于多层互连结构中。在一些实施例中,在退火步骤(g)之后,通过下列步骤继续该工艺,来形成通路层和另外的互连层:
(h)在铜上沉积层间电介质;
(i)对层间电介质形成图案,来在层间电介质中形成通路孔;
(j)在该层间电介质上沉积第二图案限定层,来用第二图案限定层的材料填充通路孔;
(k)在第二图案限定层上形成掩模图案;
(l)采用掩模图案作为掩模来蚀刻掉第二图案限定层,以去除通路孔中的第二图案限定层的材料,并在第二图案限定层中形成沟槽;
(m)在沟槽的侧壁上和通路孔的侧壁上沉积阻挡材料;
(n)在阻挡材料上沉积铜和钛的种子层;
(o)沉积铜,来用互连层铜填充这些沟槽,并用通路层铜来填充通路孔;
(p)执行化学机械抛光步骤;以及
(q)在周围为氮气的环境下对该结构进行退火,使钛在互连层铜的暴露表面上与氮气反应,以在互连层铜上形成自对准的TiN阻挡。
可以用分解温度高于350℃的致孔剂材料形成第二图案限定层,可以在该致孔剂材料的分解温度或高于该温度的条件下执行退火步骤(q),来形成互连层铜之间的间隙。
第一和第二图案限定层的每一个均可以包括上表面上的硬掩模层,硬掩模层和层间电介质可以是同一材料。
为了形成其他的层,可以重复步骤(h)至(q),来形成多层互连结构的至少一个附加层。
附图说明
为了更好地理解本发明,参照附图,单纯通过示例对一些实施例进行说明,其中,图1至图15示出了根据本发明方法的侧视图。
这些附图只是示意性的,并没有按照比例绘制。对不同附图中的相同部件给予了相同的参考标记。
具体实施方式
参照图1,形成了在其上表面具有接触4的半导体衬底2。有机致孔剂材料6沉积在整个表面上,之后,多孔氧化物之类的硬掩模层8也沉积在整个表面上。下文将讨论用作致孔剂和硬掩模层的合适的材料。对光致抗蚀剂10形成图案,以形成掩模。
接下来,如图2所示,一起对致孔剂材料6和硬掩模层8进行蚀刻,来形成沟槽12的图案。然后去除光致抗蚀剂10。由于致孔剂材料6和硬掩模层8一起形成图案,所以将他们一起称为图案限定层9。
沉积阻挡金属层14,之后沉积示意性示出的铜-钛种子层16。这是采用铜-钛靶通过物理汽相沉积(PVD)形成的。钛的量可以小于10%,优选在0.5%到5%。
参照图3,随后在电镀步骤形成大量铜18,来用互连层铜20填充沟槽20,并在表面上留下过量的铜22。
化学机械抛光步骤去除过量的铜22,并且如果需要的话,化学机械抛光步骤可以部分去除硬掩模层8,从而产生图4中所示的结构。接下来,在氮气环境下,在400℃或更高的温度下对该结构进行退火。种子层16的钛扩散通过沉积的铜18,一些钛抵达了互连层铜的上表面,在这里,它通过与周围的氮气进行反应,形成了氮化钛自对准的钝化层24。退火温度越高,扩散越快。
另外,同一退火步骤使致孔剂材料6分解,留下与硬掩模8的空气间隙26,如图5所示。这完成了最底层的互连层28。继续工艺,采用双镶嵌工艺形成通路层30和另外一个互连层32(图9)。
首先,形成层间电介质材料层34,该层间电介质材料层将被用来形成通路层30,如图6所示。光致抗蚀剂被沉积,并被用来形成掩模图案36(图7)。然后,这个掩模图案被用来蚀刻层间电介质材料层34中的通路孔38,如图8所示。
然后沉积致孔剂材料,来填充通路孔38并在层间电介质材料层34上提供致孔剂材料40。然后,在致孔剂材料层40上沉积硬掩模层42,如图9所示。硬掩模层42和致孔剂材料层40一起组成另一个图案限定层44,该图案限定层将形成另一个互连层32。
在该图案限定层44上形成光致抗蚀剂的掩模图案46,执行蚀刻步骤来蚀刻该图案限定层44中的沟槽48,并去除通路孔38中的致孔剂材料(图11)。然后去除掩模图案46。
在通路孔38和沟槽48的侧壁上沉积阻挡层50,之后,像以前一样沉积铜-钛种子层52(图12)。
然后执行电镀步骤来沉积铜53。这个步骤用通路层铜54填充了通路孔38,并用互连层铜56填充了另一个图案限定层44中的沟槽,如图13所示。过量的铜58保留在表面上。用化学机械抛光步骤去除过量的铜,如图14所示。
然后在氮气环境下执行退火步骤,这个步骤在互连层铜56的顶部形成了TiN阻挡层60,还通过致孔剂材料层40的致孔剂的分解形成空气间隙62,从而产生图15中所示的具有完成的互连层28、通路层30和另一个互连层32的结构。
然后,根据需要,可以重复图6至图15所示的步骤,来形成多个层。
用于致孔剂材料层6、40的致孔剂材料的合适选择包括诸如包括抗蚀剂的丙烯酸盐(丙烯酸酯)族的聚合物之类的可以是氟化的聚合物。优选的是分解温度在350℃以上的、优选400℃左右的材料。从供应商处可以得到几种合适的材料,这些供应商包括ShipleyXP0733(TM)、JSRMicro TDP-C1002(TM)和Dow Chemical’s Houdini(TM)。
硬掩模层8和层间电介质材料层34可以方便地由同一材料形成。它们应当展现出对致孔剂的良好的蚀刻选择性。特别优选低k材料。特别优选那些可以在商业上获得的多孔材料,例如作为BlackDiamond(TM)或Aurora(TM)出售的材料。
在最后的退火步骤中,本发明的工艺对该致孔剂进行分解,从而对于剩下的工艺步骤保持存在有致孔剂。这保证了IC的结构完整性,并且避免了对额外的或特定的光刻步骤的需求。
在用来形成空气间隙的同一退火步骤中形成TiN阻挡层,这减少了工艺步骤的数量。
该方法可以提供芯片设计者可能需要的多个空气间隙层。
用铜-钛种子层来代替通常的铜种子层使得更容易引入到生产环境中。
根据本发明的方法的一个特别的好处是避免了需要在本发明的TiN阻挡层的位置上形成标准的SiC(N)覆盖层,这可以显著地减小总电容,并从而改善互连速度。
本发明可以应用于任何需要多层互连方案的情况,并可以很容易地适应于现有的半导体工艺流程中。
Claims (8)
1.一种形成铜互连结构的方法,包括:
(a)形成第一图案限定层(9);
(b)在所述第一图案限定层(9)中蚀刻出第一沟槽(12);
(c)在所述第一沟槽侧壁上沉积阻挡材料(14);
(d)在所述阻挡材料(14)上沉积铜和钛的种子层(16);
(e)沉积铜(18)来填充所述第一沟槽(12);
(f)执行化学机械抛光步骤;以及
(g)在周围为氮气的环境下对所述结构进行退火,使钛在铜的暴露表面上与氮气发生反应,来在铜上形成自对准的TiN阻挡(24);
其特征在于,在周围为氮气的环境下对所述结构进行退火的步骤(g)使所述第一图案限定层(9)在所述第一沟槽中的铜之间形成空气间隙(26)。
2.根据权利要求1所述的方法,其中,所述第一图案限定层(9)包括分解温度在350℃以上的致孔剂材料(6),而且其中,在所述致孔剂材料(6)的分解温度或高于所述分解温度的条件下执行退火步骤(g)。
3.根据权利要求2所述的方法,其中,所述第一图案限定层(9)包括位于所述致孔剂材料上的第一图案限定层(9)上表面上的硬掩模层(8)。
4.根据之前任何一项权利要求所述的方法,在退火步骤(g)之后,其还包括:
(h)沉积层间电介质(34);
(i)对所述层间电介质(34)形成图案,来在所述层间电介质中形成通路孔(38);
(j)在所述层间电介质(34)上沉积第二图案限定层(44),来用第二图案限定层(44)的材料填充所述通路孔(38);
(k)在所述第二图案限定层(44)上形成掩模图案(46);
(l)采用所述掩模图案(46)作为掩模来蚀刻掉第二图案限定层(44),以去除所述通路孔(38)中的第二图案限定层(44)的材料,并在所述第二图案限定层(44)中形成第二沟槽(48);
(m)在所述第二沟槽(48)的侧壁上和所述通路孔(38)的侧壁上沉积阻挡材料(50);
(n)在所述阻挡材料(50)上沉积铜和钛的种子层(52);
(o)沉积铜(53),来用互连层铜(56)填充所述第二沟槽,并用通路层铜(54)来填充所述通路孔;
(p)执行化学机械抛光步骤;以及
(q)在周围为氮气的环境下对所述结构进行退火,使钛在互连层铜(56)的暴露表面上与所述氮气发生反应,以在互连层铜(56)上形成自对准的TiN阻挡(60)。
5.根据权利要求4所述的方法,其中,所述第二图案限定层(44)包括分解温度高于350℃的致孔剂材料(40),以及其中,在所述致孔剂材料(40)的分解温度或高于该分解温度的条件下执行退火步骤(q),以在互连层铜(56)之间形成空气间隙(62)。
6.根据权利要求4所述的方法,其中,第一图案限定层(9)和第二图案限定层(44)的每一个均包括上表面上的硬掩模层(8,42),并且硬掩模层(8,42)和层间电介质(34)是同一种材料。
7.根据权利要求4所述的方法,包括重复步骤(h)至(q),来形成多层互连结构的至少一个附加层。
8.根据权利要求3或6所述的方法,其中,硬掩模层(8,42)是介电常数小于3的低k电介质。
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US9082770B2 (en) * | 2012-10-24 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company Limited | Damascene gap structure |
US9396990B2 (en) * | 2013-01-31 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Capping layer for improved deposition selectivity |
US9252049B2 (en) * | 2013-03-06 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming interconnect structure that avoids via recess |
US9343400B2 (en) * | 2013-03-13 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene gap filling process |
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