CN1309042C - 半导体器件的制造方法 - Google Patents
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Abstract
根据本发明的一个方案,提供一种半导体器件的制造方法,包括:形成至少一个互连层,具有低介电常数绝缘膜(1)和埋置在低介电常数绝缘膜(1)中的互连(2);形成在互连层中延伸的沟槽或孔(12);对具有沟槽或孔(12)的互连层进行热处理;以及在沟槽或孔(12)中埋置材料(13)。
Description
技术领域
本发明涉及半导体器件的制造方法,特别涉及使用低介电常数绝缘膜制备具有互连层的半导体器件的方法。
背景技术
随着半导体器件的尺寸缩小和速度增加,互连结构已由单级结构发展为多级结构。现已开发和制备出具有五层或更多层金属互连结构的半导体器件。随着不断小型化,产生了互连之间的所谓的寄生电容和互连电阻引起的信号传输延迟问题。近来,由多级互连结构造成的信号传输延迟大大降低了半导体器件的速度,现已采用了多种措施。
一般来说,互连之间的寄生电容和互连电阻造成信号传输延迟。为了降低互连电阻,现已研究由常规的铝互连改变成低电阻的铜互连。使用铜需要埋置的互连结构,是由于现有的技术很难通过类似于常规方法的干蚀刻将铜加工成互连形状。为了降低互连之间的电容,代替使用常规的硅氧化物(SiO2)通过CVD的绝缘膜,现已研究了采用通过CVD的SiOF膜、通过旋转涂覆的所谓SOG(具有SiCO成分的旋涂玻璃)、或者有机树脂(聚合物)膜形成低介电常数绝缘膜。
SiOF膜的相对介电常数通常降低到约3.4(常规的SiO2膜为3.9)。然而,就膜的稳定性而言,进一步降低相对介电常数实际上很难。相反,如SOG膜或有机树脂膜的低介电常数膜的相对介电常数可以降低到约2.0,由此目前对应用这些膜的研究很热门。近些年来,通过CVD的SiCO膜变得很普及。
对于形成埋置互连的代表性方法,在预先形成有埋置互连的底层上形成互连层的步骤为(1)形成蚀刻终止膜,(2)形成层间介质膜,(3)形成帽盖膜,(4)形成用于过孔的掩模,(5)形成过孔,(6)除去掩模,(7)形成用于互连沟槽的掩模,(8)形成互连沟槽,(9)除去掩模,(10)在蚀刻终止膜中形成开口,(11)形成阻挡金属和籽晶Cu膜,(12)形成镀覆Cu膜,以及(13)通过CMP抛光和平面化以及形成埋置的Cu互连。一般来说,层间介质膜为低介电常数膜,帽盖膜为常规的SiO2膜。
目前,叠置LSI的多级互连,并通过重复以上工艺同样叠置了使用低介电常数膜的互连层。
对于使用低介电常数膜的层间介质膜,如上所述使用通过旋转涂覆或CVD的SiCO膜。现已知低介电常数膜在以下步骤中会受损伤:膜淀积步骤(3)、干蚀刻步骤(5)、(8)和(10)、以及使用等离子体灰化和用化学试剂的掩模除去步骤(6)和(9),特别是步骤(3)、(6)和(9)。对于SiCO膜,在这些步骤期间,膜中的有机成分(C成分)会受影响,在膜中形成了Si-OH基作为水吸附部位,以增加膜的收湿性。如果在绝缘膜中吸收了水,那么在随后的步骤中,特别是热处理之中,它氧化了金属互连,并降低了互连的可靠性。
发明内容
根据本发明的一个方案,提供一种半导体器件的制造方法,包括:形成至少一个互连层,具有低介电常数绝缘膜(1)和埋置在低介电常数绝缘膜(1)中的互连(2);形成在互连层中延伸的沟槽或孔(12);对具有沟槽或孔(12)的互连层进行热处理;以及在沟槽或孔(12)中埋置材料(13)。
附图说明
图1示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的一个步骤的部分剖面图;
图2示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图3示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图4示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图5示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图6示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图7示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图8示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图9示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图10示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图11示出了在根据一个实施例的半导体器件的制备方法中形成多级互连结构的另一个步骤的部分剖面图;
图12示出了在多级互连结构形成步骤中的损伤层的剖面图;
图13示出了在根据一个实施例的半导体器件的制备方法中形成互连故障防止结构的一个步骤的部分剖面图;
图14示出了在根据一个实施例的半导体器件的制备方法中形成互连故障防止结构的另一个步骤的部分剖面图;以及
图15示出了在根据一个实施例的半导体器件的制备方法中形成互连故障防止结构的另一个步骤的部分剖面图。
具体实施方式
下面参考附图介绍实施例。
图1到11示出了在根据实施例的半导体器件的制备方法中形成多级互连结构的各步骤的部分剖面图。下面参考图1到11介绍多级互连结构的形成步骤。
如图1所示,半导体元件(未示出)等形成在半导体衬底(Si衬底)S上,低介电常数绝缘膜1(例如,SiCO:H膜)通过等离子体CVD淀积在半导体衬底S上。通过公知的镶嵌工艺,铜互连2(阻挡金属和铜互连)埋置在低介电常数绝缘膜1中。如图2所示,通过等离子体CVD,在低介电常数绝缘膜1上淀积50nm的SiCN:H膜3作为蚀刻终止膜。此时,采用有机硅烷(烷基硅烷)和NH3作为源气。如图3所示,通过等离子体CVD在SiCH:H膜3上淀积350nm的SiCO:H膜4。SiCO:H膜为所谓的低介电常数绝缘膜,它的相对介电常数由常规膜的约3.9降低到约2.9。此时,有机硅烷(烷基硅烷)和O2用作源气。
如图4所示,通过等离子体CVD在SiCO:H膜4上淀积100nm的SiO2膜5作为帽盖膜。此时,有机硅烷(烷氧基硅烷)和O2用作源气。之后,如图5所示,通过光刻构图抗蚀剂掩模6并用作蚀刻掩模,通过RIE(反应离子蚀刻)处理SiO2膜5和SiCO:H膜4,由此形成了过孔7。
如图6所示,用排放的(discharged)O2气体除去抗蚀剂掩模6。施加用于形成互连沟槽的抗蚀剂掩模8,如图7所示,并通过光刻构图,如图8所示。如图9所示,使用抗蚀剂掩模8作为掩模通过RIE形成互连沟槽9。
此后,如图10所示,用排放的O2气体除去抗蚀剂掩模8,通过RIE处理过孔7底部的SiCN:H膜3,完成了用于埋置互连的沟槽。实际上,通过溅射形成阻挡金属层和Cu籽晶层,通过电镀Cu埋置在互连沟槽9和过孔7中,通过CMP(化学机械抛光)除去SiO2膜5上的Cu,以形成铜互连10(阻挡金属和铜互连)。通过重复该工艺,形成了多级互连结构,如图11所示。
这些步骤与常规的步骤相同。在通过这些步骤形成的多级互连结构中,在随后的步骤特别是热处理的影响下,半导体器件的性能变差,或者随着时间的推移,互连最终断裂。认为是通过以上提到的三个步骤,在绝缘膜1和作为低介电常数绝缘膜的SiCO:H膜4的界面上、互连沟槽9的侧面和底面上、以及过孔7的侧面上形成了损伤层11造成了所述故障,如图12所示:
(1)通过等离子体CVD淀积5到100nm的SiO2膜的步骤(图4),
(2)用排放的O2气体除去抗蚀剂掩模6(图6)的步骤,以及
(3)用排放的O2气体除去抗蚀剂掩模8(图10)的步骤,
通过在步骤(1)到(3)中排放氧来氧化低介电常数绝缘膜的表面。由于低介电常数绝缘膜含有甲基,发生了下面的反应:
其中≡Si-CH3是含在SiCO膜中的甲基。
由于形成的≡Si-OH基作为所谓的水吸附位置吸收水(H2O),特别是在金属互连附近的那部分低介电常数绝缘膜形成吸水损伤层。特别是在随后的高温热处理步骤中,金属互连被水氧化并存在断裂。现已常规地尝试通过改进形成工艺抑制形成吸水损伤层,但是没有解决该问题。
当通过以上步骤形成图11所示的多级互连结构时,类似于常规的结构,图12所示的损伤层11形成在金属互连附近的低介电常数绝缘膜上。在该状态中,由于含在损伤层11中的水造成了互连失效。本实施例通过下面的步骤防止了互连失效。
图13到15示出了根据本发明的半导体器件制造方法中形成互连故障防止结构各步骤的部分剖视图。在图13到15中,与图1到11中相同的参考数字表示相同的部分。现在参考图13到15介绍形成互连故障防止结构的各步骤。
如图13所示,形成使用低介电常数绝缘膜具有预定数量层的多级结构,形成作为终止膜的SiCN:H膜3作为最顶层。如图14所示,形成沟槽结构或孔结构12以延伸穿过各互连层。通过在最顶部的SiCN:H膜3上构图掩模(未示出)并使用掩模通过干蚀刻形成沟槽或孔形成沟槽结构或孔结构12。形成之后,通过O2灰化除去掩模。可以在半导体器件中的任意位置形成沟槽结构或孔结构12,只要沟槽结构或孔结构12延伸穿过互连层,并具有不影响互连的形状。例如,也可以沿单个半导体器件的边缘环形地形成沟槽结构或孔结构12。
之后,使用退火装置在常压下氮气氛中在250℃下热处理(退火)多级互连结构20分钟。借助延伸穿过互连层的沟槽结构或孔结构12,该热处理有效地吸收了含在下层的膜1和膜4中的水。热处理不限于250℃,但是也可以在100℃(包含)到400℃(包含)的范围内进行。在100℃或更高,水会蒸发,400℃或更低的温度不会使互连层劣化。
热处理之后,如图15所示,使用常压CVD装置形成SiO2薄膜,以在沟槽结构或孔结构12中埋置SiO2膜13。填充之后,再次通过CMP平面化最顶层的表面。该工艺有效地除去了含在损伤层中的水。
通过进行为可靠性技术领域中一种方法的加速试验可以验证降低以上方法制备的半导体器件的故障发生率的效果。在225℃常压氮气氛中加热由常规方法制备的半导体器件和由根据本实施例的方法制备的半导体器件,使用互连电阻升高的程度作为标准测量互连的断裂故障发生频率。由根据本实施例的方法制备的半导体器件显示出即使500小时之后仅0.1%的故障率,而由常规的方法制备的半导体器件显示出了52%的故障率。该结果证明本发明的方法比常规的方法有效得多。
应该注意本实施例采用了以下结构:在每层中铜互连埋置在具有低介电常数绝缘膜和SiO2膜的双层结构的层间介质膜中,但是本发明不限于该结构。通过使用单层或三层或更多层的层间介质膜也可以得到相同的效果。
本实施例使用了SiCN:H膜作为蚀刻终止膜,但是本发明不限于该膜。通过抑制了Cu扩散的绝缘膜(例如,SiC:H膜、SiCO:H膜、SiN膜或SiN:H膜)也可以得到相同的效果。
本实施例采用了SiCO:H膜作为低介电常数绝缘膜,但是本发明不限于该膜。通过具有的相对介电常数低于SiO2膜的相对介电常数3.9的低介电常数绝缘膜也可以得到相同的效果。和热处理一样,本实施例在250℃下进行退火20分钟,但是本发明不限于该温度和时间。在100℃或更高的温度可以得到相同的效果。
本实施例通过常压CVD形成了SiO2膜作为埋置结构以埋置SiO2,但是本发明不限于该方法。通过如等离子体CVD、低压CVD、汽相淀积或涂覆的其它膜形成方法也可以获得相同的效果。气氛气体不限于氮气,可以在其它的惰性气体气氛(例如,稀释气体)或真空气氛中进行退火。
本实施例使用了SiO2绝缘体作为埋置在沟槽或孔中的材料,但是本发明不限于此。通过埋置通过溅射、CVD、镀覆等如钨或铜的金属、埋置如硅的半导体、或者埋置SiOC膜也可以得到相同的效果。
如上所述,根据本实施例,使用低介电常数绝缘膜和埋置的铜互连,在互连结构中形成单层的互连层或两层或多层的多级互连层。形成沟槽或孔以延伸穿过各互连层,对所得结构进行热处理以从形成在互连层中的损伤层中吸收水,由此除去了含在互连层的低介电常数绝缘膜中的水,以减少互连故障。而且,通过用埋置材料填充延伸穿过互连层的沟槽或孔,特别是当形成两层或多层层间介质膜时,增强了具有不同成分的层间介质膜之间界面处的粘结性。这对于在随后的步骤中,特别是切割或类似步骤中防止界面处剥离非常有效。
本发明的实施例可以提供减少互连故障的半导体器件以及制造该半导体器件的方法。
额外的优点和修改对于本领域中的技术人员来说是很容易的。因此,广义的本发明不限于这里示出和介绍的具体细节和代表性实施例。因此,可以不脱离附带的权利要求书及其等效物限定的总的本发明的概念的精神或范围进行多种修改。
Claims (20)
1.一种半导体器件的制造方法,特征在于包括:
形成至少一个互连层,具有低介电常数绝缘膜(1)和埋置在低介电常数绝缘膜(1)中的互连(2);
形成在互连层中延伸的沟槽或孔(12);
对具有沟槽或孔(12)的互连层进行热处理;以及
在沟槽或孔(12)中埋置材料(13)。
2.根据权利要求1的方法,特征在于互连层具有至少两个不同成分的绝缘膜(1,3)。
3.根据权利要求1的方法,特征在于低介电常数绝缘膜(1)含有至少Si和O。
4.根据权利要求3的方法,特征在于低介电常数绝缘膜(1)还含有至少C和H。
5.根据权利要求1的方法,特征在于互连层具有通过叠置终止膜(3)、低介电常数绝缘膜(1)以及帽盖膜(5)得到的结构。
6.根据权利要求5的方法,特征在于低介电常数绝缘膜(1)含有至少Si和O。
7.根据权利要求6的方法,特征在于低介电常数绝缘膜(1)还含有至少C和H。
8.根据权利要求7的方法,特征在于终止膜(3)含有至少Si和N。
9.根据权利要求8的方法,特征在于终止膜(3)还含有至少C和H。
10.根据权利要求7的方法,特征在于帽盖膜(5)包括SiO2膜。
11.根据权利要求1的方法,特征在于通过形成低介电常数绝缘膜(1)、在低介电常数绝缘膜(1)中形成互连沟槽以及在互连沟槽中埋置互连(2)形成了互连层。
12.根据权利要求11的方法,特征在于通过在低介电常数绝缘膜(1)上形成掩模图形、使用掩模图形作为掩模干蚀刻低介电常数绝缘膜(1)以及干蚀刻之后通过灰化除去掩模图形形成互连沟槽。
13.根据权利要求1的方法,特征在于在不低于100℃和不高于400℃的温度下进行热处理。
14.根据权利要求1的方法,特征在于在惰性气体气氛或真空气氛中进行热处理。
15.根据权利要求1的方法,特征在于埋置材料(13)包括绝缘体。
16.根据权利要求15的方法,特征在于绝缘体包括SiO2。
17.根据权利要求1的方法,特征在于埋置材料(13)包括金属。
18.根据权利要求1的方法,特征在于埋置材料(13)包括半导体。
19.根据权利要求1的方法,特征在于沟槽(12)沿半导体器件的边缘形成。
20.根据权利要求1的方法,特征在于形成沟槽或孔(12)延伸穿过多个互连层,每层具有低介电常数绝缘膜(1)和互连(2)。
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