CN1988144A - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN1988144A
CN1988144A CNA2006101413863A CN200610141386A CN1988144A CN 1988144 A CN1988144 A CN 1988144A CN A2006101413863 A CNA2006101413863 A CN A2006101413863A CN 200610141386 A CN200610141386 A CN 200610141386A CN 1988144 A CN1988144 A CN 1988144A
Authority
CN
China
Prior art keywords
conductive layer
wiring
semiconductor device
electrode pad
passivating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101413863A
Other languages
English (en)
Inventor
太田行俊
永井纪行
滨谷毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1988144A publication Critical patent/CN1988144A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明揭示一种半导体器件，在这种具有用镶嵌法形成的布线的多层布线结构的半导体器件中，至少一部分电极焊盘将具有处理与外部的电连接用的区域的第1导电层(5)，形成在多层布线结构中半导体衬底(1)上必不可少的钝化膜(4)上。

Description

半导体器件
技术领域
本发明涉及半导体衬底上具有多个层间绝缘膜和电极焊盘的多层结构半导体器件。
发明背景
近年来，随着数字化社会的进步，半导体器件的高功能化、多功能化的要求越来越强烈，响应这种要求用的半导体器件电极焊盘数量不断增加。另一方面，为了适应电子设备的小型化和降低成本，需要半导体芯片进一步小型化。为了解决这些要求，虽然有布线多层化且进一步微细化的方法，但是有效利用电极焊盘的下层区的方法是有成效的。
这样有效利用电极焊盘下层区的方法中，作为在例如电子电路形成区利用电极焊盘下层区的例子，有在电极焊盘的下层形成半导体元件的面积焊盘技术。
导入这种面积焊盘技术的情况下，重要的是防止对半导体器件的电检查时由探头等冲击电极焊盘而产生的电极焊盘断裂、以及抑制导入面积焊盘技术所需的制造工序数的增加。
前者重要是因为发生电极焊盘下层断裂时，由于产生电极焊盘下层的半导体元件破坏和电极焊盘与下层布线之间漏电，有可能使作为半导体器件的功能目的完不成；后者的重要是因为制造工序数的增加关系到成本提高。
这里，用附图说明防止由对半导体器件的电检查时的探头、WLBI(WaferLevel Burn-In：晶圆级老化)冲击电极焊盘而发生电极焊盘下层断裂并且抑制导入面积焊盘所需的工序数的增加的面积焊盘技术(例如参考日本国专利公开公报2004-14609号)。
图5是示出作为已有技术公开的半导体器件的电极焊盘结构的剖视图。图5中，1是半导体衬底，2、3是绝缘膜，4是钝化膜，5是包含与电极焊盘的外部的连接区的导电层(第1导电层)，6是半导体元件。绝缘膜2上具有与半导体元件6连接用的通路22，绝缘膜3则具有布线31a、31b、31c、31d和通路32。
这种半导体器件如图5所示，布线31a与31b、布线31c与31d和布线31c与31d分别在绝缘膜3的部分33a、部分33b和部分33c分开，因而布线31a、31b、31c、31d中，除以通路32连接第1导电层5的布线31d以外，可用作分别与第1导电层5绝缘的布线。
此外，对这种焊盘结构的第1导电层5作电检查时，即使探头、WLBI等施加冲击的情况下，呈现在绝缘膜3的33a、33b、33c的部分为支柱33a、33b、33c，支撑成抵挡冲击，从而防止绝缘层3和下层的绝缘膜2发生断裂。
这种焊盘结构能用已有半导体器件制造工序中一般使用的材料、条件形成，而且不形成聚酰亚胺膜等新的层作为绝缘膜，所以不产生制造工序增加等造成的成本提高。
然而，上述已有半导体器件的焊盘结构最上层的布线之间的支柱部的绝缘膜与其布线上的绝缘膜合为一体，对以溅射法形成最上层布线的铝布线的情况、将上层布线用作与第1导电层绝缘的布线等情况而言，可形成这种一体结构，没有问题，但仅用铜布线等镶嵌(damassin)法形成的布线的情况下，以绝缘膜上形成槽并将铜制布线材料埋入该槽的方式形成，因而不能合为一体地形成布线之间的绝缘膜和该布线上的绝缘膜。
因此，与作为已有半导体器件说明的用溅射法形成铝布线的焊盘结构相同，需要在最上层布线与第1导电层之间形成绝缘膜，以便将最上层的布线用作与第1导电层绝缘的布线，但重新多形成1层绝缘膜，则制造时的工序数增加，因而存在关系到成本提高的问题。
发明内容
本发明解决上述已有问题，其目的在于提供一种能在以镶嵌法形成叠层衬底上的电极焊盘的情况下既抑制制造时关系到成本提高的工序数增加又有效利用电极焊盘的下层区的半导体器件。
为了解决上述课题，本发明的半导体器件，其多层布线结构在半导体衬底上具有多个层间绝缘膜、用镶嵌法形成的布线、以及与外部电连接用的电极焊盘，其中，所述电极焊盘的至少一部分在所述半导体衬底上的钝化膜上形成具有处理与所述外部的电连接用的区域的第1导电层，并且在紧接于所述钝化膜的下方形成具有多条所述布线的第2导电层，所述第2导电层的至少一部分以非电连接状态在所述半导体衬底的垂直方向与所述第1导电层重叠。
根据第1发明，将半导体器件做成具有用镶嵌法形成的布线的多层布线结构时，该多层布线结构中在半导体衬底1上必不可少的钝化膜上形成电极焊盘的第1导电层，从而能使第1导电层和第2导电层的布线为非分别直接电连接的状态，而不使制造时的工序数增加。
因此，能自由使用第2导电层区，可有效利用电极焊盘的下层区。
根据第2发明，将半导体器件做成具有用镶嵌法形成的布线的多层布线结构时，第2导电层中在垂直方向上与第1导电层的检查区重叠的部分配置布线，从而能使第1导电层和垂直方向上与其检查区以外的部分重叠的第2导电层的布线为非分别直接电连接的状态。
因此，能自由使用第2导电层区中在垂直方向上与第1导电层的检查区以外重叠的区域，可有效利用电极焊盘的下层区，同时还能抑制钝化膜发生断裂。
根据第3发明，将半导体器件做成具有用镶嵌法形成的布线的多层布线结构时，第2导电层中与所述第1导电层的检查区在垂直方向重叠的布线直接与第1导电层电连接，因而即使探头或WLBI作检查的工序中钝化膜发生断裂并且第1导电层和第2导电层的布线之间产生泄漏的情况下，作为半导体器件的电路也能起作用，工作上没有问题。
因此，能自由使用第2导电层区中在垂直方向上与第1导电层的检查区以外重叠的区域，可有效利用电极焊盘的下层区，同时还能在钝化膜发生断裂的情况下，照常执行探头、WLBI检查。
根据第4发明，将半导体器件做成具有用镶嵌法形成的布线的多层布线结构时，钝化膜中在垂直方向上与第1导电层的检查区重叠的部分形成开口，所以能对受探头或WLBI检查工序冲击的部位消除钝化膜。
因此，能自由使用第2导电层区中在垂直方向上与第1导电层的检查区以外重叠的区域，可有效利用电极焊盘的下层区，而且不发生钝化膜断裂，能防止发生断裂引起的电极焊盘剥离等钝化膜断裂造成的弊病。
附图说明
图1A是示出本发明实施方式1的半导体器件的结构的俯视图。
图1B是示出本发明实施方式1的半导体器件的结构的剖视图。
图2A是示出本发明实施方式2的半导体器件的结构的俯视图。
图2B是示出本发明实施方式2的半导体器件的结构的剖视图。
图3A是示出本发明实施方式3的半导体器件的结构的俯视图。
图3B是示出本发明实施方式3的半导体器件的结构的剖视图。
图4A是示出本发明实施方式4的半导体器件的结构的俯视图。
图4B是示出本发明实施方式4的半导体器件的结构的剖视图。
图5是示出已有半导体器件的电极焊盘结构的剖视图。
具体实施方式
下面，参照附图具体说明表示本发明实施方式的半导体器件。
本发明实施方式，均以绝缘膜为2层且铜布线的双镶嵌工艺的半导体器件为例进行说明。本发明实施方式的半导体器件的制造工序和制造条件基本上与通常的半导体器件的制造工序和制造条件相同，因而省略其详细说明。
实施方式1
下面，用图1A、图1B对本发明实施方式1的半导体器件说明其结构。
图1A是示出实施方式1的半导体器件的结构的俯视图。图1B是示出表示本实施方式1的半导体器件的结构的图1A的沿A-A’的截面结构的概略剖视图。
如图1A、1B所示，在半导体衬底1上形成用例如电介质氧化物形成的绝缘膜2和3、以及用例如氮化硅形成的钝化膜4。半导体器件的电极焊盘的第1导电层5的下层的绝缘膜3上配置第2导电层的布线31a、31b、31c、31d，绝缘膜2上配置布线21a、21b、21c、21d，并且半导体衬底1上配置半导体元件6。
将第1导电层5形成在钝化膜4上，并且在钝化膜4的开口部45与第2导电层的布线31b相连。
在绝缘膜2、3和该绝缘膜2、3内的通路与布线之间形成例如由TaN组成的阻挡膜，在钝化膜4与第1导电层5之间形成例如由TiN组成的阻挡膜。
接着，说明本实施方式1的半导体器件的制造方法。
本实施方式1的半导体器件制造方法与通常的半导体器件形成方法相同，例如布线和通路孔为铜(Cu)的情况下，在形成半导体元件6的半导体衬底1上，利用CVD(Chemical Vapor Deposition：化学汽相生长)法首先形成电介质氧化物的绝缘膜2。
其次，对绝缘膜2利用光刻制版和蚀刻形成通路孔和布线槽。接着，利用例如溅射法形成阻挡金属的TaN膜和Cu种膜。接着，利用电解电镀使Cu膜淀积在Cu种膜上，从而形成通路和布线21a、21b、21c、21d。
接着，利用例如CMP(Chemical Mechanical Planarization：化学机械平面化)法将Cu膜去除到绝缘膜2的上表面露出。重复上述步骤，以形成绝缘膜3以及绝缘膜3内的通路和第2导电层的布线31a、31b、31c、31d。
接着，利用例如CVD法形成由氮化硅组成的钝化膜4，并对该钝化膜4利用光刻制版和蚀刻形成开口42。接着，利用溅射法、光刻制版和蚀刻形成由Ti和TiN组成的阻挡膜以及由例如Al组成的第1导电层5。
综上所述，本实施方式1中，在具有以镶嵌法形成的布线的多层布线结构的半导体器件内，至少图中所示那样的一部分电极焊盘在钝化膜4上形成具有处理与外部的电连接用的区域的第1导电层5。
钝化膜4是用于保护半导体元件免受机械应力和杂质侵入的膜，尤其在以镶嵌法形成的Cu布线等容易氧化的布线为最上层布线的情况下，是必不可少的。通过在该必不可少的钝化膜4上形成电极焊盘的第1导电层5，能使第1导电层5和第2导电层的布线31a、31b、31c、31d为非分别直接电连接的状态，而不使制造工序数增加，从而能有效利用电极焊盘的下层区域。
实施方式2
下面，用图2A、图2B对本发明实施方式2的半导体器件说明其结构。图2A是示出实施方式2的半导体器件的结构的俯视图。图2B是示出表示本实施方式2的半导体器件的结构的图2A的沿B-B’的截面结构的概略剖视图。
这里，仅说明与实施方式1的不同点。
图2A示出探头或WLBI检查工序中探头或WLBI的凸端进行接触而冲击的检查区51。探头或WLBI的凸端在电极焊盘的第1导电层5内接触的部位即使是晶圆内相同处的芯片的相同部位的电极焊盘，但由于测试装置的探头或WLBI装置的凸端或者晶圆调整偏移，也不每次相同，具有几微米至几十微米程度的偏差。
因此，检查区51不仅是冲击各电极焊盘的第1导电层5的实际部位，而且是包含偏差的可能冲击的整个部位。在检查区51的下层的绝缘膜3内形成第2导电层的布线31e，作为虚设布线。
图2A、图2B将第2导电层的布线31e当作规模与检查区51相同的虚设布线示出，但如果这样以包含整个检查区51的下层的方式形成虚设布线，则可大于检查区51，也可将与检查区51重叠的区域以外的部分用作普通布线。形成方法与实施方式1的半导体器件制造方法相同。
综上所述，本实施方式2在绝缘膜3内的第2导电层中与第1导电层的检查区在垂直方向上重叠的部分，形成第2导电层分布线31e，作为虚设布线。
另一方面，半导体器件的包含组装工序的制造序中，冲击电极焊盘的主要工序有基于探头的检查工序、基于WLBI的检查工序、丝焊工序，其中丝焊工序比基于探头的检查工序、基于WLBI的检查工序的冲击弱。
这在实验中得到验证。本实施方式1的焊盘结构中，焊珠宽80微米左右的丝焊不使处在第1导电层5下方的钝化膜4发生断裂，但过驱动量60微米左右的常规条件的悬臂式探头检查、或基于每一凸端10g f的WLBI检查，使钝化膜4发生断裂。
此外，绝缘膜的受冲击的部分的下层有布线时，由于布线比绝缘膜软，容易产生形变，可由此形变吸收对布线上层的绝缘膜的冲击。但是，即使绝缘膜的下层有布线，绝缘膜的受冲击的部分的下层同时存在软的布线部分和硬的绝缘膜时，仅软的布线部分产生形变，在下层的绝缘膜与布线的边界面发生应力集中，所以反而上层的绝缘膜容易发生断裂。
因此，通过在绝缘膜3内的第2导电层中与第1导电层5的检查区51在垂直方向上重叠的部分将布线31e形成为虚设布线，能抑制钝化膜4发生断裂，可自由使用与检查区51以外的第1导电层5在垂直方向重叠的部分的第2导电层的布线31a、31b，能有效利用绝缘膜3能的第2导电层上形成的下层布线。
实施方式3
下面，用图3A、图3B对本发明实施方式3的半导体器件说明其结构。
图3A是示出实施方式3的半导体器件的结构的俯视图。图3B是示出表示本实施方式3的半导体器件的结构的图3A的沿C-C’的截面结构的概略剖视图。
这里，仅说明与实施方式2的不同点。
如图3A所示，绝缘膜3内处在第1导电层5的检查区51的下层的第2导电层的布线31e，通过钝化膜4的开口部42与第1导电层5电连接。再者，形成方法与实施方式1的半导体器件制造方法相同。
综上所述，根据本实施方式3，则绝缘层3内的第2导电层中与第1导电层5的检查区51在垂直方向上重叠的第2导电层的布线31e直接与第1导电层5电连接，因此即使探头或WLBI检查工序中钝化膜4发生断裂，并且第1导电层5与第2导电层的布线31e之间产生泄漏的情况下，由于原来就已电连接，能不发生作为半导体器件的电路起作用的工作上的问题。
因此，即使钝化膜4发生断裂的条件下，也能进行探头或WLBI检查。
实施方式4
下面，用图4A、图4B对本发明实施方式4的半导体器件说明其结构。
图4A是示出实施方式4的半导体器件的结构的俯视图。图4B是示出表示本实施方式4的半导体器件的结构的图4A的沿D-D’的截面结构的概略剖视图。
这里，仅说明与实施方式3的不同点。
如图4A所示，在第1导电层5的检查区51的下层的钝化膜4形成规模与检查区51相同的开口42，并通过开口部42将绝缘层3内的第2导电层的布线31e与第1导电层5连接。再者，形成方法与实施方式1的半导体器件制造方法相同。
综上所述，根据本实施方式4，钝化膜中与第1导电层的检查区51在垂直方向上重叠的部分形成开口部42，所以能使检查工序中因探头或WFBI而受到机械冲击的部位不存在钝化膜。
因此，钝化膜4的开口部42的部分不发生钝化膜4的断裂，从而不产生断裂引起的电极焊盘剥离等的起因于钝化膜4的断裂所造成的机械和电气的弊病。

Claims (4)

1、一种半导体器件，其特征在于，
其多层布线结构在半导体衬底上具有多个层间绝缘膜、用镶嵌法形成的布线、以及与外部电连接用的电极焊盘，所述电极焊盘的至少一部分
在所述半导体衬底上的钝化膜上形成具有与所述外部的电连接用的区域的第1导电层，并且
在紧接于所述钝化膜的下方形成具有多条所述布线的第2导电层，
所述第2导电层的所述布线的至少一部分
以非电连接状态在所述半导体衬底的垂直方向与所述第1导电层重叠。
2、如权利要求1中所述的半导体器件，其特征在于，
与所述第1导电层在所述半导体衬底的垂直方向重叠的所述第2导电层的所述布线，至少与所述第1导电层的检查区在垂直方向重叠。
3、如权利要求2中所述的半导体器件，其特征在于，
具有与所述第1导电层的检查区在垂直方向重叠的部分的所述第2导电层的所述布线，直接与所述第1导电层电连接。
4、如权利要求3中所述的半导体器件，其特征在于，
所述钝化膜中，在垂直方向上与所述第1导电层的检查区重叠的部分形成开口，并且
通过所述钝化膜的开口，进行所述第1导电层与所述第2导电层的布线的所述电连接。
CNA2006101413863A 2005-12-21 2006-09-26 半导体器件 Pending CN1988144A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005367293 2005-12-21
JP2005367293A JP4663510B2 (ja) 2005-12-21 2005-12-21 半導体装置

Publications (1)

Publication Number Publication Date
CN1988144A true CN1988144A (zh) 2007-06-27

Family

ID=38172510

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101413863A Pending CN1988144A (zh) 2005-12-21 2006-09-26 半导体器件

Country Status (3)

Country Link
US (1) US20070138638A1 (zh)
JP (1) JP4663510B2 (zh)
CN (1) CN1988144A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105006462A (zh) * 2009-06-18 2015-10-28 罗姆股份有限公司 半导体装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119506A (ja) * 2009-12-04 2011-06-16 Panasonic Corp 半導体装置
JP6524730B2 (ja) * 2015-03-17 2019-06-05 セイコーエプソン株式会社 半導体装置
KR102500170B1 (ko) 2018-01-03 2023-02-16 삼성전자주식회사 금속 범프를 갖는 반도체 소자 및 그 제조방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2004A (en) * 1841-03-12 Improvement in the manner of constructing and propelling steam-vessels
JP3948822B2 (ja) * 1998-04-21 2007-07-25 ローム株式会社 半導体集積回路
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
JP2005268611A (ja) * 2004-03-19 2005-09-29 Renesas Technology Corp 半導体装置の製造方法
US7026547B1 (en) * 2005-01-21 2006-04-11 Infineon Technologies Ag Semiconductor device and a method for fabricating a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105006462A (zh) * 2009-06-18 2015-10-28 罗姆股份有限公司 半导体装置
US9780069B2 (en) 2009-06-18 2017-10-03 Rohm Co., Ltd. Semiconductor device
US10163850B2 (en) 2009-06-18 2018-12-25 Rohm Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
JP4663510B2 (ja) 2011-04-06
US20070138638A1 (en) 2007-06-21
JP2007173419A (ja) 2007-07-05

Similar Documents

Publication Publication Date Title
US7459792B2 (en) Via layout with via groups placed in interlocked arrangement
US7323784B2 (en) Top via pattern for bond pad structure
US7148575B2 (en) Semiconductor device having bonding pad above low-k dielectric film
US7241636B2 (en) Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
US5700735A (en) Method of forming bond pad structure for the via plug process
US7397127B2 (en) Bonding and probing pad structures
KR101127893B1 (ko) 반도체장치
US8004086B2 (en) Semiconductor device
JP2004235416A (ja) 半導体装置、および半導体装置の製造方法
US8779591B2 (en) Bump pad structure
US20030218259A1 (en) Bond pad support structure for a semiconductor device
JPWO2005096364A1 (ja) 半導体装置及びその製造方法
US8044482B2 (en) Semiconductor device
CN1988144A (zh) 半导体器件
JP2001358169A (ja) 半導体装置
KR19990052264A (ko) 다층 패드를 구비한 반도체 소자 및 그 제조방법
US6955981B2 (en) Pad structure to prompt excellent bondability for low-k intermetal dielectric layers
KR101062820B1 (ko) 반도체 장치의 퓨즈 및 그 제조방법
US11217496B2 (en) Test pad with crack stop protection
JP2007242644A (ja) 半導体装置及びその製造方法
JPH10154708A (ja) 半導体デバイスのパッド構造
KR19990055279A (ko) 비아 홀을 이용한 다층 배선층간의 접속구조
KR20020060452A (ko) 반도체 집적 회로 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20070627