CN1152413C - 制造双镶嵌结构的方法和结构 - Google Patents

制造双镶嵌结构的方法和结构 Download PDF

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CN1152413C
CN1152413C CNB981156290A CN98115629A CN1152413C CN 1152413 C CN1152413 C CN 1152413C CN B981156290 A CNB981156290 A CN B981156290A CN 98115629 A CN98115629 A CN 98115629A CN 1152413 C CN1152413 C CN 1152413C
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马丁·古奇
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德克·托本
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Abstract

一种制作双镶嵌结构的方法，包括：在包括至少一个导电区域的半导体基底上形成一牺牲材料层；对该牺牲材料层构图，以便在该导电区域上面形成至少一个柱；在半导体基底上面，环绕该至少一个柱形成一介电层；以及在金属间介电层中形成一导线开口，该至少一个柱的部分暴露在开口范围内。介电层包括一第一介电层和一第二介电层，第一介电层的厚度稍微小于或等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上。本发明利用牺牲性柱并在导线开口和通孔之间的界面处提供了一种改进了的界限明确的边缘。还涉及用来形成双镶嵌结构的结构。

Description

制造双镶嵌结构的方法和结构
技术领域
本发明涉及一种半导体的制造技术，更具体地说，涉及一种制造双镶嵌结构(dual damascene)的方法和用于形成双镶嵌结构的结构。
背景技术
通常，半导体器件包括构成集成电路的许多电路，集成电路可用于计算机和电子设备，并可包括能在单个硅晶体半导体器件即芯片上构造出的成百万个晶体管和其它电路元件。为了使器件工作，通常将信号路径的复杂网络构成一定路线，以便连接分布在器件表面上的电路元件。随着集成电路的复杂性增加，这些信号跨越器件的有效路径选择就变得更难。因此，称作双镶嵌结构的多级或多层设计由于它们能增加器件的密度，从而为人们所需，所以，允许稠密组装的半导体器件的堆叠互连层。
在制造具有双镶嵌结构的集成电路时，通常将使半导体器件的象氧化硅那样的绝缘或介电材料构图，使之具有，例如，几千个开口，以便形成导线开口和通孔。然后可用导电金属层，例如铝，填满导线开口和通孔，以便使集成电路的有源和/或无源元件互连。也可将双镶嵌结构用来在多层基底的绝缘层，例如，聚酰亚胺中形成金属，例如，铜的多层导线，可把晶体管器件安装在多层基底上。
已公知一些制作双镶嵌结构的方法。例如，可参看美国专利第5,422,309；5,529,953；5,602,423；以及5,614,765号。通常，标准的双镶嵌结构可以这样制作：首先在绝缘层上涂上抗反射涂层(ARC，antireflective coating)和光致抗蚀剂层。然后通过带有通孔图案的第一掩模使光致抗蚀剂曝光，可通过绝缘层各向异性地蚀刻图案，以便露出下面的导电层。在蚀刻通孔之后，除去剩余的抗反射涂层和光致抗蚀剂。然后沉积新的抗反射涂层和光致抗蚀剂层。通过带有导线开口图案的第二掩模使光致抗蚀剂层曝光。一般将使第二图案对准第一掩模图案，以便用导线开口环绕通孔。除去将要形成导线开口的光致抗蚀剂部分，露出通孔和绝缘层。然后把露出的绝缘层蚀刻到等于导线高度的所需深度。当蚀刻完成时，可把通孔和导线开口两者都填满导电金属层。
第二次沉积抗反射涂层和光致抗蚀剂层用抗反射涂层填满通孔，使聚合物在后来形成导线通路的蚀刻过程中在通路内积累。由于基本图线尺寸(或最小图形尺寸，groundrule)变得越来越小，这种聚合物积累导致在通孔和导线开口的界面处形成SiO2篱笆(fence)。篱笆的出现使金属流入通路产生中断，使得在那里形成空隙。这样的空隙导致增加通孔电阻，在某些情况下，还导致通孔故障。
发明内容
从上述讨论中看出，人们需要提供一种在通孔-导线开口处不致形成篱笆的双镶嵌结构。
本发明提供一种制作双镶嵌结构的方法，包括：
a)在包括至少一个导电区域的半导体基底上形成一牺牲材料层；
b)对该牺牲材料层构图，以便在该导电区域上面形成至少一个柱；
c)在半导体基底上面，环绕该至少一个柱形成一介电层，该介电层包括一第一介电层和一第二介电层，第一介电层的厚度稍微小于或大约等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上；以及
d)通过蚀刻第二介电层，在介电层中形成一导线开口，其中第一介电层作为蚀刻中止层，该至少一个柱的部分暴露在开口范围内。
本发明还提供一种制造双镶嵌结构的方法，它包括：
a)在半导体基底的至少一部分上面形成牺牲材料层，该牺牲材料层被构图成至少一个柱；
b)在半导体基底的至少一部分上面形成金属间介电层，以便围住并覆盖该至少一个柱，该金属间介电层包括一第一介电层和一第二介电层，第一介电层的厚度稍微小于或大约等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上，该金属间介电层具有平的表面；
c)蚀刻第二介电层，以便形成至少一个导线开口，其中第一介电层作为蚀刻中止层；以及
d)从金属间介电层上除去该至少一个柱，以便形成通孔。
本发明还提供一种用来形成双镶嵌结构的结构，包括：
一个基底；
一个在所述基底上形成的具有第一蚀刻速率的牺牲材料的柱；
一个具有第二蚀刻速率并环绕柱的金属间介电层，第一蚀刻速率大于第二蚀刻速率，该金属间介电层包括一第一介电层和一第二介电层，第一介电层的厚度稍微小于或等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上，并且第二介电层的蚀刻速率大于第一介电层的蚀刻速率，从而第一介电层作为蚀刻第二介电层的蚀刻中止层；及
一个在金属间介电层中形成的露出柱的部分的导线开口。
本发明提出一种制造双镶嵌结构的新方法，它包括以下步骤：在半导体基底上形成牺牲材料层；在半导体基底上形成金属间的介电层；蚀刻金属间介电层中的导线开口并除去牺牲材料层。
在一个可以采用的具体实施例中，该方法包括以下步骤：
a)在半导体基底的至少一部分上面形成牺牲材料层；
b)使牺牲材料层构图成至少一个柱；
c)在半导体基底的至少一部分上面形成金属间的介电层；
d)在金属间的介电层中蚀刻至少一个导线开口；
e)从金属间的介电层中除去至少一个柱；以及
f)用导电材料取代金属间的介电层中的至少一个柱。
附图说明
下面参照附图描述制作双镶嵌结构的方法的优选实施例，附图中：
图1是表示在半导体基底上形成的牺牲材料层的截面图；
图2是表示在半导体基底上被构成柱的牺牲材料层的截面图；
图3是表示在半导体基底的表面上以及柱的上表面上形成的金属间介电层的截面图；
图4是表示蚀刻的导线开口的截面图；
图5是表示除去了柱的导线开口的截面图；以及
图6是表示填满导电金属层的导线开口和通孔的截面图。
具体实施方式
本发明涉及集成电路的制造。这种集成电路包括例如，随机存取存储器(RAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、静态RAM(SRAM)以及只读存储器(ROM)等存储器电路。其它集成电路包括象可编程逻辑阵列(PLA)、专用集成电路(ASIC)那样的逻辑器件或任何电路器件。本发明提供了在导线开口和通孔的界面处实质上没有互连不良的边缘的双镶嵌结构。一般地说，在象硅晶片那样的半导体基底上并列制造许多集成电路。在处理之后，晶片被切割，以便把集成电路分成很多单个芯片。然后把芯片封装成最终产品，以便用于，例如，象计算机系统、蜂窝电话、个人数字助理(PDA，personal digital assistants)等消费产品以及其它产品。
在一个实施例中，本发明包括和在其中形成双镶嵌结构的介电材料一起使用的牺牲材料。在其中形成双镶嵌结构的层在此处称为金属间介电层(IMD，intermetal dielectric)。通过选择与金属间介电层相比具有较高的湿法或干法蚀刻速率的牺牲材料可避免界限不良的边缘。
参看图1，提供了半导体基底20的一部分。基底，例如，包括硅晶片。其它基底，如砷化镓、绝缘体外延硅(SOI)、锗、或其它半导体材料也是可用的。基底20包括在其上面形成的集成电路(未示出)。此集成电路可能处于制造工艺的任一阶段。在基底上面包括象金属化层之类的底层的导电区域22。另一方面，导电区域可以是重掺杂的多晶硅层或象晶体管的源极或漏极区域之类的有源器件的任一部分。在一个实施例中，导电区域是DRAM芯片的位线。导电区域用，例如，介电材料隔离。一般地把上表面30做平面化处理，以提供平的上表面。上述集成电路可包括附加的器件、电路、以及其它互连层。
如图所示，在半导体基底20上表面30之上形成牺牲材料层15。用于牺牲材料层15的合适材料包括本领域的技术人员所熟知的任何常规材料。在一个实施例中，用来形成层15的材料包括可流动的氧化物、化学气相沉积(CVD)氧化物、硼硅玻璃(BSG)、氮化硅(SiN)、象聚对二甲基苯(parylene)、聚酰亚胺(例如光敏性聚酰亚胺)和PBO之类的不含硅的材料以及其它类似材料。非常有利的是，在这里所描述的本方法中使用的牺牲材料比下面描述的在半导体基底20上面后来形成的金属间介电层具有更大的湿法和/或干法蚀刻速率。
为了实现适宜的厚度均匀性，通常将把牺牲材料层15做基本平面化的处理。如果需要时，可使用象，例如，CMP(化学机械抛光)这样的单独的平面化步骤。一般说来，在半导体基底20上形成的牺牲材料层15的厚度将大概至少等于或大于根据在这里描述的方法形成的通孔的预期高度。牺牲材料层15的厚度可从大约1,000埃到大约10,000埃，优选是从大约1,000埃到大约8,000埃，更优选是从大约3,000埃到大6,000埃。当然，厚度可依据设计参数而变化。
参看图2，在将要形成通孔或开口的地方使牺牲层形成至少一个柱12。在上述基底的作为例子的部分形成三个柱。但是，本领域的技术人员将会理解，在制造集成电路时，可形成许多柱，使之与下面的导电区域接触。使牺牲层构成图形包括，例如，沉积抗反射涂层和光致抗蚀剂层，并在除了将要形成柱的区域之外用曝光源有选择地使光致抗蚀剂曝光。使光致抗蚀剂层显影，除去曝光的部分。然后通过，例如，反应离子蚀刻(RIE)各向异性地蚀刻基底。除去来自光致抗蚀剂层未保护的牺牲层的部分，留下与导电区域22接触的通路位置相对应的柱。虽然描述了正性光致抗蚀剂，但是也可以利用负性光致抗蚀剂。
一般说来，导电层和柱的距离通常将根据给定导体(如下所述将取代每个柱12的导电材料)的载流要求而变化，从而可避免可靠性问题，例如，电迁移。但是，在预期有小电流的场合，将把导体的尺寸和间隔限制在对一定的半导体器件和/或半导体生产过程所特定的最小宽度。每个柱12之间的宽度大概将是从大约0.15微米(μm)到大约1.0微米，优选从大约0.15μm到大约0.35μm，更优选是从大约0.15μm到大约0.25μm。
在形成至少一个柱12之后，在半导体基底20的表面和柱12的上表面上形成金属间介电层5(参看图3)。在此处描述的方法中所使用的金属间介电层材料可包括本领域的技术人员所知的任何适当的介电材料。在一个实施例中，金属间介电层材料包括A418SOG(A418旋涂玻璃)、HSG-R7SOG(HSG-R7旋涂玻璃)、有机掺杂的CVD氧化物、转换的CVD氧化物、含硅的未掺杂的硅酸盐玻璃、以及象环苯丁烯(BCB)之类的有机材料或其它类似材料。
通常可把金属间介电层5作为大体上平面化的层形成到半导体基底20的表面和柱12的上表面上。可直接通过成形过程，例如，在旋涂成膜的情况下，或者可在形成金属间介电层之后通过应用象化学机械抛光(CMP)那样的平面化处理技术，来实现大体上平面化的层。金属间介电层的厚度足以适应柱和上覆的导线。例如，金属间介电层具有比柱的高度大h的厚度，此处h大约等于导线的高度。当然，h取决于设计参数。一般说来，金属间介电层5的厚度将从大约2,000埃到大约20,000埃，优选从大约3,000埃到大约12,000埃，更优选是从大约4,000埃到大约9,000埃。形成金属间介电层5的技术是本领域的技术人员熟知的。
另一种情况是，金属间介电层稍微小于或大约等于柱的厚度。在平面化之后，在其上面形成第二金属间介电层。第二金属间介电层的厚度一般大约等于导线的高度。第二金属间介电层包括相对于第一金属间介电层的材料能被选择性地蚀刻的材料。通过提供双金属间介电层，第一金属间介电层起到形成上覆导线的蚀刻的蚀刻中止层的作用。
参看图4，使金属间介电层构图，以便产生导线开口9。利用常规的光刻和腐蚀技术实现导线开口的构图。这样的技术包括，例如，沉积抗反射涂层和光致抗蚀剂层，并接着从曝光源用象深紫外线(DUV)或超紫外线(EUV)那样的照射有选择地使光致抗蚀剂曝光。其它波长的照射也是可以采用的。然后在显影过程中除去光致抗蚀剂的曝光区域，以便露出与导线开口9对应的金属间介电层表面。进行反应离子蚀刻，以便产生开口9。反应离子蚀刻或者在确定的时间停止，以便蚀刻到能到达柱顶端的足够深度，或者在利用双金属间介电层时，用蚀刻中止技术停止。
                       表I
牺牲材料 金属层间介电层 蚀刻剂
可流动氧化物(FOx) A418SOG(旋涂玻璃) BHF
可流动氧化物 HSG-R7SOG BHF
可流动氧化物 有机掺杂CVD氧化物 BHF
可流动氧化物 CVD氧化物 BHF
CVD氧化物 A418SOG
CVD氧化物 HSG-R7SOG BHF
BSG A418SOG BHF
BSG HSG-R7SOG
BSG 有机掺杂CVD氧化物 BHF
BSG 转变的CVD氧化物 BHF
SiN CVD氧化物 CDE
有机材料，不含硅(聚对 CVD氧化物 氧气
二甲基苯、PBO)
有机材料，不含硅(聚对二甲基苯、光敏聚酰亚胺、PBO) 含硅有机材料(BCB) 氧气
其次，通过湿法或干法蚀刻过程从导线开口9的范围内有选择地除去每个柱12，以便产生如图5所示的通孔11。根据本发明，柱相对于金属间介电层有选择性地被蚀刻。柱和金属间介电层之间的蚀刻选择性使得能够除去柱而不明显除去金属间介电层。在一个实施例中，在柱和金属间介电层之间的蚀刻选择性比是大约≥8∶1，优选是大约≥12∶1，更优选是≥20∶1。产生通孔11的参数(例如，蚀刻剂的类型、蚀刻剂的浓度、时间、温度等等)本领域的技术人员容易选择。蚀刻剂的选择取决于许多因素，包括柱的成分。适用的蚀刻剂包括BHF、CDE以及氧。表I列举了可用来除去柱的蚀刻剂的材料和类型的例示性组合。
在形成通孔11以后，把导电材料25沉积在里面并填满通孔11和导线开口9，如图6所示。可用任何已知的或常规的工艺过程形成导电材料25，例如，通过各种有选择的化学气相沉积(CVD)。这里可利用任何通用的导电材料。形成导电材料25的适用材料包括但不局限于Ti、TiN、TiW、W、Al、Cu、Pd及其它类似材料。优选的材料包括W和Al。
尽管已经参照上述带有一定程度特殊性的说明性实施例描述了本发明，对于本领域的技术人员来说，在阅读上述说明之后，其中可能的改变和变化将显而易见。因而应该理解，在不脱离其精神和范围的情况下，可用与在此处具体描述的不同的方式实现本发明。

Claims (19)

1.一种制作双镶嵌结构的方法，包括：
a)在包括至少一个导电区域的半导体基底上形成一牺牲材料层；
b)对该牺牲材料层构图，以便在该导电区域上面形成至少一个柱；
c)在半导体基底上面，环绕该至少一个柱形成一介电层，该介电层包括一第一介电层和一第二介电层，第一介电层的厚度小于或等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上；以及
d)通过蚀刻第二介电层，在介电层中形成一导线开口，其中第一介电层作为蚀刻中止层，该至少一个柱的部分暴露在开口范围内。
2.根据权利要求1所述的方法，其中，牺牲材料层具有比介电层高的蚀刻速率。
3.根据权利要求1所述的方法，其中，牺牲材料层用从包括可流动氧化物、CVD氧化物、BSG、SiN、聚对二甲基苯、聚酰亚胺及PBO的一组中所选出的材料制成。
4.根据权利要求1所述的方法，其中，介电层用从包括A418SOG、HSG-R7、有机掺杂的CVD氧化物、转换的CVD氧化物、含硅的未掺杂的硅酸盐玻璃、以及有机材料的一组中所选出的材料制成。
5.根据权利要求1所述的方法，进一步包括在形成导线开口之前使介电层平面化的步骤。
6.根据权利要求1所述的方法，进一步包括以下步骤：
e)从介电层上除去该至少一个柱，以便提供一个通孔；以及
f)在通孔里面沉积导电材料。
7.根据权利要求6所述的方法，其中，导电材料选自包括W和Al的一组。
8.根据权利要求6所述的方法，其中，除去步骤包括蚀刻该至少一个柱。
9.根据权利要求8所述的方法，其中，一种选自包括BHF和氧的组的蚀刻剂用于蚀刻步骤。
10.一种制造双镶嵌结构的方法，它包括：
a)在半导体基底的至少一部分上面形成牺牲材料层，该牺牲材料层被构图成至少一个柱；
b)在半导体基底的至少一部分上面形成金属间介电层，以便围住并覆盖该至少一个柱，该金属间介电层包括一第一介电层和一第二介电层，第一介电层的厚度小于或等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上，该金属间介电层具有平的表面；
c)蚀刻第二介电层，以便形成至少一个导线开口，其中第一介电层作为蚀刻中止层；以及
d)从金属间介电层上除去该至少一个柱，以便形成通孔。
11.根据权利要求10所述的方法，其中，牺牲材料层具有比金属间介电层高的蚀刻速率。
12.根据权利要求10所述的方法，其中，牺牲材料层用从包括可流动氧化物、CVD氧化物、BSG、SiN、聚对二甲基苯、聚酰亚胺和PBO的一组中所选出的材料制成。
13.根据权利要求10所述的方法，其中，金属间介电层用从包括有机掺杂的CVD氧化物、CVD氧化物以及含硅有机材料的一组中所选出的材料制成。
14.根据权利要求10所述的方法，其中，除去步骤包括蚀刻该至少一个柱。
15.根据权利要求14所述的方法，其中，选自包括BHF和氧气的一组的蚀刻剂被用于蚀刻步骤中。
16.根据权利要求10所述的方法，进一步包括用导电材料填满金属间介电层中的通孔的步骤。
17.根据权利要求16所述的方法，其中，导电材料选自包括W和Al的一组。
18.一种用来形成双镶嵌结构的结构，包括：
一个基底；
一个在所述基底上形成的具有第一蚀刻速率的牺牲材料的柱；
一个具有第二蚀刻速率并环绕柱的金属间介电层，第一蚀刻速率大于第二蚀刻速率，该金属间介电层包括一第一介电层和一第二介电层，第一介电层的厚度小于或等于所述至少一个柱的厚度，第二介电层形成在第一介电层之上，并且第二介电层的蚀刻速率大于第一介电层的蚀刻速率，从而第一介电层作为蚀刻第二介电层的蚀刻中止层；及
一个在金属间介电层中形成的露出柱的部分的导线开口。
19.根据权利要求18所述的结构，其中，所述基底包括一个导体，而柱位于上述导体的一部分之上。
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Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004870A (en) * 1997-08-26 1999-12-21 Texas Instruments Incorporated Method for forming a self-aligned contact
TW377502B (en) * 1998-05-26 1999-12-21 United Microelectronics Corp Method of dual damascene
US6096655A (en) * 1998-09-02 2000-08-01 International Business Machines, Corporation Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure
US6649515B2 (en) * 1998-09-30 2003-11-18 Intel Corporation Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
US6228758B1 (en) * 1998-10-14 2001-05-08 Advanced Micro Devices, Inc. Method of making dual damascene conductive interconnections and integrated circuit device comprising same
US6093632A (en) * 1998-12-07 2000-07-25 Industrial Technology Research Institute Modified dual damascene process
TW406369B (en) * 1998-12-18 2000-09-21 United Microelectronics Corp Method for manufacturing damascene
JP3214475B2 (ja) * 1998-12-21 2001-10-02 日本電気株式会社 デュアルダマシン配線の形成方法
KR20000071346A (ko) * 1999-02-15 2000-11-25 가네꼬 히사시 듀얼다마신공정을 사용한 반도체장치 제조방법
US6204143B1 (en) * 1999-04-15 2001-03-20 Micron Technology Inc. Method of forming high aspect ratio structures for semiconductor devices
US6534870B1 (en) * 1999-06-15 2003-03-18 Kabushiki Kaisha Toshiba Apparatus and method for manufacturing a semiconductor device
US6329118B1 (en) * 1999-06-21 2001-12-11 Intel Corporation Method for patterning dual damascene interconnects using a sacrificial light absorbing material
KR100708491B1 (ko) * 1999-08-26 2007-04-16 브레우어 사이언스 인코포레이션 듀얼 다마신 공정을 위한 개선된 충전 조성물을 포함하는 기판구조체, 충전조성물의 도포방법, 충전조성물의 적합성 결정방법, 및 전구체 구조체
US6873087B1 (en) 1999-10-29 2005-03-29 Board Of Regents, The University Of Texas System High precision orientation alignment and gap control stages for imprint lithography processes
US6380003B1 (en) * 1999-12-22 2002-04-30 International Business Machines Corporation Damascene anti-fuse with slot via
US6319821B1 (en) * 2000-04-24 2001-11-20 Taiwan Semiconductor Manufacturing Company Dual damascene approach for small geometry dimension
EP1303792B1 (en) * 2000-07-16 2012-10-03 Board Of Regents, The University Of Texas System High-resolution overlay alignement methods and systems for imprint lithography
KR100827741B1 (ko) * 2000-07-17 2008-05-07 보드 오브 리전츠, 더 유니버시티 오브 텍사스 시스템 임프린트 리소그래피 공정을 위한 자동 유체 분배 방법 및시스템
AU2001280980A1 (en) * 2000-08-01 2002-02-13 Board Of Regents, The University Of Texas System Methods for high-precision gap and orientation sensing between a transparent template and substrate for imprint lithography
US20050274219A1 (en) * 2004-06-01 2005-12-15 Molecular Imprints, Inc. Method and system to control movement of a body for nano-scale manufacturing
US20060005657A1 (en) * 2004-06-01 2006-01-12 Molecular Imprints, Inc. Method and system to control movement of a body for nano-scale manufacturing
EP1352295B1 (en) * 2000-10-12 2015-12-23 Board of Regents, The University of Texas System Template for room temperature, low pressure micro- and nano-imprint lithography
US6440842B1 (en) * 2001-02-02 2002-08-27 Macronix International Co. Ltd. Method of forming a dual damascene structure by patterning a sacrificial layer to define the plug portions of the structure
US6355563B1 (en) * 2001-03-05 2002-03-12 Chartered Semiconductor Manufacturing Ltd. Versatile copper-wiring layout design with low-k dielectric integration
US20020164544A1 (en) * 2001-05-02 2002-11-07 Advanced Micro Devices, Inc. Dual damascene using removable via studs
US6964793B2 (en) * 2002-05-16 2005-11-15 Board Of Regents, The University Of Texas System Method for fabricating nanoscale patterns in light curable compositions using an electric field
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
US6821896B1 (en) 2001-05-31 2004-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method to eliminate via poison effect
US6448185B1 (en) 2001-06-01 2002-09-10 Intel Corporation Method for making a semiconductor device that has a dual damascene interconnect
US6680262B2 (en) 2001-10-25 2004-01-20 Intel Corporation Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface
US6488509B1 (en) 2002-01-23 2002-12-03 Taiwan Semiconductor Manufacturing Company Plug filling for dual-damascene process
US7060633B2 (en) * 2002-03-29 2006-06-13 Texas Instruments Incorporated Planarization for integrated circuits
US20030186536A1 (en) * 2002-03-29 2003-10-02 Brenner Michael F. Via formation in integrated circuits by use of sacrificial structures
US7037639B2 (en) * 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US7253112B2 (en) 2002-06-04 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene process
US20030235787A1 (en) * 2002-06-24 2003-12-25 Watts Michael P.C. Low viscosity high resolution patterning material
US6642139B1 (en) * 2002-06-28 2003-11-04 Macronix International Co., Ltd. Method for forming interconnection structure in an integration circuit
US6926929B2 (en) 2002-07-09 2005-08-09 Molecular Imprints, Inc. System and method for dispensing liquids
US7077992B2 (en) * 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US7019819B2 (en) 2002-11-13 2006-03-28 Molecular Imprints, Inc. Chucking system for modulating shapes of substrates
US6900881B2 (en) 2002-07-11 2005-05-31 Molecular Imprints, Inc. Step and repeat imprint lithography systems
US6908861B2 (en) * 2002-07-11 2005-06-21 Molecular Imprints, Inc. Method for imprint lithography using an electric field
US7027156B2 (en) 2002-08-01 2006-04-11 Molecular Imprints, Inc. Scatterometry alignment for imprint lithography
US7070405B2 (en) * 2002-08-01 2006-07-04 Molecular Imprints, Inc. Alignment systems for imprint lithography
KR100462884B1 (ko) * 2002-08-21 2004-12-17 삼성전자주식회사 희생충진물질을 이용한 반도체 장치의 듀얼다마신배선형성방법
US7071088B2 (en) * 2002-08-23 2006-07-04 Molecular Imprints, Inc. Method for fabricating bulbous-shaped vias
US6900133B2 (en) * 2002-09-18 2005-05-31 Applied Materials, Inc Method of etching variable depth features in a crystalline substrate
US6794262B2 (en) * 2002-09-23 2004-09-21 Infineon Technologies Ag MIM capacitor structures and fabrication methods in dual-damascene structures
US8349241B2 (en) * 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
EP1579482A4 (en) * 2002-10-28 2009-03-18 Acute Inc METHOD AND DEVICE FOR PLANARIZING A SEMICONDUCTOR WAFER
US6872666B2 (en) * 2002-11-06 2005-03-29 Intel Corporation Method for making a dual damascene interconnect using a dual hard mask
US6980282B2 (en) * 2002-12-11 2005-12-27 Molecular Imprints, Inc. Method for modulating shapes of substrates
US6929762B2 (en) * 2002-11-13 2005-08-16 Molecular Imprints, Inc. Method of reducing pattern distortions during imprint lithography processes
US6871558B2 (en) * 2002-12-12 2005-03-29 Molecular Imprints, Inc. Method for determining characteristics of substrate employing fluid geometries
US7491639B2 (en) * 2002-12-20 2009-02-17 Nxp, B.V. Method of manufacturing a semiconductor device and semiconductor obtained by means of such a method
US7452574B2 (en) * 2003-02-27 2008-11-18 Molecular Imprints, Inc. Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer
US20040168613A1 (en) * 2003-02-27 2004-09-02 Molecular Imprints, Inc. Composition and method to form a release layer
US7186656B2 (en) * 2004-05-21 2007-03-06 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7179396B2 (en) * 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7323417B2 (en) * 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7122079B2 (en) * 2004-02-27 2006-10-17 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
GB2400245B (en) * 2003-04-01 2005-09-28 Power Gems Ltd Ignition system for a high-frequency high-intensity discharge lamp system
US7396475B2 (en) * 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US20050160934A1 (en) * 2004-01-23 2005-07-28 Molecular Imprints, Inc. Materials and methods for imprint lithography
US7157036B2 (en) * 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US7136150B2 (en) * 2003-09-25 2006-11-14 Molecular Imprints, Inc. Imprint lithography template having opaque alignment marks
US7090716B2 (en) * 2003-10-02 2006-08-15 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US8211214B2 (en) * 2003-10-02 2012-07-03 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US8076386B2 (en) * 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US7906180B2 (en) 2004-02-27 2011-03-15 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US7361455B2 (en) * 2004-03-31 2008-04-22 Intel Corporation Anti-reflective coatings
US20050276919A1 (en) * 2004-06-01 2005-12-15 Molecular Imprints, Inc. Method for dispensing a fluid on a substrate
US20050275311A1 (en) * 2004-06-01 2005-12-15 Molecular Imprints, Inc. Compliant device for nano-scale manufacturing
US6977210B1 (en) * 2004-06-08 2005-12-20 Nanya Technology Corporation Method for forming bit line contact hole/contact structure
KR100643568B1 (ko) 2004-06-30 2006-11-10 주식회사 하이닉스반도체 반도체소자의 깊은 콘택홀 형성 방법
US7205244B2 (en) * 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7547504B2 (en) * 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7041604B2 (en) * 2004-09-21 2006-05-09 Molecular Imprints, Inc. Method of patterning surfaces while providing greater control of recess anisotropy
US7252777B2 (en) * 2004-09-21 2007-08-07 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US7241395B2 (en) * 2004-09-21 2007-07-10 Molecular Imprints, Inc. Reverse tone patterning on surfaces having planarity perturbations
WO2006060757A2 (en) * 2004-12-01 2006-06-08 Molecular Imprints, Inc. Eliminating printability of sub-resolution defects in imprint lithography
US20060145398A1 (en) * 2004-12-30 2006-07-06 Board Of Regents, The University Of Texas System Release layer comprising diamond-like carbon (DLC) or doped DLC with tunable composition for imprint lithography templates and contact masks
US20060286792A1 (en) * 2005-06-20 2006-12-21 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene process
US7256131B2 (en) * 2005-07-19 2007-08-14 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate
US7452804B2 (en) * 2005-08-16 2008-11-18 Infineon Technologies Ag Single damascene with disposable stencil and method therefore
US7259102B2 (en) * 2005-09-30 2007-08-21 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
US7892962B2 (en) * 2007-09-05 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Nail-shaped pillar for wafer-level chip-scale packaging
FR2974194B1 (fr) 2011-04-12 2013-11-15 Commissariat Energie Atomique Procede de lithographie
US9761450B1 (en) * 2016-09-26 2017-09-12 International Business Machines Corporation Forming a fin cut in a hardmask
JP6982976B2 (ja) 2017-04-19 2021-12-17 キヤノン株式会社 半導体デバイスの製造方法および半導体デバイス
CN113571466B (zh) * 2020-04-29 2024-01-26 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
WO2023023060A1 (en) * 2021-08-16 2023-02-23 Microchip Technology Incorporated Method of forming an integrated circuit via

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
JPS60250650A (ja) * 1984-05-25 1985-12-11 Nec Corp 層間膜のスル−ホ−ル形成方法
DE59009067D1 (de) * 1990-04-27 1995-06-14 Siemens Ag Verfahren zur Herstellung einer Öffnung in einem Halbleiterschichtaufbau und dessen Verwendung zur Herstellung von Kontaktlöchern.
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure
US5158910A (en) * 1990-08-13 1992-10-27 Motorola Inc. Process for forming a contact structure
US5434451A (en) * 1993-01-19 1995-07-18 International Business Machines Corporation Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines
EP0609496B1 (de) * 1993-01-19 1998-04-15 Siemens Aktiengesellschaft Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene
JPH07122637A (ja) * 1993-10-25 1995-05-12 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH088209A (ja) * 1994-01-10 1996-01-12 Cypress Semiconductor Corp 半導体装置の製造のための除去されるポストの処理方法
US6297110B1 (en) * 1994-07-29 2001-10-02 Stmicroelectronics, Inc. Method of forming a contact in an integrated circuit
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
JPH08288385A (ja) * 1995-04-13 1996-11-01 Toshiba Corp 半導体装置の製造方法
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
US5614765A (en) * 1995-06-07 1997-03-25 Advanced Micro Devices, Inc. Self aligned via dual damascene
KR0179292B1 (ko) * 1996-04-12 1999-04-15 문정환 반도체소자의 다층배선 형성방법

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EP0890984A1 (en) 1999-01-13
KR19990007227A (ko) 1999-01-25
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