TW399314B - Improved dual damascene structure - Google Patents
Improved dual damascene structure Download PDFInfo
- Publication number
- TW399314B TW399314B TW087108059A TW87108059A TW399314B TW 399314 B TW399314 B TW 399314B TW 087108059 A TW087108059 A TW 087108059A TW 87108059 A TW87108059 A TW 87108059A TW 399314 B TW399314 B TW 399314B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- dielectric layer
- pillar
- forming
- item
- Prior art date
Links
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- 239000000463 material Substances 0.000 claims abstract description 55
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- 229910052751 metal Inorganic materials 0.000 claims description 16
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- 239000004020 conductor Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
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- NRNFFDZCBYOZJY-UHFFFAOYSA-N p-quinodimethane Chemical group C=C1C=CC(=C)C=C1 NRNFFDZCBYOZJY-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 4
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- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims 1
- 229920000052 poly(p-xylylene) Polymers 0.000 claims 1
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- NIHNNTQXNPWCJQ-UHFFFAOYSA-N fluorene Chemical compound C1=CC=C2CC3=CC=CC=C3C2=C1 NIHNNTQXNPWCJQ-UHFFFAOYSA-N 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 101000905241 Mus musculus Heart- and neural crest derivatives-expressed protein 1 Proteins 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 239000003353 gold alloy Substances 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1026—Forming openings in dielectrics for dual damascene structures the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
__p A 7 B7 五、發芯 ;q£L^lL· W 經濟部中央標準局員工消費合作社印製 刻(RIE),各向異性地蝕刻基板。移除未受光阻層保護之 拋棄式層的部分.留下對應於與導電區22接觸之通路位 冒的柱。雖然是用正光阻說明,但是也可以使用負光阻。 通常,導電層的柱之距離會根據已知導體之載流需求 而改變(如下之說明.導電材料會取代各螺柱1 2 ),使得 可以解決可靠度間題,如電子遷移。但是,在期望低電 流時.半導體的尺寸及間隔將限制,成為某特定半導體 元件及/或半導體製程之待定最小寬度。在各柱12之間 的寬度範圍通常約從0 . 1 5 w m到i . Ο /ζ πι ,約從0 . I 5 w m到 0.35« m較佳,約從0.15« m到0.35w ra則更佳。 至少一柱1 2樣態化之後,在半導體基板2 0之表面上和 柱12之上表而上形成IMD層5(參見第3圖)。用在此處所說 明之方法中的I M D材料可以包含本項技術人士所知的任 何滴當的介電材料。在一實施例中,IMD材料包含Α418 SOG. HSG-R7 S0G,有機摻雜的CVD氣化物,反相的CVD 氣化物,含矽材料,而未摻雜的矽酸玻璃,有機金屬, 如B C Β或類似之材料。 該IMD層5通常偽形成在半導體基板20的表面上和柱 12的整値上表而上,當作其後的平坦化層。在形成IMD 層之後,其後的平坦化層可直接透過成形製程完成,如 旋塗膜之方法,或藉由應用平坦化技術,如化學機械研 磨(CMP)予以完成。IMD之厚度要夠.才能足以容納柱及 在其下之導線。例如,IMD之厚度要比螺栓之高度大h , 其中h約等於導線之髙度。當然h取決於設計參數,通 8 - 本紙張尺度適用中國國家標準(CNS ) Λ4現格(210X297公浼) 扣衣------1T---;---^ . - (請先閱讀背面之注意事項再填寫本頁) Λ7 B7 五、發明説明(〖) mu 術—箫1 本發明傜關於一種半導體之製造,尤其是形成一種雙 紋路結構。 相-關』LJ5—背一 一般而言,半導體元件包含許多形成積體電路之電路 ,稽體雷路可以用在電腦和電子設備,且可能内含數以 百萬計可以製造在單矽晶半導體元件,即晶Η上之電晶 體和其他電路構件,,為了要使元件有功能,複雜的訊號 路徑網路通常會定路徑連接到分佈在元件表面上之電路 構件Λ當積體電路的複雜度增加時,這些橫越過元件之 訊號的有效路徑會變得更困難。因此,需要稱為雙紋路 結構之多層次或多層組態,因其能夠增加元件的密度, 所以,圮許緊密組裝的半導體元件之堆叠交互連接水準 (stacked interconnected levels) 〇 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 當製诰具有雙紋路結構之積體電路時,例如,半導體 元件之絶緣或介電質材料,如氣化矽,通常會製作數千 値開口,以産生導線開口和通路開口。然後,再用導電 金屬層,如鋁,填谋該導線和通路開口.積體電路的主 動和/或被動構件交互連接。該雙紋路結構也可用於形 成多厣基板之絶緣層(如聚醯亞胺)内的多層次金鼷(如 銅)導線,其中該基板可安裝至半導體元件上。 製造雙紋路結構之方法,已廣為人知.例如,參見美 國專利第 5,422,309; 5,529,953; 5,602,423;和 5,614,765 -3 - 本紙悵尺度適用中國國家標準(CNS ) Λ4規格(210X297公兑) Λ7 B7 五、發明説明(> ) 號。一般而言,製造一標準雙纹路結構可以先用抗反射 塗層(ARC)及光阻劑層塗覆之絶線層。之後,透過具有 通路開口影像圖樣之第一光罩,將光阻曝光,再各向異 性地蝕刻該画案以穿透絶緣層,露出其下之導電層。在 蝕刻該通路開口之後,移除其餘的ARC和光阻。然後再 沈穑新的ARC和光阻層。透過具有導線開口影像圖樣之 第二光罩,將該光阻曝光。該第二影像圖樣通常對齊該 第一光罩圖樣以包圍具有導線開口之通路開口。要形成 導線開口之光阻部分被除去,曝露出該通路開口和絶緣 層,、之後,蝕刻該曝露出的絶緣層至一所要的深度,其 等於導線高度。當蝕刻完成時,將通路開口和導線開口 都用一導電金屬層填滿。 ARC和光阻層的第二次沈積使通路充填ARC,導致在後 繼之形成導線開口之蝕刻期間,在該通路孔洞中形成聚 合物。由於基本的規則(groundru丨es>變得愈來愈小, 經濟部中央標準局員工消費合作社印製 (請义閱讀背面之注意事項再填寫本頁) 此種聚合物之形成在通路和導線開口之介面上導致Si02 柵橱(fence)。棚稱之出現使金屬流入通路受到干擾而 在内部造成空隙,在某些情形下,此種空隙會造成通路 電阳增加,且在某些狀況下通路失敗。 由上述之討論,有需要提供未在通路-導線上形成柵 欄之雙紋路結構。 明-總1 一種嶄新的雙紋路結構製造方法.包含之步驟有:在 半導體基板上形成一抛棄式材料層;形成一内金鼷介電 -4 - 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X 297公筇) ΑΊ Β7 五、發明説明(4 ) 層在該半導體基板上;蝕刻在該中間金鼷介電層中的導 線開口,且移除該抛棄式材料層。 於一很有用的實施例中,其方法包含之步驟有: a) 至少在部分的半導體基板上形成一抛棄式材料層; b) 使該抛棄式材料層樣態化,成為至少一傾柱(stud); c) 至少在部分的半導體基板上形成一中間金靨介電層; d) 在該内金靨介電層中至少蝕刻一導線開口; e) 自該内金驅介電層移除至少一柱;及 f )在該内金屬介電層中用導電材料至少取代一樣。 圖式 雙紋路結構之製造方法的優選實施例參考圖式說明於 後,其中: 第1圖為在半導體基板上所形成之抛棄式材料層的横 截而圖; 第2圖為在半導體基板上,將該抛棄式材料層製成螺栓 圖案之樺截面圖; 第3圈為形成在該半導體基板表面上,且覆蓋該柱之 上表而之該内金驅介電層之橫截面圖; 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 第4 _為蝕刻後之導線開口的横截面圖; 第5圖為移除柱後之導線開口的横截面画;及 第6圖為填滿導電金屬層之導線開口和通路開口的横截 而圖^ 優i實例JgJl· 本發明俗關於積體電路(I C s )之製造。此種I C s包含記 -5 - 本纸认尺戍迻:i】中内《家撑準(CNS ) Μ規格(2丨) 經濟部中央標準局貝工消費合作社印装 Λ7 B7 五、發明説明(4 ) 億體電路類,如隨機存取記億體(RAMs).動態RAMs(DRAMs) ,同步DRAMs(SDRAMs),靜態、RAMs(SRAMs)及唯讀記億 體(ROMs)。還有其他的ICs,包含邏輯元件,如可程式 邏輯陣列(PLAs),待用ICs(ASICs)或任何電路元件。本 發明提供一種基本上在導線和通路開口之介面,沒有不 良的定義邊緣。通常,在半導體基板,如矽晶圓上,會 同時製诰許多平行的ICs。所以在製程結束後,為了分 隔1C ,要將晶圖切割成許多個別的晶Η。然後再將晶片 組裝成最後客戶所用的産品,如計算機系統,行動電話 .個人數位式援肋系統(PDAs)及其他産品。 在一奮_例中,本發明包含與介電材料有關之拋棄式 材料的使用,其中有形成該雙紋路結構。内部形成有該 雙紋路結構之層在此處稱為中間金屬介電層(IMD)。不 良的定義邊緣可以藉由選擇比IMD有較高濕或乾蝕刻速率 之拋棄式材料而避免。 參考第1圖,其顯示部分的半導體基板20。例如,該 基板為矽晶圓。也可以使用其他的基板,如砷化鎵,絶 綠體上之矽(SOI),鍺或其他的半導體材料。基板20包含 形成在其上之ICs(未顯示 該ICs可以處在任何的製程 階段。在基板上還包含位在其下之導電區22,如金屬化 層,、可選擇地,導電區為高摻雜之多晶矽層或主動元件 的仟何部分,如電晶體的源極或汲掻區。在一實施例中 ,導電區表示DRAM晶片之位元線,例如,該導電區可以 ϋ由介電材料予以絶緣。通常.要將上表面30平坦化, -6 - 本紙張尺度適用中國國家標準(CNS ) A4J1見格(210> 297公炱) ---------Λ------訂 (請洗閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局貝工消费合作社印裝 五、發明説明 ( f ) 1 1 才 能 提 供 一 平 坦 的 上 表 面 〇 I C 'S可以包含額3 +的元件, 1 1 I 電 氣 回 路 和 其 他 交 互 連 接 的 同 级 元 件 〇 1 1 如 圖 所 示 9 抛 棄 式 材 料 層 1 5偽 形 成 在 半 導 體 基 板 2C 之 1 先 1 表 面 3 0上 〇 可 用 作 抛 棄 式 材 料 層 1 5之 適 當 材 料 包 含 已 知 閱 讀 1 背 1 技 術 技 m 中 的 任 何 傳 統 材 料 〇 在 實 施 例 中 > 形 成 層 15 1¾ 之 1 所 採 用 之 材 料 包 含 可 流 動 氣 化 物 » C V D氣化物, BSG SiN 意 1 事 1 5 不 含 矽 之 材 料 , 如 對 苯 二 甲 撐 9 聚 醯 亞 胺 (如烕光聚 項 1 填 1 m 亞 胺 )和P B0 > 及 類 似 之 材 料 0 用 在 此 處 說 明 之 方 法 中 寫 ·. 本 | 的 拋 棄 式 材 料 > 其 濕 和 / 或 乾 蝕 刻 速 率 基 本 上 高 於 形 成 頁 1 | 在 半 導 體 基 板 2 0 上 之 I Μ D層, 此說明於後。 - 1 | 為 了 要 達 到 適 當 的 均 勻 厚 度 » 通 常 將 抛 棄 式 材 料 層 1 1 1 5大 致 上 先 平 坦 化 » 如 果 需 要 可 以 採 用 個 別 的 平 坦 化 1 訂 1 1 步 驟 , 如 C Μ P〇 通常, 形成在半導體基板2 0上之抛棄式 材 料 層 1 5的 厚 度 * 大 概 至 少 要 等 於 或 大 於 依 本 發 明 方 法 1 1 所 形 成 之 通 路 開 P 之 期 望 高 度 〇 抛 棄 式 材 料 層 1 5之 厚 度 1 I 範 圍 約 從 1 , 00 0 X到 10 ,0 00 〇 A, 約從1 ,〇 0 0 A到8 ,〇 0 0 X較佳 1 1 ♦ 約 3, 0 0 0 X到 6 , 0 0 6 0 A 更 佳 〇 1 當 然 > 厚 度 之 變 化 取 決 於 設 計 參 數 〇 - 1 I 參 考 第 2 圖 9 抛 棄 式 層 被 樣 態 化 » 至 少 形 成 一 柱 12 ,於 1 1 該 處 將 形 成 通 路 孔 洞 或 開 P 〇 在 基 板 之 實 例 部 分 9 偽 形 1 1 成 3 m 柱 〇 但 是 » 本 項 技 術 人 士 將 會 瞭 解 在 1C S之製迪 1 中 * 可 以 形 成 許 多 的 柱 » 以 接 觸 在 其 下 之 導 電 區 〇 例 如 1 f 拋 棄 式 層 的 樣 態 化 包 含 沈 積 ARC和光阻層, 及用曝光 1 I 源 使 待 形 成 柱 之 區 域 外 的 光 阻 曝 光 〇 然 後 將 該 光 阻 層 顳 1 影 * 再 移 除 曝 光 的 部 分 〇 7 之 後 由 例 如 9 反 m 離 子 拽 1 1 1 1 本纸張尺度適用中國國家標皁(C'NS 1 ; :!() )
__p A 7 B7 五、發芯 ;q£L^lL· W 經濟部中央標準局員工消費合作社印製 刻(RIE),各向異性地蝕刻基板。移除未受光阻層保護之 拋棄式層的部分.留下對應於與導電區22接觸之通路位 冒的柱。雖然是用正光阻說明,但是也可以使用負光阻。 通常,導電層的柱之距離會根據已知導體之載流需求 而改變(如下之說明.導電材料會取代各螺柱1 2 ),使得 可以解決可靠度間題,如電子遷移。但是,在期望低電 流時.半導體的尺寸及間隔將限制,成為某特定半導體 元件及/或半導體製程之待定最小寬度。在各柱12之間 的寬度範圍通常約從0 . 1 5 w m到i . Ο /ζ πι ,約從0 . I 5 w m到 0.35« m較佳,約從0.15« m到0.35w ra則更佳。 至少一柱1 2樣態化之後,在半導體基板2 0之表面上和 柱12之上表而上形成IMD層5(參見第3圖)。用在此處所說 明之方法中的I M D材料可以包含本項技術人士所知的任 何滴當的介電材料。在一實施例中,IMD材料包含Α418 SOG. HSG-R7 S0G,有機摻雜的CVD氣化物,反相的CVD 氣化物,含矽材料,而未摻雜的矽酸玻璃,有機金屬, 如B C Β或類似之材料。 該IMD層5通常偽形成在半導體基板20的表面上和柱 12的整値上表而上,當作其後的平坦化層。在形成IMD 層之後,其後的平坦化層可直接透過成形製程完成,如 旋塗膜之方法,或藉由應用平坦化技術,如化學機械研 磨(CMP)予以完成。IMD之厚度要夠.才能足以容納柱及 在其下之導線。例如,IMD之厚度要比螺栓之高度大h , 其中h約等於導線之髙度。當然h取決於設計參數,通 8 - 本紙張尺度適用中國國家標準(CNS ) Λ4現格(210X297公浼) 扣衣------1T---;---^ . - (請先閱讀背面之注意事項再填寫本頁) A7 137 五、發明説明(7 ) 常,中間金屬介電層5之厚度範圍傺約從2000 λ到20000又 ,以約從30()()1到200〇i較佳,而約從4000Α到900(^更佳。 用以形成中間金颶介電層5之技術傜在本項技術人 士能理解的範圍内。 可選擇地,該IMD層稍小於或約等於該柱之厚度。在 平坦化之後,在其上形成第二I MD層。此第二ΙΟ層之厚 度通常約第於導線之高度。第二IHD層為一種可以選擇 性蝕刻到第一 ΙΜΙ)層之材料。藉由雙IMD層之提供,該第 一 IMD層作為藉蝕刻而形成在其下之導線畤的蝕刻停止 層〇 經濟部中央標隼局員工消费合作社印聚 (請先閱讀背而之注意事項再填寫本頁 '1Τ 參考第4圖,ΙΜΙ)層樣態化,以産生導線開口 9導線開 口之樣態化俗使用傳統的徹影製程和蝕刻技術完成。例 如,此種技術包含沈積ARC和光阻層,及其後用曝光源 如深紫外線(DUV)或極深紫外線(EUV)之射光,選擇性曝 光該光阻層。也可以使用其他波長之射光,之後顯影, 移除光阻層之曝光區,以曝露對應線開口 9之IMD表面 。再用RIE産生開口 9, RIE在適當時機終fh,以蝕刻的 夠深,才能到達柱之頂部,或是當使用雙IMD層時,用 蝕刻停It層技術终止。 其次,從導線開口 9之中,藉由濕或乾蝕刻製程,選 擇性移除各個柱12,以産生通路開口 11,(如第5圖所示) 。根據本發明,可以選擇性蝕刻該柱到該I M D層。該柱和 IMD之間的蝕刻選擇性要夠,才能不用實際上,移除該IMD 層而可以移除柱。在一實施例中,該柱和IMD之間的蝕刻 本紙张Κ度適用中國國家標準(CNS ) ( 210Χ297公#·) 經滴部中央標準局員工消费合作社印54 A7 137 五、發明説明(及) 遴擇性約差8·· 1,約差12: 1更佳,而約g20: 1則更佳。 用以産生通路開口 11之參數(如蝕刻劑之種類,蝕刻劑 之濃度,時間,溫度等)俗在本技術人士所知之範圍中。 蝕刻劑之選擇取決於數値因子,其中包含柱之組成。適 合的蝕刻劑包含BHF, CDE和氣。表1表列可以使用以移 除柱之蝕刻劑的材料和種類。 表 1 抛秦式材料 IMD 蝕刻物 -------------------訂 (請先間讀背而之注意事項再填寫本頁) 可流動的氣化物(F 0 X ) A4 18 SOG BH F F〇 X HSG-R7 S0G BHF F〇 X 有機摻雜的 CVD 氧化物 BHF F〇 X C V D氣化物 BH F CVD氣化物 A4 18 S0G BHF C V D氧化物 HSG-R7 S0G BHF BSG A418 S0G BHF BSG HSG-R7 S0G BHF BSG 有機摻雜的 CVD 氣化物 BHF BS G 反相的CVD氧化物 BHF S i N CVD氣化物 CDE 有機材料, 不含矽的材料(對 CVD氣化物 氣 苯二甲撐, 聚酵亞胺, P B0 ) 有機材料, 不含矽的材 料(對苯含S i的有機 氣 二甲撐,正 威光聚挺亞 胺,ΡΒ0)金鼷(BCB) -10- 本紙張乂度沩^ W ( ('NS ) Λ4 規枋(2 1 Ο X 297,:.> 兮) 經濟部中央標準局員工消費合作社印聚 Λ7 B7五、發明説明(9 ) 在形成通路開口 11之後,將導電材料25沈積在其中, 曰.请滿通路開口 11和導線開口 9。如第6圖所示。導電 材料25可藉由任何已知的或傳統的程序形成,如利用選 擇性的化學氣相沈積法(C V D )。此處可以使用任何的傳 統導雷材料,形成導電材料2 5之適用材料包含但不僅限 於Ti, TiN, TiW, W,Al,Cu. Pd或類似之材料。而較佳之 材料為W和A U 雖然本發明已參者上述具有某種程度特殊性之實施例 説明.但是變化例和變更例有可能在那些技術技藝中, 因此,本發明表示其為不離本發明精神和範圍之恃別説 明,、 參考符號説明 (請先閱讀背面之注意事項再填寫本頁)
、1T 15......拋棄式材料層 20......半導體基板 2 2......導電區 5.......IMD 層 12......柱 9.......線開口 11......通路開口 -11- 本紙張尺度適用中國國家標隼(CNS ) Λ4規格(210X 297公处)
Claims (1)
- g71 〇8〇59 399314 asC8 ' D8 經濟部中央標準局員工消費合作社印裝 六、申請專利範圍 1 1 1 .一 種 製 造 雙 紋 路 結 構 之 方 法 • 包 含 * 1 1 a)在 至 少 包 含 一 導 電 區 之 半 導 體 基 板 上 形 成 一 層 抛 1 I 棄 式 (s a c r i f i c i a 1 )材料層 • » 請 1 1 b)使 抛 棄 式 材 料 層 之 樣 態 化 以 在 該 導 電 區 上 能 至 少 先 閱 1 I 讀 1 1 提 供 一 柱 (S t U d) 背 ιέ 1 1 之 1 c )在 環 繞 至 少 柱 之 半 導 醱 基 板 上 形 成 介 電 層 及 注 I 意 I d) 在 中 間 金 屬 介 電 層 中 » 形 成 導 線 開 □ i 至 少 一 柱 事 項 1 I 再 1 Λ 之 一 部 分 會 曝 露 在 開 Π 之 中 〇 法 其 中 寫 本 衮 2 •如 請 專 利 範 圍 第 1 項 之 方 » 該 抛 棄 式 材 料 層 頁 之 蝕 刻 速 率 大 於 該 中 間 金 靥 介 電 層 〇 ! 3 .如 申 請 專 利 範 圍 第 1 項 之 方 法 其 中 該 抛 棄 式 材 料 層 1 I 之 材 料 傷 選 擇 白 由 可 流 動 的 氧 化 物 * CVD氧化物, BSG 1 1 訂 1 9 s i N聚對苯二甲撐( pa r y 1 e n e ), 聚醅亞胺和ΡΒ0所 組 成 之 組 群 〇 1 I 4 •如 請 專 利 範 圍 第 1 項 之 方 法 9 其 中 該 中 間 金 颺 介 電 1 1 層 之 材 料 僳 選 擇 白 由 有 機 摻 雜 的 c V D氣化物, C VD 氧 化 1 | 物 和 含 矽 有 機 材 料 所 組 成 之 組 群 〇 | 5 .如 申 請 專 利 範 圍 第 1 項 之 方 法 9 進 一 步 包 含 ; 在 形 成 1 1 導 線 開 η 前 之 中 間 金 颳 介 電 層 的 平 坦 化 步 驟 〇 1 | 6 如 申 請 專 利 範 圍 第 1 項 之 方 法 9 還 包 含 之 步 驟 為 ! 1 e ) 白 該 中 間 金 屬 介 電 層 移 除 該 至 少 一 柱 9 以 形 成 通 1 I 道 及 1 1 f)沈 積 一 導 電 材 料 在 該 通 道 内 〇 1 1 7 .如 申 請 專 利 範 圍 第 6 項 之 方 法 t 其 中 該 導 電 材 料 % 選 1 1 -1 2- 1 1 1 1 本紙伕尺度適用中國國家標準(CNS ) Λ·4現格(-、:〇y 公釐) A8 393314 ll D8 六、申請專利範圍 擇自由W和A丨組成之組群。 8. 如申請專利範圍第6項之方法,其中該移除步驟包含 蝕刻該至少一柱。 9. 如申請專利範圍第8項之方法,其中蝕刻步驟中所用 之鈾刻劑俗遘自BHF和氣所組成之組群。 10. —種製造雙紋路結構之方法,包含: a) 在至少一部分的半導體基板上形成一拋棄式材料 層.該拋棄式材料層係要製作成至少一個柱之樣態; b) 在至少一部分的該半導體基板上形成一中間金屬 介電層,環繞並覆蓋至少一柱,該中間金屬介電層具 有一平坦的表面; c )蝕刻該中間金屬介電層,至少要形成一痼導線開 口 ;及 d >自該中間金屬介電層移除該至少一柱而形成通路。 11. 如申請專利範圍第10項之方法,其中該抛棄式材料層 之蝕刻速率高於該中間金屬介電層。 經滴部中央標準局員工消費合作社印裝 (請先閱讀背面之注意事項再填寫本頁) 12. 如申請專利範圍第10項之方法,其中該拋棄式材料 厣之材料俗選擇自由可流動的氣化物,CVD氣化物, BSG, SiN,對苯二甲撑,聚醯亞胺和ΡΒ0所組成之組 群。 13. 如申請專利範圍第10項之方法,其中該中間金颶介 電層之材料偽選擇自由有機摻雜的CVD氣化物,CVD氣 化物和含矽有機材料所組成之組群。 14. 如申請專利範圍第10項之方法,其中該移除步驟包 -1 3 - 本紙張尺度適用中國國家標準(CNS ) Λ4规格(2丨0X 297公釐) 399314 A8 Βδ C8 D8 六、申請專利範圍 含該至少一柱之蝕刻。 15. 如申謫專利範圍第14項之方法,其中在蝕刻步驟所 使用之蝕刻劑僳選擇自由B H F和氣所组成之組群。 16. 如申請專利範圍第10項之方法,還包含用導電材料 埔充在該中間金腸介電層中之通輅的步驟。 17. 如申謫專利範圍第16項之方法,其中該導電材料係 選擇自由W和Α1所組成之組群。 18. —種形成雙紋路結構所用之結構,包含: -基板; -形成在該基板上,具有第一蝕刻速率之抛棄式材 料柱; -具有第二蝕刻速率且環繞該柱之中間金颶介電層 ,該第一蝕刻速率大於第二蝕刻速率;及 -導線開口,形成在該中間金颶介電層中,且曝露 一部分之柱。 19. 如申請專利範圍第18項之結構,其中該基板包含一 導體,且該柱位在一部分之導體上。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 -14- 本紙張尺度適用中國國家標隼(CNS ) Λ4規格(210Χ 297公釐)
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- 1998-05-25 TW TW087108059A patent/TW399314B/zh not_active IP Right Cessation
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- 1998-06-05 DE DE69826934T patent/DE69826934T2/de not_active Expired - Lifetime
- 1998-06-23 KR KR1019980023582A patent/KR100535798B1/ko not_active IP Right Cessation
- 1998-06-30 JP JP18405798A patent/JP4690509B2/ja not_active Expired - Fee Related
- 1998-06-30 CN CNB981156290A patent/CN1152413C/zh not_active Expired - Fee Related
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KR100535798B1 (ko) | 2006-02-28 |
CN1208947A (zh) | 1999-02-24 |
JP4690509B2 (ja) | 2011-06-01 |
EP0890984A1 (en) | 1999-01-13 |
JPH1174356A (ja) | 1999-03-16 |
KR19990007227A (ko) | 1999-01-25 |
DE69826934T2 (de) | 2005-10-13 |
EP0890984B1 (en) | 2004-10-13 |
CN1152413C (zh) | 2004-06-02 |
US6033977A (en) | 2000-03-07 |
DE69826934D1 (de) | 2004-11-18 |
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