KR100614782B1 - 이중 다마신 구조를 포함하는 집적회로 제조방법 및 집적회로 - Google Patents
이중 다마신 구조를 포함하는 집적회로 제조방법 및 집적회로 Download PDFInfo
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- KR100614782B1 KR100614782B1 KR1020000050713A KR20000050713A KR100614782B1 KR 100614782 B1 KR100614782 B1 KR 100614782B1 KR 1020000050713 A KR1020000050713 A KR 1020000050713A KR 20000050713 A KR20000050713 A KR 20000050713A KR 100614782 B1 KR100614782 B1 KR 100614782B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (24)
- 집적회로를 제조하는 방법에 있어서,(a)제 1 마스크층을 사용하여, 제 1 층, 제 2 층 및 정지층을 갖는 층들의 스택에 제 1 개구를 형성하는 단계와,(b)상기 제 1 마스크층을 완전히 제거하기 이전에, 제 2 마스크층을 사용하여 상기 층들 중 적어도 한 층내에 베이스를 갖는 제 2 개구를 형성하는 단계로서, 상기 제 2 개구는 상기 제 1 개구보다 크고, 상기 제 1 개구는 상기 베이스의 적어도 일부분에 형성되는, 상기 제 2 개구 형성 단계를 포함하고, 상기 단계 (a)는 상기 제 2 마스크층을 형성하기 이전에 실행되는, 집적회로 제조 방법.
- 제 1 항에 있어서, 상기 스택을 형성하기 위해 상기 제 1 층과 상기 제 2 층사이에 상기 정지층을 형성하는 단계를 더 포함하는, 집적회로 제조 방법.
- 제 2 항에 있어서, 상기 단계 (a)는 상기 정지층, 상기 제 1 층 및 상기 제 2 층내에 상기 제 1 개구를 형성하는 단계를 더 포함하는, 집적회로 제조 방법.
- 제 3 항에 있어서, 상기 단계 (b)는 상기 제 1 층 및 상기 제 2 층 중 한 층내에 상기 제 2 개구를 형성하는 단계를 더 포함하는, 집적회로 제조 방법.
- 제 1 항에 있어서, 상기 정지층은 TaN, Si3N4, 실리콘 과다 산화물(silicon-rich oxide) 및 다층 SiO2 유전체로 구성되는 그룹으로부터 선택되는, 집적회로 제조 방법.
- 제 1 항에 있어서, 상기 제 1 층 및 상기 제 2 층은 유전체인, 집적회로 제조 방법.
- 제 1 항에 있어서, 상기 집적회로내에 상호접속들을 형성하기 위해, 상기 제 1 개구 및 상기 제 2 개구내에 도전성 재료를 형성하는 단계를 더 포함하는, 집적회로 제조 방법.
- 제 1 항에 있어서, 상기 베이스를 형성하기 위해 상기 정지층의 표면을 노출하는 단계를 더 포함하는, 집적회로 제조 방법.
- 제 1 항에 있어서, 상기 제 1 마스크층 및 상기 제 2 마스크층을 사용하여 이중 다마신 구조(dual damascene structure)를 형성하는 단계를 포함하는, 집적회로 제조 방법.
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Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/386,065 | 1999-08-30 | ||
US09/386,065 US6365327B1 (en) | 1999-08-30 | 1999-08-30 | Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit |
US9/386,065 | 1999-08-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010030170A KR20010030170A (ko) | 2001-04-16 |
KR100614782B1 true KR100614782B1 (ko) | 2006-08-25 |
Family
ID=23524018
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000050713A KR100614782B1 (ko) | 1999-08-30 | 2000-08-30 | 이중 다마신 구조를 포함하는 집적회로 제조방법 및 집적회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6365327B1 (ko) |
JP (2) | JP2001110900A (ko) |
KR (1) | KR100614782B1 (ko) |
GB (1) | GB2356973B (ko) |
TW (1) | TW498523B (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
US6762087B1 (en) * | 2000-06-16 | 2004-07-13 | Agere Systems Inc. | Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor |
GB2368721A (en) * | 2000-06-16 | 2002-05-08 | Agere Syst Guardian Corp | Integrated circuit with damascene structure and capacitor |
US6537866B1 (en) * | 2000-10-18 | 2003-03-25 | Advanced Micro Devices, Inc. | Method of forming narrow insulating spacers for use in reducing minimum component size |
US6790772B2 (en) * | 2002-05-09 | 2004-09-14 | Macronix International Co., Ltd. | Dual damascene processing method using silicon rich oxide layer thereof and its structure |
US7186640B2 (en) * | 2002-06-20 | 2007-03-06 | Chartered Semiconductor Manufacturing Ltd. | Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics |
US7217649B2 (en) * | 2003-03-14 | 2007-05-15 | Lam Research Corporation | System and method for stress free conductor removal |
US7078344B2 (en) * | 2003-03-14 | 2006-07-18 | Lam Research Corporation | Stress free etch processing in combination with a dynamic liquid meniscus |
US7232766B2 (en) * | 2003-03-14 | 2007-06-19 | Lam Research Corporation | System and method for surface reduction, passivation, corrosion prevention and activation of copper surface |
US7009281B2 (en) * | 2003-03-14 | 2006-03-07 | Lam Corporation | Small volume process chamber with hot inner surfaces |
KR100721195B1 (ko) * | 2004-12-02 | 2007-05-23 | 주식회사 하이닉스반도체 | 반도체 소자의 듀얼 다마신 금속 배선 형성 방법 |
KR100591136B1 (ko) * | 2005-05-27 | 2006-06-20 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5635423A (en) * | 1994-10-11 | 1997-06-03 | Advanced Micro Devices, Inc. | Simplified dual damascene process for multi-level metallization and interconnection structure |
JP2872086B2 (ja) * | 1995-08-30 | 1999-03-17 | 日本電気株式会社 | 半導体装置の製造方法 |
US5880018A (en) | 1996-10-07 | 1999-03-09 | Motorola Inc. | Method for manufacturing a low dielectric constant inter-level integrated circuit structure |
JPH10209273A (ja) * | 1997-01-16 | 1998-08-07 | Fujitsu Ltd | 半導体装置の製造方法 |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
JP3183238B2 (ja) * | 1997-11-27 | 2001-07-09 | 日本電気株式会社 | 半導体装置の製造方法 |
US6291334B1 (en) | 1997-12-19 | 2001-09-18 | Applied Materials, Inc. | Etch stop layer for dual damascene process |
JPH11186391A (ja) * | 1997-12-25 | 1999-07-09 | Toshiba Corp | 半導体装置およびその製造方法 |
US6042999A (en) * | 1998-05-07 | 2000-03-28 | Taiwan Semiconductor Manufacturing Company | Robust dual damascene process |
US6211092B1 (en) | 1998-07-09 | 2001-04-03 | Applied Materials, Inc. | Counterbore dielectric plasma etch process particularly useful for dual damascene |
US6127263A (en) * | 1998-07-10 | 2000-10-03 | Applied Materials, Inc. | Misalignment tolerant techniques for dual damascene fabrication |
US6245662B1 (en) | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
TW437040B (en) | 1998-08-12 | 2001-05-28 | Applied Materials Inc | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
EP1112590A1 (en) * | 1999-07-01 | 2001-07-04 | Lam Research Corporation | Method for patterning a layer of a low dielectric constant material |
-
1999
- 1999-08-30 US US09/386,065 patent/US6365327B1/en not_active Expired - Lifetime
-
2000
- 2000-06-14 TW TW089111610A patent/TW498523B/zh not_active IP Right Cessation
- 2000-08-08 GB GB0019487A patent/GB2356973B/en not_active Expired - Fee Related
- 2000-08-14 JP JP2000245497A patent/JP2001110900A/ja active Pending
- 2000-08-30 KR KR1020000050713A patent/KR100614782B1/ko active IP Right Grant
-
2009
- 2009-02-16 JP JP2009032389A patent/JP5334616B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6365327B1 (en) | 2002-04-02 |
TW498523B (en) | 2002-08-11 |
GB2356973B (en) | 2003-02-19 |
JP2009111429A (ja) | 2009-05-21 |
GB0019487D0 (en) | 2000-09-27 |
JP5334616B2 (ja) | 2013-11-06 |
JP2001110900A (ja) | 2001-04-20 |
KR20010030170A (ko) | 2001-04-16 |
GB2356973A (en) | 2001-06-06 |
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