CN114203667A - 具有三维结构的半导体装置 - Google Patents
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- CN114203667A CN114203667A CN202110366848.6A CN202110366848A CN114203667A CN 114203667 A CN114203667 A CN 114203667A CN 202110366848 A CN202110366848 A CN 202110366848A CN 114203667 A CN114203667 A CN 114203667A
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Abstract
本公开提供一种具有三维结构的半导体装置,该半导体装置包括:第一晶圆,第一晶圆包括在其一个表面上的第一接合焊盘;第二晶圆,第二晶圆包括在其接合至第一晶圆的所述一个表面的一个表面上的接合至第一接合焊盘的第二接合焊盘;多个防翘曲凹槽,多个防翘曲凹槽在第一晶圆的所述一个表面上,并且被布置为条形形状;以及多个防翘曲肋部,多个防翘曲肋部在第二晶圆的所述一个表面上,多个防翘曲肋部分别联接至多个防翘曲凹槽,并且被布置为条形形状。
Description
技术领域
各个实施方式总体上涉及一种半导体技术,并且更具体地,涉及一种具有使用晶圆接合技术的三维结构的半导体装置。
背景技术
在半导体装置中,为了高容量和小型化的提高,需要增加集成度。用于增加集成度的提案包括这样的结构:其中,包括在半导体装置中的组件不是在单个晶圆上制造,而是分开地在至少两个晶圆上制造,并且然后晶圆被接合以电联接组件。
在半导体制造工艺中使用的材料层具有固有应力(intrinsic stress),并且由于材料层沉积工艺和热处理工艺引起的应力,在晶圆中可能出现翘曲。当晶圆中出现翘曲时,可能出现接合失败,其中,晶圆之间的粘合力降低并且晶圆之间的电联接被切断。
发明内容
各个实施方式致力于提出能够抑制或减少晶圆翘曲的措施。
在一个实施方式中,具有三维结构的半导体装置可以包括:第一晶圆,第一晶圆包括在其一个表面上的第一接合焊盘;第二晶圆,第二晶圆包括在其接合至第一晶圆的所述一个表面的一个表面上的接合至第一接合焊盘的第二接合焊盘;多个防翘曲凹槽,多个防翘曲凹槽在第一晶圆的所述一个表面上,并且被布置为条形形状;以及多个防翘曲肋部,多个防翘曲肋部在第二晶圆的所述一个表面上,多个防翘曲肋部分别联接至多个防翘曲凹槽,并且被布置为条形形状。
在一个实施方式中,具有三维结构的半导体装置可以包括:第一晶圆,第一晶圆包括在其一个表面上的第一接合焊盘;第二晶圆,第二晶圆包括在其接合至第一晶圆的所述一个表面的一个表面上的接合至第一接合焊盘的第二接合焊盘;多个第一防翘曲焊盘,多个第一防翘曲焊盘在第一晶圆的所述一个表面上,并且被布置为条形形状;以及多个第二防翘曲焊盘,多个第二防翘曲焊盘在第二晶圆的所述一个表面上,并且分别接合至多个第一防翘曲焊盘,并且多个第二防翘曲焊盘被布置为条形形状。
在一个实施方式中,具有三维结构的半导体装置可以包括:第一晶圆,第一晶圆包括在其一个表面上的第一接合焊盘;第二晶圆,第二晶圆包括在其接合至第一晶圆的所述一个表面的一个表面上的接合至第一接合焊盘的第二接合焊盘;以及多个防翘曲金属肋部,多个防翘曲金属肋部被限定在第一晶圆中,并且被布置为条形形状。
附图说明
图1是示出根据本公开的实施方式的具有三维结构的半导体装置的截面图。
图2是示出防翘曲凹槽的设置的俯视图。
图3A至图3C是示出配置单位区域的方法的俯视图。
图4A是示出根据本公开的另一实施方式的具有三维结构的半导体装置的截面图。
图4B是示出图4A的防翘曲凹槽和第一防翘曲焊盘的延伸方向的俯视图。
图5A、图6A、图7A和图8A是示出根据本公开的其它实施方式的具有三维结构的半导体装置的截面图。
图5B、图6B、图7B和图8B是示出图5A、图6A、图7A和图8A中所示的防翘曲凹槽和增强支撑件的延伸方向的俯视图。
图9到图13是示出根据本公开的其它实施方式的具有三维结构的半导体装置的截面图。
图14是在芯片级结构上示出根据本公开的实施方式的第一防翘曲焊盘的设置的俯视图。
图15A是示出根据本公开的又一实施方式的具有三维结构的半导体装置的截面图。
图15B是示出图15A所示的防翘曲金属肋部的延伸方向的视图。
图16是示出根据本公开的另一实施方式的具有三维结构的半导体装置的截面图。
具体实施方式
本公开的优点和特征以及实现它们的方法将从以下示例性实施方式的描述中变得显而易见,并且将参照附图的描述。然而,本公开不限于这里公开的示例性实施方式,而是可以以各种不同的方式来实现。本公开的示例性实施方式将本公开的范围传达给本领域技术人员。
因为在附图中给出的描述本公开的实施方式的数值、尺寸、比例、角度、元件数量仅仅是说明性的,所以本公开不限于所示内容。在整个说明书中,相同的附图标记表示相同的组件。在描述本公开时,当确定相关技术的详细描述可能使本发明的要点或清晰性变得模糊时,将省略其详细描述。应当理解,除非另外特别说明,否则在说明书和权利要求书中使用的术语“包括”,“具有”、“包含”等不应当被解释为限于其后列出的手段。当提及单数名词时使用不定冠词或定冠词(例如,“一”、“一个”或“该”)时,除非另外特别说明,否则该冠词可以包括该名词的复数。
在解释本公开的实施方式中的元件时,即使在没有明确声明的情况下,它们也应被解释为包括误差范围。
此外,在描述本公开的组件时,可以使用诸如第一、第二、A、B、(a)和(b)的术语。这些术语仅用于将一个组件与另一组件区分的目的,并且不限制组件的实质、顺序、次序或数量。此外,本公开的实施方式中的组件不受这些术语的限制。这些术语仅用于区分一个组件和另一个组件。因此,如本文所用,第一组件可以是在本公开的技术精神内的第二组件。
如果组件被描述为“连接”、“联接”或“链接”到另一组件,则这可以意味着该组件不仅直接“连接”、“联接”或“链接”,而且还经由第三组件间接“连接”、“联接”或“链接”。在描述位置关系时,诸如“元件B上的元件A”、“元件B上方的元件A”、“元件B下方的元件A”和“元件B旁边的元件A”,除非明确使用术语“直接”或“紧接”,否则一个或更多个其它元件可以被设置在元件A和元件B之间。
本公开的各个示例性实施方式的特征可以部分地或全部地联接、组合或分离。技术上各种交互和操作是可能的。可以单独地或组合地实践各个示例性实施方式。
在下文中,将参照附图详细描述本公开的实施方式的各个示例。
图1是示出根据本公开的实施方式的具有三维结构的半导体装置的截面图。
参照图1,根据本公开的实施方式的具有三维结构的半导体装置可以包括彼此接合的第一晶圆W1和第二晶圆W2。为了便于理解本公开的实施方式,在本说明书中用于参考的截面图示出第一晶圆W1和第二晶圆W2是分离的。然而,应当理解,第一晶圆W1和第二晶圆W2实际上彼此接合。
第一晶圆W1可以包括第一基板10,限定在第一基板10下方的存储器单元阵列MCA以及限定在第一基板10之下以覆盖存储器单元阵列MCA的介电层30。存储器单元阵列MCA可以具有其中多个存储器单元三维层叠的结构。例如,存储器单元阵列MCA可以包括交替层叠在源极板11之下的多个电极层22和多个层间介电层24,以及穿过多个电极层22和多个层间介电层24的垂直沟道CH。
电极层22可以包括至少一条源极选择线、至少一条漏极选择线和多条字线。垂直沟道CH可以联接至位线BL。至少一个源极选择晶体管、多个存储器单元及至少一个漏极选择晶体管可以在垂直方向VD上沿一个垂直沟道CH设置,从而构成一个单元串。垂直方向VD表示从第一基板10的顶表面垂直突出的方向。可以通过位线BL和字线来访问每个存储器单元。尽管本实施方式公开了三维层叠的存储器单元作为示例,但是应当注意,本公开的范围不限于此。
第二晶圆W2可以包括第二基板40、限定在第二基板40上的逻辑电路LOGIC以及限定在第二基板40上以覆盖逻辑电路LOGIC的介电层50。逻辑电路LOGIC可以用于控制存储器单元阵列MCA。
第一晶圆W1可以在其一个表面S1上包括电联接至存储器单元阵列MCA的多个第一接合焊盘PAD1。第二晶圆W2可以在其一个表面S2上包括电联接至逻辑电路LOGIC的多个第二接合焊盘PAD2。当第一接合焊盘PAD1和第二接合焊盘PAD2彼此接合时,第一晶圆W1的存储器单元阵列MCA和第二晶圆W2的逻辑电路LOGIC可以电联接。
当从上述一个表面S1蚀刻介电层30达预定深度时,可以形成多个防翘曲凹槽(anti-warpage groove)RG。多个防翘曲凹槽RG可以用于分散或减轻应力,从而抑制第一晶圆W1的翘曲。
介电层30的其中形成有多个防翘曲凹槽RG的表面部分30A可以由比介电层30的内部部分30B具有更高的硬度(hardness)的介电材料制成。虽然未示出,但是介电层30可以包括在用于形成防翘曲凹槽RG的蚀刻工艺期间用作蚀刻停止件的蚀刻停止层,并且可以通过改变蚀刻停止层的垂直位置来调整防翘曲凹槽RG的深度。
介电层50可以包括在垂直方向VD上从第二晶圆W2的上述一个表面S2突出到预定高度的突出部,以形成与第一晶圆W1的多个防翘曲凹槽RG相对应的多个防翘曲肋部(anti-warpage rib)RR。多个防翘曲肋部RR可以用于增加第二晶圆W2的刚性,从而抑制第二晶圆W2的翘曲。
介电层50的从其形成多个防翘曲肋部RR的表面部分50A可以由比介电层50的内部部分50B具有更高硬度的介电材料制成。虽然未示出,但是可以通过经由蚀刻工艺图案化介电层50来形成多个防翘曲肋部RR。虽然未示出,但是介电层50可以包括在用于形成防翘曲肋部RR的蚀刻工艺期间用作蚀刻停止件的蚀刻停止层,并且可以通过改变蚀刻停止层的垂直位置来调整防翘曲肋部RR的高度。
虽然图1示出第一晶圆W1是包括存储器单元阵列MCA的单元晶圆,并且第二晶圆W2是包括用于控制存储器单元阵列MCA的逻辑电路LOGIC的逻辑晶圆,但是应当注意,本公开的技术精神不限于此。
在下文中,并且在附图中,平行于第一基板10的顶表面并且彼此相交的两个方向分别被定义为第一方向FD和第二方向SD。例如,第一方向FD可以对应于字线的延伸方向,并且第二方向SD可以对应于位线的延伸方向。第一方向FD和第二方向SD可以基本上彼此垂直相交。在附图中,由箭头指示的方向和与其相反的方向表示相同的方向。
图2是示出防翘曲凹槽的设置的俯视图。
参照图2,第一晶圆W1可以包括在第一方向FD和第二方向SD上排布的多个单位区域UA。单位区域UA可以包括例如以棋盘图案在第一方向FD和第二方向SD上交替地设置的多个第一单位区域UA1和多个第二单位区域UA2。
具有线形或条形形状的多个防翘曲凹槽RG可以被布置(laid out)在第一单位区域UA1和第二单位区域UA2中的每一个中。
第一单位区域UA1中的防翘曲凹槽RG的延伸方向和第二单位区域UA2中的防翘曲凹槽RG的延伸方向可以彼此不同。例如,在第一方向上FD延伸的防翘曲凹槽RG可以被布置在第一单位区域UA1中,并且在第二方向SD上延伸的防翘曲凹槽RG可以被布置在第二单位区域UA2中。因为防翘曲凹槽RG在不同方向上延伸,所以可以避免并且防止在制造工艺中在第一方向FD和第二方向SD上引起的固有应力集中在在任何一个方向上。
在一个实施方式中,包括在第一晶圆W1中的第一单位区域UA1的数量和包括在第一晶圆W1中的第二单位区域UA2的数量可以相同,并且包括在第一晶圆W1中的第一单位区域UA1的面积之和与包括在第一晶圆W1中的第二单位区域UA2的面积之和可以基本相同。
第二晶圆W2(见图1)的防翘曲肋部RR(见图1)与防翘曲凹槽RG具有基本相同的布局结构。因此,以下将不单独描述防翘曲肋部RR的布局结构。
图3A至图3C是示出配置单位区域的方法的俯视图。
参照图3A,第一晶圆W1可以包括被设置为彼此分离的多个芯片区域CHIP,在第一方向FD和第二方向SD上延伸的划片道(scribe lane)SL插置于所述多个芯片区域CHIP之间。划片道SL可以用作用于在分割工艺期间将芯片区域CHIP彼此分离的分离线。图3A示出了以芯片区域CHIP为单位配置的单位区域UA。
在三维存储器中,芯片区域CHIP在第一方向FD和第二方向SD上的长度之间的不对称性可能由于增加存储器单元的层叠数量的设计改变而增大。这种不对称性的增大可能减小由防翘曲凹槽RG提供的应力分散效果,从而导致在第一方向FD上的应力与在第二方向SD上的应力之间的不平衡。因此,需要减小单位区域UA在第一方向FD和第二方向SD上的长度之差。优选地,单位区域UA在第一方向FD和第二方向SD上的长度应当相同。也就是说,单位区域UA应该具有正方形或基本上正方形的结构。
如图3B所示,为了减小单位区域UA在第一方向FD和第二方向SD上的长度之差,每个芯片区域CHIP可以被划分为形成多个单位区域UA。例如,在长度L1具有大约是长度L2的两倍的尺寸的情况下,每个芯片区域CHIP可以在第一方向FD上被划分为两个以在每个芯片区域CHIP中形成两个单位区域UA。
如图3C所示,多个相邻芯片区域CHIP可以被分组为形成一个单位区域UA。例如,在长度L1具有大约是长度L2的三倍的尺寸的情况下,在第二方向SD上连续设置的三个芯片区域CHIP可以被分组为形成一个单位区域UA。
图4A是示出根据本公开的另一实施方式的具有三维结构的半导体装置的截面图,并且图4B是示出图4A的防翘曲凹槽和第一防翘曲焊盘(anti-warpage pad)的延伸方向的俯视图。
参照图4A,第一防翘曲焊盘DPAD1可以被限定在第一晶圆W1的一个表面S1上。第一防翘曲焊盘DPAD1可以用于抑制第一晶圆W1的翘曲。
第一防翘曲焊盘DPAD1是对存储器单元阵列MCA和逻辑电路LOGIC的操作不施加任何影响的虚设图案。第一防翘曲焊盘DPAD1可以与存储器单元阵列MCA和逻辑电路LOGIC电隔离。
接合至第一防翘曲焊盘DPAD1的第二防翘曲焊盘DPAD2可以被限定在第二晶圆W2的一个表面S2上。第二防翘曲焊盘DPAD2可以用于抑制第二晶圆W2的翘曲。
第二防翘曲焊盘DPAD2是对存储器单元阵列MCA和逻辑电路LOGIC的操作不施加任何影响的虚设图案。第二防翘曲焊盘DPAD2可以与存储器单元阵列MCA和逻辑电路LOGIC电隔离。
第一防翘曲焊盘DPAD1和第二防翘曲焊盘DPAD2可以由硬度高于第一接合焊盘PAD1和第二接合焊盘PAD2的导电材料制成。例如,第一接合焊盘PAD1和第二接合焊盘PAD2可以由铜(Cu)制成,并且第一防翘曲焊盘DPAD1和第二防翘曲焊盘DPAD2可以由钨(W)制成。
为了简化图示,图4A中仅示出了一个第一防翘曲焊盘DPAD1和一个第二防翘曲焊盘DPAD2。然而,应当理解,在本公开所设想的实施方式中提供了多个第一防翘曲焊盘DPAD1和多个第二防翘曲焊盘DPAD2。
参照图4B,多个第一防翘曲焊盘DPAD1可以被布置在第一晶圆W1的第一单位区域UA1和第二单位区域UA2的每一个中。
每个第一防翘曲焊盘DPAD1可以具有沿特定方向延伸的条形或线形形状。在第一单位区域UA1中布置的第一防翘曲焊盘DPAD1的延伸方向和在第二单位区域UA2中布置的第一防翘曲焊盘DPAD1的延伸方向可以彼此不同。例如,在第一方向FD上延伸的第一防翘曲焊盘DPAD1可以被布置在第一单位区域UA1中,并且在第二方向SD上延伸的第一防翘曲焊盘DPAD1可以被布置在第二单位区域UA2中。这种布局分散了在第一方向FD上引起的应力和在第二方向SD上引起的应力,并且抑制或减小了应力被集中在任何一个方向上。
在每个单位区域UA中,第一防翘曲焊盘DPAD1的延伸方向可以与防翘曲凹槽RG的延伸方向相同。例如,在第一单位区域UA1中,防翘曲凹槽RG的延伸方向和第一防翘曲焊盘DPAD1的延伸方向可以相同(例如,第一方向FD)。在第二单位区域UA2中,防翘曲凹槽RG的延伸方向和第一防翘曲焊盘DPAD1的延伸方向可以相同(例如,第二方向SD)。
图5A、图6A、图7A和图8A是示出根据本公开的其它实施方式的具有三维结构的半导体装置的截面图,并且图5B、图6B、图7B和图8B是示出图5A至图8A中所示出的防翘曲凹槽和增强支撑件(reinforcing support)的延伸方向的俯视图。
参照图5A,第一基板10可以具有被设置为面向存储器单元阵列MCA的前表面和背离前表面的后表面。多个凹槽R可以形成在第一基板10的后表面上,并且增强支撑件SP1可以填充在多个凹槽R中。增强支撑件SP1用于抑制第一晶圆W1的翘曲,并且可以由比第一基板10具有更高的硬度的材料制成。
参照图5B,多个增强支撑件SP1可以被布置在第一单位区域UA1和第二单位区域UA2中的每一个中。每个增强支撑件SP1可以具有在特定方向上延伸的条形或线形形状。
布置在第一单位区域UA1中的增强支撑件SP1的延伸方向和布置在第二单位区域UA2中的增强支撑件SP1的延伸方向可以彼此不同。例如,在第一方向FD上延伸的增强支撑件SP1可以被布置在第一单位区域UA1中,并且在第二方向SD上延伸的增强支撑件SP1可以被布置在第二单位区域UA2中。
在每个单位区域UA中,增强支撑件SP1的延伸方向可以与防翘曲凹槽RG的延伸方向相同。例如,在第一单位区域UA1中,防翘曲凹槽RG的延伸方向和增强支撑件SP1的延伸方向可以相同(例如,第一方向FD)。在第二单位区域UA2中,防翘曲凹槽RG的延伸方向和增强支撑件SP1的延伸方向可以相同(例如,第二方向SD)。
参照图6A和图6B,在每个单位区域UA中,增强支撑件SP1’的延伸方向可以与防翘曲凹槽RG的延伸方向不同。例如,在第一单位区域UA1中,防翘曲凹槽RG的延伸方向可以是第一方向FD,并且增强支撑件SP1’的延伸方向可以是第二方向SD。在第二单位区域UA2中,防翘曲凹槽RG的延伸方向可以是第二方向SD,并且增强支撑件SP1’的延伸方向可以是第一方向FD。
参照图7A,多个凹槽R’可以被形成在第一基板10的前表面上,并且增强支撑件SP2可以被填充在多个凹槽R’中。增强支撑件SP2用于抑制第一晶圆W1的翘曲,并且可以由比第一基板10具有更高的硬度的材料制成。
参照图7B,多个增强支撑件SP2可以被布置在第一单位区域UA1和第二单位区域UA2中的每一个中。与图5A中的增强支撑件SP1类似,增强支撑件SP2也可以具有在特定方向上延伸的条形或线形形状。
布置在第一单位区域UA1中的增强支撑件SP2的延伸方向和布置在第二单位区域UA2中的增强支撑件SP2的延伸方向可以彼此不同。例如,布置在第一单位区域UA1中的增强支撑件SP2的延伸方向可以是第一方向FD,并且布置在第二单位区域UA2中的增强支撑件SP2的延伸方向可以是第二方向SD。
在每个单位区域UA中,增强支撑件SP2的延伸方向可以与防翘曲凹槽RG的延伸方向相同。例如,在第一单位区域UA1中,防翘曲凹槽RG的延伸方向和增强支撑件SP2的延伸方向可以相同(例如,第一方向FD)。在第二单位区域UA2中,防翘曲凹槽RG的延伸方向和增强支撑件SP2的延伸方向可以相同(例如,第二方向SD)。
参照图8A和图8B,在每个单位区域UA中,增强支撑件SP2’的延伸方向可以与防翘曲凹槽RG的延伸方向不同。例如,在第一单位区域UA1中,防翘曲凹槽RG的延伸方向可以是第一方向FD,并且增强支撑件SP2’的延伸方向可以是第二方向SD。在第二单位区域UA2中,防翘曲凹槽RG的延伸方向可以是第二方向SD,并且增强支撑件SP2’的延伸方向可以是第一方向FD。
图9至图13是示出根据本公开的其它实施方式的具有三维结构的半导体装置的截面图。
参照图9,第一防翘曲焊盘DPAD1可以被限定在第一晶圆W1的一个表面S1上,并且第二防翘曲焊盘DPAD2可以被限定在第二晶圆W2的一个表面S2上。当与上面参照图4A和图4B所述的实施方式相比时,图9所示的实施方式具有省略了防翘曲凹槽(图4A的RG)和防翘曲肋部(图4A的RR)的结构。
参照图10,第一晶圆W1还可以包括围绕第一接合焊盘PAD1的侧表面和底表面的导电增强图案CS1。导电增强图案CS1可以由比第一接合焊盘PAD1具有更高硬度的导电材料制成。
导电增强图案CS1可以与第一防翘曲焊盘DPAD1在相同的工艺步骤中形成。例如,可以在第一晶圆W1的一个表面S1上形成第一沟槽和具有比第一沟槽的开口宽度大的开口宽度的第二沟槽,并且可以在第一沟槽和第二沟槽中形成导电材料。由于第一沟槽和第二沟槽之间的开口宽度的差异,当具有较小开口宽度的第一沟槽完全由导电材料填充时,导电材料可以仅在具有较大开口宽度的第二沟槽的侧壁和底面上成线状地(linearly)形成,或者形成为层。填充在第一沟槽中的导电材料可以构成第一防翘曲焊盘DPAD1,并且形成在第二沟槽的侧壁和底表面上的导电材料层可以构成导电增强图案CS1。在形成导电增强图案CS1之后,在第二沟槽中形成第一接合焊盘PAD1。
参照图11,第一晶圆W1还可以包括覆盖第一接合焊盘PAD1的底表面的导电增强图案CS2。导电增强图案CS2可以由比第一接合焊盘PAD1的具有更高硬度的导电材料制成。
导电增强图案CS2可以与第一防翘曲焊盘DPAD1在相同的工艺步骤中形成。例如,在如上文参照图10所述在第二沟槽中形成导电增强图案CS1之后,可以通过去除形成在第二沟槽的侧壁上的导电增强图案CS1来形成导电增强图案CS2。结果,导电增强图案CS2是导电增强图案CS1的保留在第二沟槽的底表面上的部分。
参照图12,为了增加第一晶圆W1中的第一防翘曲焊盘DPAD1的翘曲抑制效果,可以将第一防翘曲焊盘DPAD1形成为具有大于第一接合焊盘PAD1的厚度的厚度。例如,如果第一接合焊盘PAD1的厚度是T1,则第一防翘曲焊盘DPAD1的厚度可以是大于T1的T2。
此外,如图13所示,第一防翘曲焊盘DPAD1可以根据位置而具有不同的厚度。例如,在垂直方向VD上与位线BL交叠的第一防翘曲焊盘DPAD1可以具有厚度T2a,并且在垂直方向VD上不与位线BL交叠的第一防翘曲焊盘DPAD1可以具有大于T2a的厚度T2b。
图14是在芯片级结构上示出根据本公开的实施方式的第一防翘曲焊盘的设置的俯视图。
参照图14,第一晶圆W1的芯片区域CHIP可以包括第一联接区域OFC和第二联接区域SR。联接至位线的第一接合焊盘PAD1可以布置在第一联接区域OFC中,并且联接至字线的第一接合焊盘PAD1可以布置在第二联接区域SR中。
第一联接区域OFC和第二联接区域SR之外的区域可以被定义为开放区域(openarea)。第一防翘曲焊盘DPAD1可以被设置在开放区域中。第一防翘曲焊盘DPAD1的长度可以考虑晶圆接合期间的焊盘对准裕度(alignment margin)来确定。
图15A是示出根据本公开的又一实施方式的具有三维结构的半导体装置的截面图,并且图15B是示出图15A中所示的防翘曲金属肋部的延伸方向的俯视图。
参照图15A,第一晶圆W1可以包括多个防翘曲金属肋部MR。防翘曲金属肋部MR用于防止第一晶圆W1的翘曲,并且可以被设置在介电层30中并且可以与存储器单元阵列MCA电隔离。
参照图15B,多个防翘曲金属肋部MR可以被布置在第一单位区域UA1和第二单位区域UA2中的每一个中。每个防翘曲金属肋部MR可以具有沿特定方向延伸的条形或线形形状。布置在第一单位区域UA1中的防翘曲金属肋部MR的延伸方向和布置在第二单位区域UA2中的防翘曲金属肋部MR的延伸方向可以彼此不同。例如,布置在第一单位区域UA1中的防翘曲金属肋部MR的延伸方向可以是第一方向FD,并且布置在第二单位区域UA2中的防翘曲金属肋部MR的延伸方向可以是第二方向SD。
返回参照图15A,防翘曲金属肋部MR可以通过联接布线IW彼此电联接。
防翘曲金属肋部MR可以电联接至限定在第一晶圆W1的一个表面S1上的第一防翘曲焊盘DPAD1。
第二晶圆W2可以在其一个表面S2上包括接合至第一防翘曲焊盘DPAD1的第二防翘曲焊盘DPAD2。尽管未示出,但是第二防翘曲焊盘DPAD2可以电联接至逻辑电路LOGIC,并且可以被提供有来自逻辑电路LOGIC的屏蔽电压(shield voltage)。提供给第二防翘曲焊盘DPAD2的屏蔽电压可以通过第一防翘曲焊盘DPAD1传送至防翘曲金属肋部MR和联接布线IW。防翘曲金属肋部MR和联接布线IW可以用于抑制第一晶圆W1的存储器单元阵列MCA与第二晶圆W2的逻辑电路LOGIC之间的干扰。
图16是示出根据本公开的另一实施方式的具有三维结构的半导体装置的截面图。
参照图16,可以在介电层30中的相邻防翘曲金属肋部MR之间限定气隙AIR。气隙AIR可以具有在与防翘曲金属肋部MR的延伸方向相同的方向上延伸的条形或线形形状。气隙AIR可以用于分散或减轻应力,从而抑制第一晶圆W1的翘曲。
气隙AIR的介电常数为小于介电层30的介电常数(ε>1)的ε0(=1)。因此,当与没有气隙AIR的情况相比时,在气隙AIR形成在介电层30中的情况下,存储器单元阵列MCA与逻辑电路LOGIC之间的耦合电容的值减小,并且因此,由于耦合电容引起的存储器单元阵列MCA与逻辑电路LOGIC之间的干扰减小。
本公开的上述示例性实施方式不仅可以通过设备和方法来实现,还可以通过实现与本公开的示例性实施方式的配置相对应的功能的程序或通过其上记录有该程序的记录介质来实现,并且可以由本领域普通技术人员根据前述示例性实施方式的描述来容易地实现。
尽管出于说明的目的描述了本公开的示例性实施方式,但是本领域技术人员将理解,在不脱离本公开的范围和精神的情况下,各种修改、添加和替换是可能的。因此,以上和附图中公开的实施方式应被认为仅是描述性的,而不是用于限制技术范围。本公开的技术范围不受实施方式和附图的限制。本公开的精神和范围应当结合所附权利要求来解释,并且包括落入所附权利要求的范围内的所有等同物。
相关申请的交叉引用
本申请要求于2020年9月2日向韩国知识产权局提交的韩国专利申请第10-2020-0111624号的优先权,其全部内容通过引用结合于此。
Claims (20)
1.一种具有三维结构的半导体装置,该半导体装置包括:
第一晶圆,所述第一晶圆包括在所述第一晶圆的一个表面上的第一接合焊盘;
第二晶圆,所述第二晶圆包括在所述第二晶圆的接合至所述第一晶圆的所述一个表面的一个表面上的第二接合焊盘,所述第二接合焊盘接合至所述第一接合焊盘;
多个防翘曲凹槽,所述多个防翘曲凹槽在所述第一晶圆的所述一个表面上,并且被布置为条形形状;以及
多个防翘曲肋部,所述多个防翘曲肋部在所述第二晶圆的所述一个表面上,并且分别联接至所述多个防翘曲凹槽,并且所述多个防翘曲肋部被布置为条形形状。
2.根据权利要求1所述的半导体装置,其中,
所述第一晶圆包括在第一方向和第二方向上交替设置的多个第一单位区域和多个第二单位区域,
所述第一方向和所述第二方向平行于所述第一晶圆的所述一个表面并且彼此相交,并且
设置在所述多个第一单位区域中的所述防翘曲凹槽的延伸方向与设置在所述多个第二单位区域中的所述防翘曲凹槽的延伸方向彼此不同。
3.根据权利要求2所述的半导体装置,其中,所述多个第一单位区域的面积之和与所述多个第二单位区域的面积之和相同。
4.根据权利要求2所述的半导体装置,其中,所述多个第一单位区域中的每一个和所述多个第二单位区域中的每一个具有正方形形状。
5.根据权利要求2所述的半导体装置,其中,所述第一晶圆包括:
第一基板;
存储器单元阵列,所述存储器单元阵列设置在所述第一基板上方,并且通过位线和字线被访问;以及
第一介电层,所述第一介电层设置在所述第一基板上以覆盖所述存储器单元阵列,并且在所述第一介电层的表面部分上具有所述多个防翘曲凹槽,
其中,所述第一介电层的所述表面部分由具有大于所述第一介电层的内部部分的硬度的硬度的介电材料制成。
6.根据权利要求5所述的半导体装置,其中,
所述字线在所述第一方向上延伸,并且所述位线在所述第二方向上延伸,并且
设置在所述多个第一单位区域中的所述防翘曲凹槽的延伸方向是所述第一方向,并且设置在所述多个第二单位区域中的所述防翘曲凹槽的延伸方向是所述第二方向。
7.根据权利要求5所述的半导体装置,其中,所述第二晶圆包括:
第二基板;
逻辑电路,所述逻辑电路设置在所述第二基板上并且被配置为控制所述存储器单元阵列;以及
第二介电层,所述第二介电层被限定在所述第二基板上以覆盖所述逻辑电路,并且在所述第二介电层的表面部分上具有所述多个防翘曲肋部,
其中,所述第二介电层的所述表面部分由具有大于所述第二介电层的内部部分的硬度的硬度的介电材料制成。
8.根据权利要求5所述的半导体装置,该半导体装置还包括:
多个增强支撑件,所述多个增强支撑件设置在多个凹槽中,所述多个凹槽被限定在所述第一基板的面向所述存储器单元阵列的前表面和所述第一基板的背离所述前表面的后表面中的至少一个上,并且所述多个增强支撑件被布置为条形形状。
9.根据权利要求8所述的半导体装置,其中,设置在所述第一单位区域中的所述增强支撑件的延伸方向和设置在所述第二单位区域中的所述增强支撑件的延伸方向彼此不同。
10.根据权利要求8所述的半导体装置,其中,所述增强支撑件包括硬度高于所述第一基板的硬度的材料。
11.一种具有三维结构的半导体装置,该半导体装置包括:
第一晶圆,所述第一晶圆包括在所述第一晶圆的一个表面上的第一接合焊盘;
第二晶圆,所述第二晶圆包括在所述第二晶圆的接合至所述第一晶圆的所述一个表面的一个表面上的第二接合焊盘,所述第二接合焊盘接合至所述第一接合焊盘;
多个第一防翘曲焊盘,所述多个第一防翘曲焊盘在所述第一晶圆的所述一个表面上,并且被布置为条形形状;以及
多个第二防翘曲焊盘,所述多个第二防翘曲焊盘在所述第二晶圆的所述一个表面上并且分别接合至所述多个第一防翘曲焊盘,并且所述多个第二防翘曲焊盘被布置为条形形状。
12.根据权利要求11所述的半导体装置,其中,
所述第一晶圆包括在第一方向和第二方向上交替设置的多个第一单位区域和多个第二单位区域,
所述第一方向和所述第二方向平行于所述第一晶圆的所述一个表面并且彼此相交,并且
设置在所述多个第一单位区域中的所述第一防翘曲焊盘的延伸方向与设置在所述多个第二单位区域中的所述第一防翘曲焊盘的延伸方向彼此不同。
13.根据权利要求11所述的半导体装置,该半导体装置还包括:
在所述第一接合焊盘的侧表面和底表面上的导电增强图案。
14.根据权利要求11所述的半导体装置,该半导体装置还包括:
设置在所述第一接合焊盘的底表面上的导电增强图案。
15.根据权利要求11所述的半导体装置,其中,所述多个第一防翘曲焊盘中的至少一个具有大于所述第一接合焊盘的厚度的厚度。
16.根据权利要求15所述的半导体装置,其中,所述多个第一防翘曲焊盘包括硬度大于所述第一接合焊盘的硬度的材料。
17.一种具有三维结构的半导体装置,该半导体装置包括:
第一晶圆,所述第一晶圆包括在所述第一晶圆的一个表面上的第一接合焊盘;
第二晶圆,所述第二晶圆包括在所述第二晶圆的接合至所述第一晶圆的所述一个表面的一个表面上的第二接合焊盘,所述第二接合焊盘接合至所述第一接合焊盘;以及
多个防翘曲金属肋部,所述多个防翘曲金属肋部被限定在所述第一晶圆中,并且被布置为条形形状。
18.根据权利要求17所述的半导体装置,该半导体装置还包括:
联接布线,所述联接布线联接所述多个防翘曲金属肋部中的相邻防翘曲金属肋部,
其中,屏蔽电压被施加到所述多个防翘曲金属肋部和所述联接布线。
19.根据权利要求17所述的半导体装置,其中,所述第一晶圆包括:
介电层,所述介电层围绕所述多个防翘曲金属肋部;以及
气隙,所述气隙被限定在所述介电层中的所述多个防翘曲金属肋部之间。
20.根据权利要求17所述的半导体装置,其中,
所述第一晶圆包括在第一方向和第二方向上交替设置的多个第一单位区域和多个第二单位区域,
所述第一方向和所述第二方向平行于所述第一晶圆的所述一个表面并且彼此相交,并且
设置在所述多个第一单位区域中的所述防翘曲金属肋部的延伸方向与设置在所述多个第二单位区域中的所述防翘曲金属肋部的延伸方向彼此不同。
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Family Cites Families (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100997524B1 (ko) * | 2008-10-28 | 2010-11-30 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 및 그 제조방법 |
KR20120048841A (ko) | 2010-11-08 | 2012-05-16 | 에스케이하이닉스 주식회사 | 적층 반도체 패키지 |
US8630156B2 (en) * | 2011-02-04 | 2014-01-14 | Tdk Corporation | Optical recording and reading method, optical recording and reading apparatus, optical recording medium, and method for producing an optical recording medium |
JP5853389B2 (ja) * | 2011-03-28 | 2016-02-09 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法。 |
KR20130123722A (ko) | 2012-05-03 | 2013-11-13 | 에스케이하이닉스 주식회사 | 반도체 칩 및 이를 갖는 적층 반도체 패키지 |
KR20140081028A (ko) * | 2012-12-21 | 2014-07-01 | 삼성전자주식회사 | 반도체 발광소자 및 반도체 발광소자 제조방법 |
WO2015040798A1 (ja) * | 2013-09-20 | 2015-03-26 | パナソニックIpマネジメント株式会社 | 半導体装置及びその製造方法 |
JPWO2016117711A1 (ja) * | 2015-01-23 | 2017-11-02 | 古河電気工業株式会社 | 金属部材と樹脂モールドとの複合体および樹脂モールドとの複合体形成用金属部材 |
JP2016146449A (ja) * | 2015-02-09 | 2016-08-12 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP2016174101A (ja) * | 2015-03-17 | 2016-09-29 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN111883501A (zh) * | 2015-05-18 | 2020-11-03 | 索尼公司 | 半导体装置和成像装置 |
EP3306719B1 (en) * | 2015-05-25 | 2019-04-03 | Nissan Motor Co., Ltd. | Solid oxide fuel cell |
KR102035378B1 (ko) * | 2015-06-08 | 2019-11-18 | 주식회사 엘지화학 | 금속배선층이 형성된 적층체 및 이를 제조하는 방법 |
KR102333081B1 (ko) * | 2015-06-18 | 2021-12-01 | 삼성전기주식회사 | 인쇄회로기판 |
JP2017017238A (ja) * | 2015-07-03 | 2017-01-19 | 株式会社ジェイデバイス | 半導体装置及びその製造方法 |
US11342189B2 (en) * | 2015-09-17 | 2022-05-24 | Semiconductor Components Industries, Llc | Semiconductor packages with die including cavities and related methods |
US20200258750A1 (en) * | 2017-08-17 | 2020-08-13 | Semiconductor Components Industries, Llc | Die support structures and related methods |
JP6842234B2 (ja) * | 2015-10-13 | 2021-03-17 | ローム株式会社 | 光半導体装置の製造方法および光半導体装置 |
KR102522322B1 (ko) * | 2016-03-24 | 2023-04-19 | 삼성전자주식회사 | 반도체 패키지 |
US20170373211A1 (en) * | 2016-06-24 | 2017-12-28 | Merlin Solar Technologies, Inc. | Cell-to-cell interconnect |
JP6783614B2 (ja) * | 2016-10-11 | 2020-11-11 | 株式会社ディスコ | 配線基板の製造方法 |
US20180130768A1 (en) * | 2016-11-09 | 2018-05-10 | Unisem (M) Berhad | Substrate Based Fan-Out Wafer Level Packaging |
US10153218B2 (en) * | 2016-11-29 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
JP2018113414A (ja) * | 2017-01-13 | 2018-07-19 | 新光電気工業株式会社 | 半導体装置とその製造方法 |
TWI675402B (zh) * | 2017-02-17 | 2019-10-21 | 美商美國亞德諾半導體公司 | 轉印方法及平行轉印方法 |
US10157887B2 (en) * | 2017-03-09 | 2018-12-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US10083917B1 (en) * | 2017-03-22 | 2018-09-25 | Toyota Motor Engineering & Manufacturing North America, Inc. | Power electronics assemblies and vehicles incorporating the same |
US10879194B2 (en) * | 2017-05-25 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device package and method of manufacturing the same |
US11404276B2 (en) * | 2017-08-17 | 2022-08-02 | Semiconductor Components Industries, Llc | Semiconductor packages with thin die and related methods |
US20210035807A1 (en) * | 2017-08-17 | 2021-02-04 | Semiconductor Components Industries, Llc | Semiconductor package stress balance structures and related methods |
US10964677B2 (en) * | 2017-10-06 | 2021-03-30 | Intel Corporation | Electronic packages with stacked sitffeners and methods of assembling same |
CN111316408B (zh) * | 2017-10-30 | 2023-07-18 | 三菱电机株式会社 | 电力用半导体装置以及电力用半导体装置的制造方法 |
US10636749B2 (en) * | 2017-11-14 | 2020-04-28 | Intel Corporation | Semiconductor package substrate support structures for ball-grid array cavities, and methods of assembling same |
US10312201B1 (en) * | 2017-11-30 | 2019-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Seal ring for hybrid-bond |
DE102018100958B3 (de) * | 2018-01-17 | 2019-03-14 | Infineon Technologies Ag | Verfahren zum bilden einer chipanordnung, chipanordnung, verfahren zum bilden eines chipbausteins und chipbaustein |
US11538764B2 (en) * | 2018-01-31 | 2022-12-27 | The Regents Of The University Of California | Flexible and stretchable interconnects for flexible systems |
KR102388922B1 (ko) * | 2018-02-22 | 2022-04-21 | 삼성에스디아이 주식회사 | 이차 전지용 트레이 및 이를 성형하기 위한 지그 |
JP7056226B2 (ja) * | 2018-02-27 | 2022-04-19 | Tdk株式会社 | 回路モジュール |
US11037864B2 (en) * | 2018-02-28 | 2021-06-15 | Stmicroelectronics, Inc. | Lead frame for improving adhesive fillets on semiconductor die corners |
US10937743B2 (en) * | 2018-04-30 | 2021-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mixing organic materials into hybrid packages |
US10790254B2 (en) * | 2018-05-09 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure |
US10629592B2 (en) * | 2018-05-25 | 2020-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through silicon via design for stacking integrated circuits |
WO2020017579A1 (ja) * | 2018-07-18 | 2020-01-23 | クミ化成株式会社 | 射出成形用金型、および成形品の製造方法 |
US10867925B2 (en) * | 2018-07-19 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming chip package structure |
US10879144B2 (en) * | 2018-08-14 | 2020-12-29 | Texas Instruments Incorporated | Semiconductor package with multilayer mold |
CN110858576B (zh) * | 2018-08-24 | 2022-05-06 | 芯舟科技(厦门)有限公司 | 覆晶封装基板及其制法 |
JP7268035B2 (ja) * | 2018-08-29 | 2023-05-02 | ローム株式会社 | パッケージ構造、半導体装置およびパッケージ構造の形成方法 |
US10438863B1 (en) * | 2018-09-21 | 2019-10-08 | Xilinx, Inc. | Chip package assembly with surface mounted component protection |
JP7172368B2 (ja) * | 2018-09-27 | 2022-11-16 | セイコーエプソン株式会社 | 三次元造形装置、および、三次元造形物の製造方法 |
WO2020061976A1 (en) * | 2018-09-28 | 2020-04-02 | Intel Corporation | Moderated deformation of a vapor chamber to match a shape of a heat source |
KR102480631B1 (ko) | 2018-10-01 | 2022-12-26 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
JP7282500B2 (ja) * | 2018-10-19 | 2023-05-29 | キヤノン株式会社 | 半導体装置、機器、半導体装置の製造方法 |
US11476174B2 (en) * | 2018-10-31 | 2022-10-18 | Intel Corporation | Solder mask design for delamination prevention |
US10985199B2 (en) * | 2018-10-31 | 2021-04-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Image sensor having stress releasing structure and method of forming same |
CN111211059B (zh) * | 2018-11-22 | 2023-07-04 | 矽品精密工业股份有限公司 | 电子封装件及其制法与散热件 |
JP7273488B2 (ja) * | 2018-12-04 | 2023-05-15 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、及び電子機器 |
CN111312800B (zh) * | 2018-12-12 | 2023-03-28 | 联华电子股份有限公司 | 具有外延层的半导体结构及其制作方法 |
US11114406B2 (en) * | 2019-01-31 | 2021-09-07 | Sandisk Technologies Llc | Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip |
WO2020162142A1 (ja) * | 2019-02-05 | 2020-08-13 | ソニー株式会社 | 発光素子組立体、マルチビームレーザチップ組立体及び光造形装置、並びに、部材組立体及びその製造方法 |
US10658381B1 (en) | 2019-03-28 | 2020-05-19 | Sandisk Technologies Llc | Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same |
TW202038394A (zh) * | 2019-04-08 | 2020-10-16 | 力成科技股份有限公司 | 半導體封裝結構 |
CN110047911B (zh) * | 2019-04-22 | 2020-06-30 | 武汉新芯集成电路制造有限公司 | 一种半导体晶圆、键合结构及其键合方法 |
CN110600440B (zh) * | 2019-05-13 | 2021-12-14 | 华为技术有限公司 | 一种埋入式封装结构及其制备方法、终端 |
US11018120B2 (en) * | 2019-06-06 | 2021-05-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package with stress buffering layer and method for manufacturing the same |
CN113169083A (zh) * | 2019-06-20 | 2021-07-23 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
CN110429177A (zh) * | 2019-07-24 | 2019-11-08 | 武汉华星光电半导体显示技术有限公司 | 一种柔性oled显示面板及其制作方法 |
US20210320075A1 (en) * | 2019-07-26 | 2021-10-14 | Sandisk Technologies Llc | Bonded assembly containing bonding pads spaced apart by polymer material, and methods of forming the same |
TWI754997B (zh) * | 2019-07-31 | 2022-02-11 | 日商村田製作所股份有限公司 | 半導體裝置及高頻模組 |
KR102589686B1 (ko) * | 2019-08-12 | 2023-10-16 | 삼성전자주식회사 | 패키지 기판 및 이를 포함하는 반도체 패키지 |
TWI791881B (zh) * | 2019-08-16 | 2023-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其組合式基板與製法 |
US20210066208A1 (en) * | 2019-08-29 | 2021-03-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method of manufacturing the same |
US11164749B1 (en) * | 2019-09-16 | 2021-11-02 | Xilinx, Inc. | Warpage reduction |
TWI712135B (zh) * | 2019-09-16 | 2020-12-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US11289429B2 (en) * | 2019-10-07 | 2022-03-29 | Sandisk Technologies Llc | Three-dimensional memory die containing stress-compensating slit trench structures and methods for making the same |
KR20210041929A (ko) * | 2019-10-08 | 2021-04-16 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 |
US10879206B1 (en) * | 2019-10-16 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for forming the same |
US11302600B2 (en) * | 2019-12-18 | 2022-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
US11302652B2 (en) * | 2019-12-20 | 2022-04-12 | Texas Instruments Incorporated | Semiconductor package substrate with a smooth groove about a perimeter of a semiconductor die |
KR20210083429A (ko) * | 2019-12-26 | 2021-07-07 | 삼성전자주식회사 | 반도체 소자 |
US11282815B2 (en) * | 2020-01-14 | 2022-03-22 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices and electronic systems |
US20210280523A1 (en) * | 2020-03-04 | 2021-09-09 | Qualcomm Incorporated | Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods |
JP2021145053A (ja) * | 2020-03-12 | 2021-09-24 | キオクシア株式会社 | 半導体記憶装置 |
JP2021150574A (ja) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体装置 |
TW202143401A (zh) * | 2020-05-08 | 2021-11-16 | 力成科技股份有限公司 | 半導體封裝方法及其結構 |
US11276651B2 (en) * | 2020-05-18 | 2022-03-15 | Globalfoundries U.S. Inc. | IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structure |
US11764096B2 (en) * | 2020-07-08 | 2023-09-19 | Micron Technology, Inc. | Method for semiconductor die edge protection and semiconductor die separation |
US11222867B1 (en) * | 2020-07-09 | 2022-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package and manufacturing method thereof |
US11469186B2 (en) * | 2020-07-24 | 2022-10-11 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method for manufacturing the same |
US11502107B2 (en) * | 2020-08-19 | 2022-11-15 | Innolux Corporation | Crack stopper structure in electronic device |
-
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