JP6783614B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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- JP6783614B2 JP6783614B2 JP2016200273A JP2016200273A JP6783614B2 JP 6783614 B2 JP6783614 B2 JP 6783614B2 JP 2016200273 A JP2016200273 A JP 2016200273A JP 2016200273 A JP2016200273 A JP 2016200273A JP 6783614 B2 JP6783614 B2 JP 6783614B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000002184 metal Substances 0.000 claims description 109
- 229910052751 metal Inorganic materials 0.000 claims description 109
- 239000000758 substrate Substances 0.000 claims description 81
- 238000000034 method Methods 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 367
- 238000005498 polishing Methods 0.000 description 13
- 238000000227 grinding Methods 0.000 description 12
- 239000000126 substance Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000002390 adhesive tape Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000012779 reinforcing material Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 238000002679 ablation Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/043—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by using a moving tool for milling or cutting the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/26—Cleaning or polishing of the conductive pattern
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/48—After-treatment of electroplated surfaces
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0346—Deburring, rounding, bevelling or smoothing conductor edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Mechanical Engineering (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
本発明の第1実施形態にかかる配線基板の製造方法を図面に基づいて説明する。図1は、第1実施形態にかかる配線基板の製造方法により製造される配線基板を示す断面図である。図1に示す配線基板1は、半導体チップや各種電機部品を実装して搭載し、これらの電極と他の部品との導通を確保するインターポーザーやプリント配線基板といった再配線層を有する配線基板である。本実施形態において、配線基板1は、半導体チップを搭載して印刷配線基板に接続されて、半導体チップの電極と印刷配線基板の配線パターンとを予め定められたパターン通りに接続するインターポーザーである。配線基板1は、図1に示すように、コアとなるコア基板10と、コア基板10の表面10a及び裏面10bの双方に形成された再配線層である回路パターン層20とを備える。
次に、本発明の第2実施形態にかかる配線基板の製造方法について説明する。第2実施形態にかかる配線基板の製造方法は、図2に示す第一の除去工程ST5及び第二の除去工程ST6の手法が異なることを除き、第1実施形態にかかる配線基板の製造方法と同様である。以下、第2実施形態の第一の除去工程ST5及び第二の除去工程ST6について、図面に基づいて説明し、第一の除去工程ST5及び第二の除去工程ST6以外の説明は省略する。図11は、第2実施形態にかかる配線基板の製造方法における第一の除去工程ST5を実施する様子を示す説明図であり、図12は、第2実施形態にかかる配線基板の製造方法における第二の除去工程ST6を実施する様子を示す説明図である。
10 コア基板
10a 表面
10b 裏面
20 回路パターン層(再配線層)
21 第1回路パターン層
21a、22a、23a 絶縁層
21b、22b、23b 回路パターン
21c、22c、23c 配線層
22 第2回路パターン層
23 第3回路パターン層
30 バイト切削装置
31 バイト工具
32、41、52、61 チャックテーブル
32a、41a、52a、61a 保持面
33 バイトホイール
40 レーザー加工装置
42 レーザー光線照射部
50 研削装置
51 研削砥石
60 CMP装置
62 研磨ホイール
63 研磨パッド
L レーザー光線
M 金属
ML 金属層
R 溝
S シード層
Claims (4)
- 表面に再配線層を含む配線基板の製造方法であって、
コア基板に絶縁層を形成する絶縁層形成工程と、
該絶縁層に配線層となる溝を形成する溝形成工程と、
該溝形成工程において該溝が形成された該絶縁層の露出面に金属のシード層を形成するシード層形成工程と、
該シード層に配線層となる金属をめっき処理で電着させ該溝に金属を充填し金属層を形成する金属層形成工程と、
該金属層を該絶縁層の上端に至らない位置までバイト切削して除去する第一の除去工程と、
該第一の除去工程の後に、エッチング又はCMP処理により該絶縁層の上端を露出させて回路パターンを露出させるとともに露出面を平坦化する第二の除去工程と、を含む配線基板の製造方法。 - 表面に再配線層を含む配線基板の製造方法であって、
コア基板に絶縁層を形成する絶縁層形成工程と、
該絶縁層に配線層となる溝を形成する溝形成工程と、
該溝形成工程において該溝が形成された該絶縁層の露出面に金属のシード層を形成するシード層形成工程と、
該シード層に配線層となる金属をめっき処理で電着させ該溝に金属を充填し金属層を形成する金属層形成工程と、
該金属層を該絶縁層の上端までバイト切削して除去する第一の除去工程と、
該第一の除去工程の後に、エッチング又はCMP処理により回路パターンが露出した露出面を平坦化する第二の除去工程と、を含む配線基板の製造方法。 - 該コア基板の表裏面に前記請求項1または2の方法により回路パターンを形成する配線基板の製造方法。
- 前記第二の除去工程の後、前記平坦化された回路パターン上に絶縁層を形成する絶縁層形成工程と、前記溝形成工程と、前記シード層形成工程と、前記金属層形成工程と、前記第一の除去工程と、前記第二の除去工程と、を繰り返し回路パターンを積層する請求項1から3のいずれか一項に記載の配線基板の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016200273A JP6783614B2 (ja) | 2016-10-11 | 2016-10-11 | 配線基板の製造方法 |
TW106131121A TWI722241B (zh) | 2016-10-11 | 2017-09-12 | 配線基板的製造方法 |
KR1020170128061A KR20180040091A (ko) | 2016-10-11 | 2017-09-29 | 배선 기판의 제조 방법 |
CN201710928667.1A CN107920424B (zh) | 2016-10-11 | 2017-10-09 | 布线基板的制造方法 |
US15/727,843 US10874021B2 (en) | 2016-10-11 | 2017-10-09 | Manufacturing method for wiring board |
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JP2016200273A JP6783614B2 (ja) | 2016-10-11 | 2016-10-11 | 配線基板の製造方法 |
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JP2018064001A JP2018064001A (ja) | 2018-04-19 |
JP6783614B2 true JP6783614B2 (ja) | 2020-11-11 |
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US (1) | US10874021B2 (ja) |
JP (1) | JP6783614B2 (ja) |
KR (1) | KR20180040091A (ja) |
CN (1) | CN107920424B (ja) |
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WO2020188923A1 (ja) * | 2019-03-15 | 2020-09-24 | 京セラ株式会社 | 配線基板およびその製造方法 |
JP7306337B2 (ja) * | 2020-06-25 | 2023-07-11 | トヨタ自動車株式会社 | 配線基板の製造方法 |
KR20220029987A (ko) * | 2020-09-02 | 2022-03-10 | 에스케이하이닉스 주식회사 | 3차원 구조의 반도체 장치 |
CN112105143A (zh) * | 2020-10-15 | 2020-12-18 | 河南博美通电子科技有限公司 | 一种铝箔代替高分子柔性膜的柔性电路板结构及制备工艺 |
TWI835219B (zh) * | 2022-07-25 | 2024-03-11 | 陳旭東 | 減成法細線路電路板製造方法 |
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JP3361556B2 (ja) * | 1992-09-25 | 2003-01-07 | 日本メクトロン株式会社 | 回路配線パタ−ンの形成法 |
JP2748895B2 (ja) * | 1995-08-11 | 1998-05-13 | 日本電気株式会社 | 印刷配線板の製造方法 |
JPH1098268A (ja) * | 1996-09-24 | 1998-04-14 | Oki Electric Ind Co Ltd | 柱状導体のめっき方法及びそれにより得られる多層プリント配線板 |
JP3191759B2 (ja) * | 1998-02-20 | 2001-07-23 | 日本電気株式会社 | 半導体装置の製造方法 |
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JP2005026313A (ja) * | 2003-06-30 | 2005-01-27 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
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US10874021B2 (en) | 2020-12-22 |
JP2018064001A (ja) | 2018-04-19 |
CN107920424B (zh) | 2022-03-04 |
US20180103547A1 (en) | 2018-04-12 |
KR20180040091A (ko) | 2018-04-19 |
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