CN113169081A - 具有增强性能的晶片级扇出封装 - Google Patents
具有增强性能的晶片级扇出封装 Download PDFInfo
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- CN113169081A CN113169081A CN201980079375.2A CN201980079375A CN113169081A CN 113169081 A CN113169081 A CN 113169081A CN 201980079375 A CN201980079375 A CN 201980079375A CN 113169081 A CN113169081 A CN 113169081A
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Abstract
本公开涉及一种增强晶片级封装的性能的封装工艺。所公开的封装包含多个模制化合物(26、34、42)、多层重布结构,以及具有装置层和所述装置层下方的裸片凸块(30)的经薄化裸片(10T)。所述多层重布结构包含在所述多层重布结构的底部处的封装接触件(50)以及将所述裸片凸块连接到所述封装接触件的重布互连件(46)。第一模制化合物(26)驻留于所述经薄化裸片周围以囊封所述经薄化裸片的侧壁,且延伸超出所述经薄化裸片的顶部表面以界定所述经薄化裸片上方的开口。第二模制化合物(34)驻留于所述多层重布结构与所述第一模制化合物之间以囊封所述装置层的底部表面和每一裸片凸块。第三模制化合物(42)填充所述开口且与所述经薄化裸片的所述顶部表面接触。
Description
技术领域
本公开涉及一种封装工艺,且更具体地说,涉及一种提供具有增强的热和电气性能的晶片级扇出(WLFO)封装的封装工艺。
背景技术
蜂窝式及无线装置的广泛利用驱动射频(RF)技术的快速发展。在其上制造RF装置的衬底在实现RF技术的高水平性能方面起着重要作用。在常规硅衬底上制造RF装置可能会受益于硅材料的低成本、大规模的晶片生产能力、完善的半导体设计工具以及完善的半导体制造技术。
尽管将常规硅衬底用于RF装置制造具有益处,但在行业中众所周知,常规硅衬底对于RF装置可能具有两个不合需要的特性:谐波失真和低电阻率值。谐波失真是在硅衬底上构建的RF装置中实现高水平线性度的关键障碍。另外,在硅衬底中遇到的低电阻率在微机电系统(MEMS)或其它无源组件的高频率下会使品质因子(Q)降级。
此外,高速和高性能晶体管更密集地集成在RF装置中,即使它们需要运载更多功率。因此,由于通过晶体管的大量电力、集成在RF装置中的大量晶体管和晶体管的高操作速度,RF装置生成的热量将显著增大。因此,需要以实现更好散热的配置来封装RF装置。
晶片级扇出(WLFO)封装技术和嵌入式晶片级球栅阵列(EWLB)技术当前在便携式RF应用中吸引大量注意力。WLFO和EWLB技术被设计成提供高密度输入/输出端口(I/O)以及低轮廓封装高度,而不会增加组件半导体芯片的大小。芯片上的I/O衬垫大小保持较小,从而将裸片大小保持为最小。此能力允许在单个晶片内密集地封装RF装置。
为了适应RF装置的增加的发热,减少硅衬底的有害谐波失真和质量因子损失,且利用WLFO/EWLB封装技术的优点,因此本公开的目的是提供用于具有增强的热和电气性能的晶片级扇出(WLFO)封装的封装工艺。
发明内容
本公开涉及一种提供具有增强的热和电气性能的晶片级扇出(WLFO)封装的封装工艺。根据示例性过程,提供一种包含第一完整裸片、第一模制化合物和第二模制化合物的模具封装。在此,所述第一完整裸片包含第一装置层、所述第一装置层上方的第一电介质层、所述第一电介质层上方的第一硅衬底,以及所述第一装置层下方的若干第一裸片凸块。所述第一模制化合物驻留于所述第一完整裸片周围以囊封所述第一完整裸片的侧壁,而所述第一硅衬底的背侧暴露。所述第二模制化合物形成于所述第一模制化合物下方以覆盖所述第一装置层的底部表面且囊封每一第一裸片凸块。接下来,基本上移除第一完整裸片的第一硅衬底以提供第一经薄化裸片且形成开口,所述开口在第一模制化合物内和第一经薄化裸片上方。第一经薄化裸片的顶部表面在开口的底部处暴露。随后施加第三模制化合物以基本上填充所述开口且直接接触所述第一经薄化裸片的所述顶部表面。在形成第三模制化合物之后,将第二模制化合物薄化以暴露每一第一裸片凸块。最后,在第二模制化合物下方形成多层重布结构。所述多层重布结构包含多层重布结构的底部处的若干封装接触件,以及将封装接触件连接到第一裸片凸块中的某些第一裸片凸块的重布互连件。
在示例性过程的一个实施例中,多层重布结构是无玻璃的,且重布互连件与每一第一裸片凸块之间的连接是无焊料的。
在示例性过程的一个实施例中,第一完整裸片提供微机电系统(MEMS)组件。
在示例性过程的一个实施例中,第一完整裸片由绝缘体上硅(SOI)结构形成。第一完整裸片的第一装置层由SOI结构的硅层形成,第一完整裸片的第一电介质层是SOI结构的内埋氧化物层,且第一完整裸片的第一硅衬底是SOI结构的硅衬底。
在示例性过程的一个实施例中,模具封装还包含第二完整裸片,其包含第二装置层、第二装置层上方的第二硅衬底以及第二装置层下方的若干第二裸片凸块。所述第一完整裸片比所述第二完整裸片高。第一模制化合物囊封第二完整裸片的侧壁和顶部表面。所述第二模制化合物覆盖所述第二装置层的底部表面且囊封每一第二裸片凸块。在此,第一完整裸片提供MEMS组件,且第二完整裸片提供控制MEMS组件的互补金属氧化物半导体(CMOS)控制器。
在示例性过程的一个实施例中,第三模制化合物具有大于1E6 Ohm-cm的电阻率。
在示例性过程的一个实施例中,第三模制化合物具有大于2W/m·K的热导率。
在示例性过程的一个实施例中,第三模制化合物具有大于10W/m·K的热导率。
在示例性过程的一个实施例中,第一模制化合物、第二模制化合物和第三模制化合物由不同材料形成。
在示例性过程的一个实施例中,第二模制化合物和第三模制化合物由相同的材料形成。
在示例性过程的一个实施例中,在开口的底部处暴露的第一经薄化裸片的顶部表面是第一电介质层的顶部表面。
在示例性过程的一个实施例中,通过提供包含第一完整裸片和第一模制化合物的前体封装来形成模具封装。在此,第一模制化合物囊封第一完整裸片的侧壁和顶部表面,且第一装置层的底部表面和每一第一裸片凸块暴露。接下来,所述第二模制化合物形成于所述第一模制化合物下方以覆盖所述第一装置层的底部表面且囊封每一第一裸片凸块。随后向下薄化所述第一模制化合物以暴露所述第一硅衬底的背侧。
在示例性过程的一个实施例中,通过将第一非凸块裸片附接到载体的顶部表面形成前体封装。在此,第一非凸块裸片包含第一装置层、第一装置层上方的第一电介质层,以及第一电介质层上方的第一硅衬底。接下来,在载体的顶部表面上方施加第一模制化合物以囊封第一非凸块裸片。随后移除载体以暴露第一非凸块裸片的第一装置层的底部表面。最后,在第一装置层的暴露底部表面处形成若干第一裸片凸块以完成第一完整裸片。第一裸片凸块未被第一模制化合物覆盖。
在示例性过程的一个实施例中,第三模制化合物的一部分驻留于第一模制化合物上方。
在示例性过程的一个实施例中,第一模制化合物的顶部表面和第三模制化合物的顶部表面是共面的。
根据另一实施例,示例性过程还包含在第一模制化合物的顶部表面和第三模制化合物的顶部表面上方施加第四模制化合物。
在示例性过程的一个实施例中,第一模制化合物和第四模制化合物由相同材料形成。
在示例性过程的一个实施例中,第三模制化合物是通过压缩模制工艺施加的。
在示例性过程的一个实施例中,用于施加第三模制化合物的模制压力低于1000psi。
本领域的技术人员在结合附图阅读优选实施例的以下详细描述之后,将了解本公开的范围且认识到本公开的额外方面。
附图说明
并入在本说明书中并且形成本说明书的一部分的附图说明本公开的若干方面,并且与描述一起用以解释本公开的原理。
图1-4示出根据本公开的一个实施例的提供前体封装的示例性步骤。
图5提供示出从图4中示出的前体封装提供具有增强性能的晶片级扇出(WLFO)封装的示例性过程的流程图。
图6-13示出与图5的过程相关联的步骤。
应理解,为了说明的清楚起见,图1-13可能未按比例绘制。
具体实施方式
下文阐述的实施例表示使本领域的技术人员能够实践实施例的必要信息,且说明实践实施例的最佳模式。在根据附图阅读以下描述后,本领域的技术人员将理解本公开的概念且将认识到本文中并未特定阐释的这些概念的应用。应理解,这些概念和应用落入本公开和所附权利要求书的范围内。
将理解,虽然术语“第一”、“第二”等可在本文中用于描述各种元件,但这些元件不应受这些术语限制。这些术语仅用以将一个元件与另一元件区分开来。举例来说,在不脱离本公开的范围的情况下,第一元件可称为第二元件,且类似地,第二元件可称为第一元件。如本文所用,术语“和/或”包括相关联的所列项目中的一个或多个的任何和所有组合。
将理解,当例如层、区或衬底的元件被称为在另一元件“上”或延伸“到”另一元件“上”时,其可以直接在所述另一元件上或直接延伸到另一元件上,或也可能存在介入元件。相比之下,当元件被称为“直接在”另一元件“上”或“直接”延伸“到”另一元件“上”时,不存在介入元件。同样,应理解,当例如层、区或衬底的元件被称为在另一元件“上方”或在其“上方”延伸时,其可直接在另一元件上方或在另一元件上方延伸,或也可存在介入元件。相比之下,当元件被称为“直接在”另一元件“上方”或“直接”在另一元件“上方”延伸时,不存在介入元件。还应理解,当元件被称为“连接”或“耦合”到另一元件时,其可直接连接或耦合到另一元件,或可存在介入元件。相比之下,当元件被称作“直接连接”或“直接耦合”到另一元件时,不存在插入元件。
在本文中可使用例如“下方”或“上方”或“上部”或“下部”或“水平”或“垂直”的相对术语来描述一个元件、层或区与另一元件、层或区的关系,如图所示。应理解,这些术语和上文所论述的术语既定涵盖除图式中所描绘的定向以外的装置的不同定向。
本文中所使用的术语仅出于描述特定实施例的目的,且并不意图限制公开内容。如本文中所使用,除非上下文另外清晰地指示,否则单数形式“一”和“所述”也意图包含复数形式。将进一步理解,术语“包括”和/或“包含”在于本文中使用时指定所陈述的特征、整数、步骤、操作、元件和/或组件的存在,但并不排除一或多个其它特征、整数、步骤、操作、元件、组件和/或其群组的存在或添加。
除非另外定义,否则本文中所使用的所有术语(包含技术和科学术语)具有与本领域的普通技术人员通常所理解的相同的意义。将进一步理解的是,除非在此明确地定义,否则本文中使用的术语应被解释为具有与其在本说明书和相关技术的上下文中的含义一致的含义,并且将不以理想化或过度正式的意义来解释。
本公开涉及一种提供具有增强的热和电气性能的晶片级扇出(WLFO)封装的封装工艺。图1-4示出根据本公开的一个实施例的提供前体封装的示例性步骤。尽管示例性步骤说明为系列,但示例性步骤不一定取决于次序。一些步骤可能以与所呈现的次序不同的次序进行。另外,本公开的范围内的过程可包含比图1-4中说明的过程更少或更多的步骤。
起初,将第一非凸块裸片10N和第二非凸块裸片12N附接到载体14的顶部表面,如图1中所图示。在不同应用中,可能存在附接到载体14的更少或更多裸片。举例来说,在一些应用中,可能存在附接到载体14的多个第一非凸块裸片10N,同时省略第二非凸块裸片12N。在一些应用中,可能存在附接到载体14的多个第一非凸块裸片10N和一个第二非凸块裸片12N。在一些应用中,可能存在附接到载体14的多个第一非凸块裸片10N和多个第二非凸块裸片12N。在一些应用中,除第一非凸块裸片10N和第二非凸块裸片12N以外,可能存在附接到载体14的一些集成无源装置裸片(未示出)。为了增强附接,在载体14的顶部表面处可能存在粘合剂层(未示出)。
第一非凸块裸片10N包含第一装置层16、第一装置层16上方的第一电介质层18,以及第一电介质层18上方的第一硅衬底20。因此,第一装置层16的底部表面是第一非凸块裸片10N的底部表面,且第一硅衬底20的背侧是第一非凸块裸片10N的顶部表面。在一个实施例中,第一非凸块裸片10N可以由绝缘体上硅(SOI)结构形成,其指代包含硅衬底、硅层和包夹在硅衬底与硅层之间的内埋氧化物层的结构。第一非凸块裸片10N的第一装置层16可以通过在SOI结构的硅层中或上集成电子组件(未示出)形成。第一非凸块裸片10N的第一电介质层18可以是SOI结构的内埋氧化物层。第一非凸块裸片10N的第一硅衬底20可以是SOI结构的硅衬底。在此,第一非凸块裸片10N可以分别具有25μm与250μm之间或10μm与750μm之间的厚度,且第一硅衬底20可以分别具有25μm与250μm之间或10μm与750μm之间的厚度。第一装置层16可以具有0.1μm与50μm之间的厚度,且第一电介质层18可以具有10nm与2000nm之间的厚度。
在另一实施例中,第一非凸块裸片10N可以提供微机电系统(MEMS)组件(未示出),其通常是开关且在第一装置层16内。在此,第一非凸块裸片10N可以分别具有25μm与300μm之间或10μm与800μm之间的厚度,且第一硅衬底20可以分别具有25μm与300μm之间或10μm与800μm之间的厚度。第一装置层16可以具有0.5μm与100μm之间的厚度,且可以由电介质和金属层的组合(例如氧化硅、氮化硅、铝、钛、铜或类似物)形成。第一电介质层18可以具有10nm与10000nm之间的厚度,且可以由氧化硅、氮化硅、氧化铝或氮化铝形成。
第二非凸块裸片12N包含第二装置层22和第二装置层22上方的第二硅衬底24。第二装置层22的底部表面是第二非凸块裸片12N的底部表面,且第二硅衬底24的背侧是第二非凸块裸片12N的顶部表面。如果第一非凸块裸片10N提供MEMS组件,那么第二非凸块裸片12N可以提供控制MEMS组件且在第二装置层22中的互补金属氧化物半导体(CMOS)控制器(未示出)。在此,第二非凸块裸片12N分别具有25μm与250μm之间或10μm与750μm之间的厚度,且第二硅衬底24可以分别具有25μm与250μm之间或10μm与750μm之间的厚度。第二装置层22可以具有0.1μm与50μm之间的厚度,且可以由电介质和金属层的组合形成(例如氧化硅、氮化硅、铝、钛、铜或类似物)。另外,如果第一非凸块裸片10N不提供MEMS组件且由SOI结构形成,那么可省略第二非凸块裸片12N。此外,第二非凸块裸片12N可以比第一非凸块裸片10N短。
接下来,将第一模制化合物26施加在载体14的顶部表面上方以囊封第一非凸块裸片10N和第二非凸块裸片12N,如图2中所图示。第一模制化合物26可为有机环氧树脂体系或类似物,其可用作蚀刻剂屏障以保护第一非凸块裸片10N和第二非凸块裸片12N不受蚀刻化学品影响(以下部分中描述细节),所述蚀刻化学品例如氢氧化钾(KOH)、氢氧化钠(NaOH)和乙酰胆碱(ACH)。第一模制化合物26可通过各种程序施加,例如片材模制、包覆模制、压缩模制、转移模制、围坝填充囊封或丝网印刷囊封。在典型压缩模制中,用于施加第一模制化合物26的模制压力是在100psi与1000psi之间。由于第一非凸块裸片10N和第二非凸块裸片12N相对地厚且第一非凸块裸片10N和第二非凸块裸片12N的底部表面是基本上平坦的,因此在此模制步骤期间第一非凸块裸片10N和第二非凸块裸片12N不会发生竖直变形。
接着使用固化过程(未示出)来硬化第一模制化合物26。固化温度介于100℃与320℃之间,具体取决于哪种材料用作第一模制化合物26。遵循研磨工艺(未示出)来提供第一模制化合物26的平坦化顶部表面。随后移除载体14以暴露第一非凸块裸片10N的第一装置层16的底部表面和第二非凸块裸片12N的第二装置层22的底部表面,如图3中所示。
图4示出提供前体封装28的处理步骤。在此,在第一装置层16下方在第一装置层16的暴露底部表面处形成若干第一裸片凸块30以提供第一完整裸片10。在第二装置层22下方在第二装置层22的暴露底部表面处形成若干第二裸片凸块32以提供第二完整裸片12。第一裸片凸块28和第二裸片凸块30可以是铜柱,且未被第一模制化合物26覆盖。
图5提供示出从图4中示出的前体封装28提供具有增强性能的晶片级扇出(WLFO)封装的示例性过程的流程图。图6-13示出与图5的过程相关联的步骤。虽然流程图和相关联步骤是以系列示出,但它们不一定取决于次序。一些步骤可能以与所呈现的次序不同的次序进行。另外,本公开的范围内的过程可包含比图5中说明的过程更少或更多的步骤。
首先,在第一模制化合物26下方形成第二模制化合物34,如图6中所图示(步骤100)。第二模制化合物34覆盖第一装置层16的暴露底部表面和第二装置层22的暴露底部表面,且囊封每一第一裸片凸块30和每一第二裸片凸块32。第一完整裸片10和第二完整裸片12下方不存在气隙。第二模制化合物34可具有在5μm与200μm之间的厚度。第二模制化合物34和第一模制化合物26可以由相同材料或不同材料形成。由于第二模制化合物34直接连接到第一装置层16和第二装置层22,因此第二模制化合物34可以由高热导率材料形成以获得第一完整裸片10和第二完整裸片12的优良热性能。第二模制化合物34具有大于2W/m·K或大于10W/m·K的热导率,例如热塑性材料或热固性材料。
第二模制化合物34可通过各种程序涂覆,例如片材模制、包覆模制、压缩模制、转移模制、围坝填充囊封或丝网印刷囊封。在典型压缩模制中,如果第二模制化合物34由高热导率材料(>=2W/m·K)形成,那么用于施加第二模制化合物34的模制压力和温度分别在250psi与1000psi之间和100℃与350℃之间。在此,由于前体封装28相对地厚,因此在此模制步骤期间第一完整裸片10和第二完整裸片12不会发生竖直变形。
接着使用固化过程(未示出)来硬化第二模制化合物34。固化温度介于100℃与320℃之间,具体取决于哪种材料用作第二模制化合物34。遵循研磨工艺(未示出)以提供第二模制化合物34的平坦化底部表面。接下来,将第一模制化合物26向下薄化以暴露第一完整裸片10的第一硅衬底20的背侧且提供模具封装36,如图7中所图示(步骤102)。薄化程序可利用机械研磨工艺完成。在此,第二完整裸片12具有比第一完整裸片10低的高度,使得第二完整裸片12的第二硅衬底24不暴露且第二完整裸片12仍由第一模制化合物26完全囊封。
在第一硅衬底20的背侧暴露之后,基本上移除第一硅衬底20以提供经蚀刻封装38,如图8中所图示(步骤104)。从第一完整裸片10移除第一硅衬底20提供第一经薄化裸片10T,且在第一模制化合物26内和第一经薄化裸片10T上方形成第一开口40。在此,基本上移除硅衬底指代移除硅衬底的至少95%且留下硅衬底的至多2μm。在所需情况中,完全移除第一硅衬底20,使得第一经薄化裸片10T的第一电介质层18在第一开口40的底部处暴露。
基本上移除第一硅衬底20可以通过蚀刻工艺用潮湿/干燥蚀刻剂化学品提供,所述蚀刻剂化学品可以是TMAH、KOH、ACH、NaOH或类似物。第一电介质层18可以充当蚀刻停止层以保护第一经薄化裸片10T的第一装置层16。第一模制化合物26囊封且保护第二完整裸片12不受潮湿/干燥蚀刻剂化学品影响,且第二模制化合物34保护第一经薄化裸片10T的底部表面和第二完整裸片12的底部表面不受蚀刻剂化学品影响。
接下来,施加第三模制化合物42以基本上填充第一开口40,如图9A中所图示(步骤106)。在此,基本上填充开口指代填充整个开口的至少75%。第三模制化合物42直接驻留于第一经薄化裸片10T的顶部表面上方。如果第一开口40中未留下第一硅衬底20,那么第三模制化合物42将直接驻留于第一电介质层18上方。在一些情况下,第三模制化合物42的一部分还可以驻留于第一模制化合物26上方。第三模制化合物42通过第一模制化合物26与第二完整裸片12分离。第二完整裸片12的顶部表面与第一模制化合物26接触。
第三模制化合物42可以具有大于2W/m·K或大于10W/m·K的热导率,且具有大于1E6 Ohm-cm的电阻率。通常,第三模制化合物42的热导率越高,第一经薄化裸片10T的热性能越好。此外,第三模制化合物42的高电阻率可以改善在第一经薄化裸片10T中提供的MEMS组件的在高频率下的质量因子(Q),或如果从SOI结构形成则可以减少第一经薄化裸片10T中的信号丢失。
第三模制化合物42可以由热塑性材料或热固性材料形成,例如PPS(聚苯基硫化物)、掺杂有氮化硼或氧化铝热添加剂的包覆模制环氧树脂,或类似物。第一模制化合物26、第二模制化合物34和第三模制化合物42可以由相同材料或不同材料形成。举例来说,第二模制化合物34和第三模制化合物42可以由相同材料形成,而第一模制化合物26可以由不同材料形成。不同于第三模制化合物42,第一模制化合物26不具有热导率要求。
第三模制化合物42可通过各种程序涂覆,例如薄片模制、包覆模制、压缩模制、转移模制、围坝填充囊封或丝网印刷囊封。在第三模制化合物42的模制工艺期间,在整个经蚀刻封装38上液化和模制压力可能不均匀。因为第一经薄化裸片10T和在第一经薄化裸片10T正下方的第二模制化合物34的一部分比经蚀刻封装38的其它部分薄,所以它们可能比经蚀刻封装38的其它部分经历更多变形。在典型压缩模制中,如果第三模制化合物42由高热导率材料(>=2W/m·K)形成,那么用于施加第二模制化合物42的模制压力和温度分别在250psi与1000psi之间和100℃与350℃之间。接着使用固化过程(未示出)来硬化第三模制化合物42。取决于哪种材料用作第三模制化合物42,固化温度在100℃与320℃之间。遵循研磨工艺(未示出)来提供第三模制化合物42的平坦化顶部表面。
应注意,第一经薄化裸片10T和第一经薄化裸片10T下方的第二模制化合物部分34的组合可以具有至少8μm的厚度。第一经薄化裸片10T下方不存在气隙,且第二模制化合物34的底部表面是平坦化的。因此,在第三模制化合物42的模制步骤期间第一经薄化裸片10T不会发生竖直变形。然而,如果第一模制化合物26下方未形成第二模制化合物34,特别地是未填充第一经薄化裸片10T竖直下方的第一裸片凸块30之间的间隙,那么在第三模制化合物42的模制步骤期间可能发生第一经薄化裸片10T的竖直变形。在第一经薄化裸片10T下方竖直地间隙中无额外支撑的情况下,第一经薄化裸片10T不会经受高竖直模制压力。
在一些应用中,第三模制化合物42不覆盖第一模制化合物26的顶部表面。实际上,第三模制化合物42的顶部表面和第一模制化合物26的顶部表面是共面的,如图9B中所图示。此外,如果第三模制化合物42的一部分驻留于第一模制化合物26上方,那么可以施加研磨工艺以向下薄化第三模制化合物42,直到第三模制化合物42的顶部表面和第一模制化合物26的顶部表面是共面的。
另外,如果第三模制化合物42的顶部表面和第一模制化合物26的顶部表面是共面的,那么可能存在施加于第一模制化合物26上方和第三模制化合物42上方的第四模制化合物44,如图9C中所图示。在此,第四模制化合物44可以由与第一模制化合物26、第二模制化合物34和/或第三模制化合物42相同或不同的材料形成。举例来说,第一模制化合物26和第四模制化合物44可以由一种材料形成,而第二模制化合物34和第三模制化合物42可以由另一种材料形成。类似于第一模制化合物26,第四模制化合物44不具有热导率要求。
第四模制化合物44可通过各种程序涂覆,例如薄片模制、包覆模制、压缩模制、转移模制、围坝填充囊封或丝网印刷囊封。接着使用固化过程(未示出)来硬化第四模制化合物44。取决于哪种材料用作第四模制化合物44,固化温度在100℃与320℃之间。遵循研磨工艺(未示出)来提供第四模制化合物44的平坦化顶部表面。
在施加第三模制化合物42之后,将第二模制化合物34薄化以暴露每一第一裸片凸块30和每一第二裸片凸块32,如图10中所图示(步骤108)。在此,由于第一裸片凸块30从第一经薄化裸片10T的底部表面突出且第二裸片凸块32从第二完整裸片12的底部表面突出,因此第一经薄化裸片10T的底部表面和第二完整裸片12的底部表面仍被第二模制化合物34完全覆盖。薄化程序可利用机械研磨工艺完成。
参考图11至13,根据本公开的一个实施例形成多层重布结构(步骤110)。虽然重布步骤以系列示出,但重布步骤不一定是按次序的。一些步骤可能以与所呈现的次序不同的次序进行。此外,本公开的范围内的重布步骤可包含比图11-13中示出的那些更少或更多的步骤。
首先在第二模制化合物34下方形成若干重布互连件46,如图11中所图示。出于此图示的目的,重布互连件46包含三个第一重布互连件46(1)和一个第二重布互连件46(2)。在不同应用中,重布互连件46可包含更少或更多的第一重布互连件46(1)和更少或更多的第二重布互连件46(2)。每一第一重布互连件46(1)电耦合到在第二模制化合物34的底部表面处暴露的第一裸片凸块30和第二裸片凸块32中的对应一个。第二重布互连件46(2)被配置成将一个第一裸片凸块30连接到对应第二裸片凸块32,使得第一经薄化裸片10T连接到第二完整裸片12。重布互连件46与第一裸片凸块30/第二裸片凸块32之间的连接是无焊料的。
接下来,在第二模制化合物34下方形成电介质图案48以部分地囊封每一第一重布互连件46(1),如图12中所图示。因此,每一第一重布互连件46(1)的一部分通过电介质图案48暴露。此外,电介质图案48完全囊封第二重布互连件46(2)。在此,没有第二重布互连件46(2)的部分通过电介质图案48暴露。在不同应用中,可能存在通过电介质图案48以及形成于电介质图案48下方的额外电介质图案(未示出)电耦合到第一重布互连件46(1)的额外重布互连件(未示出),使得每一额外重布互连件的一部分暴露。
最后,形成若干封装接触件50以完成多层重布结构52且提供WLFO封装54,如图13中所图示。每一封装接触件50形成于多层重布结构52的底部处,且通过电介质图案48电耦合到对应第一重布互连件46(1)的暴露部分。因此,第一重布互连件46(1)将封装接触件50连接到第一裸片凸块30和第二裸片凸块32中的某些裸片凸块。另外,封装接触件50彼此分开且在电介质图案48下方延伸。
多层重布结构52可以不含玻璃纤维或不含玻璃。在此,玻璃纤维指代扭曲而变为较大分组的个别玻璃链。这些玻璃链可以随后被编织为织物。电介质图案48可以由苯并环丁烯(BCB)、聚酰亚胺或其它电介质材料形成。重布互连件46可以由铜或其它合适的金属形成。封装接触件50可以由铜、金、镍和钯中的至少一个形成。多层重布结构52具有2μm与300μm之间的厚度。
所属领域的技术人员将认识到对本公开的优选实施例的改善和修改。所有此类改善和修改被视为在本文中公开的概念和所附的权利要求书的范围内。
权利要求书(按照条约第19条的修改)
1.一种方法,其包括:
·形成包含第一完整裸片和第一模制化合物的前体封装,其中:
·所述第一完整裸片包括第一装置层、所述第一装置层上方的第一电介质层、所述第一电介质层上方的第一硅衬底,以及所述第一装置层下方的多个第一裸片凸块;以及
·所述第一模制化合物囊封所述第一完整裸片的侧壁和顶部表面,而所述第一装置层的底部表面和所述多个第一裸片凸块中的每一个暴露;
·在所述第一模制化合物下方施加所述第二模制化合物以覆盖所述第一装置层的所述底部表面且囊封所述多个第一裸片凸块中的每一个;
·向下薄化所述第一模制化合物以暴露所述第一硅衬底的背侧;
·基本上移除所述第一完整裸片的所述第一硅衬底以提供第一经薄化裸片且在所述第一模制化合物内和所述第一经薄化裸片上方形成开口,其中所述第一经薄化裸片具有在所述开口的底部处暴露的顶部表面;
·在施加所述第二模制化合物之后施加第三模制化合物以基本上填充所述开口且直接接触所述第一经薄化裸片的所述顶部表面;以及
·在施加所述第三模制化合物之后薄化所述第二模制化合物以暴露所述多个第一裸片凸块中的每一个。
2.根据权利要求1所述的方法,其中所述第一经薄化裸片提供微机电系统(MEMS)组件。
3.根据权利要求1所述的方法,其中所述第一完整裸片由绝缘体上硅(SOI)结构形成,其中所述第一完整裸片的所述第一装置层由所述SOI结构的硅层形成,所述第一完整裸片的所述第一电介质层是所述SOI结构的内埋氧化物层,且所述第一完整裸片的所述第一硅衬底是所述SOI结构的硅衬底。
4.根据权利要求1所述的方法,其中:
·所述前体封装还包括第二裸片,所述第二裸片包含第二装置层、所述第二装置层上方的第二硅衬底以及所述第二装置层下方的多个第二裸片凸块,其中:
·所述第一完整裸片比所述第二裸片高;且
·所述第一模制化合物囊封所述第二裸片的侧壁和顶部表面;以及
·施加所述第二模制化合物以覆盖所述第二装置层的底部表面且囊封所述多个第二裸片凸块中的每一个。
5.根据权利要求4所述的方法,其中所述第一经薄化裸片提供MEMS组件,且所述第二裸片提供控制所述MEMS组件的互补金属氧化物半导体(CMOS)控制器。
6.根据权利要求1所述的方法,其中所述第三模制化合物具有大于1E6 Ohm-cm的电阻率。
7.根据权利要求1所述的方法,其中所述第三模制化合物具有大于2W/m·K的热导率。
8.根据权利要求1所述的方法,其中所述第三模制化合物具有大于10W/m·K的热导率。
9.根据权利要求1所述的方法,其中所述第一模制化合物、所述第二模制化合物和所述第三模制化合物由不同材料形成。
10.根据权利要求1所述的方法,其中所述第二模制化合物和所述第三模制化合物由相同的材料形成。
11.根据权利要求1所述的方法,其中在所述第二模制化合物的所述薄化过程之前所述第二模制化合物具有5μm与200μm之间的厚度。
12.根据权利要求1所述的方法,其中在所述开口的所述底部处暴露的所述第一经薄化裸片的所述顶部表面是所述第一电介质层的顶部表面。
13.根据权利要求1所述的方法,还包括在所述第二模制化合物下方形成多层重布结构,其中所述多层重布结构包括所述多层重布结构的底部处的多个封装接触件,以及将所述多个封装接触件连接到所述多个第一裸片凸块中的某些第一裸片凸块的重布互连件。
14.根据权利要求13所述的方法,其中:
·所述多层重布结构是无玻璃的,且
·所述重布互连件与所述多个第一裸片凸块中的每一个之间的连接是无焊料的。
15.根据权利要求1所述的方法,其中形成所述前体封装包括:
·将第一非凸块裸片附接到载体的顶部表面,其中所述第一非凸块裸片包含所述第一装置层、所述第一装置层上方的所述第一电介质层以及所述第一电介质层上方的所述第一硅衬底;
·在所述载体的所述顶部表面上方施加所述第一模制化合物以囊封所述第一非凸块裸片;
·移除所述载体以暴露所述第一非凸块裸片的所述第一装置层的所述底部表面;
·在所述第一装置层的所述暴露底部表面处形成所述多个第一裸片凸块以完成所述第一完整裸片,其中所述多个第一裸片凸块未被所述第一模制化合物覆盖。
16.根据权利要求1所述的方法,其中所述第三模制化合物的一部分驻留于所述第一模制化合物上方。
17.根据权利要求1所述的方法,其中所述第一模制化合物的顶部表面和所述第三模制化合物的顶部表面是共面的。
18.根据权利要求17所述的方法,还包括在所述第一模制化合物的所述顶部表面和所述第三模制化合物的所述顶部表面上方施加第四模制化合物。
19.根据权利要求18所述的方法,其中所述第一模制化合物和所述第四模制化合物由相同的材料形成。
20.根据权利要求1所述的方法,其中所述第三模制化合物是通过压缩模制工艺来施加。
21.根据权利要求1所述的方法,其中用于施加所述第三模制化合物的模制压力低于1000psi。
Claims (22)
1.一种方法,其包括:
·提供包含第一完整裸片、第一模制化合物和第二模制化合物的模具封装,其中:
·所述第一完整裸片包括第一装置层、所述第一装置层上方的第一电介质层、所述第一电介质层上方的第一硅衬底,以及所述第一装置层下方的多个第一裸片凸块;
·所述第一模制化合物驻留于所述第一完整裸片周围以囊封所述第一完整裸片的侧壁,其中所述第一硅衬底的背侧暴露;
·所述第二模制化合物形成于所述第一模制化合物下方以覆盖所述第一装置层的底部表面且囊封所述多个第一裸片凸块中的每一个;
·基本上移除所述第一完整裸片的所述第一硅衬底以提供第一经薄化裸片且在所述第一模制化合物内和所述第一经薄化裸片上方形成开口,其中所述第一经薄化裸片具有在所述开口的底部处暴露的顶部表面;
·施加第三模制化合物以基本上填充所述开口且直接接触所述第一经薄化裸片的所述顶部表面;以及
·薄化所述第二模制化合物以暴露所述多个第一裸片凸块中的每一个。
2.根据权利要求1所述的方法,其中所述第一完整裸片提供微机电系统(MEMS)组件。
3.根据权利要求1所述的方法,其中所述第一完整裸片由绝缘体上硅(SOI)结构形成,其中所述第一完整裸片的所述第一装置层由所述SOI结构的硅层形成,所述第一完整裸片的所述第一电介质层是所述SOI结构的内埋氧化物层,且所述第一完整裸片的所述第一硅衬底是所述SOI结构的硅衬底。
4.根据权利要求1所述的方法,其中所述模具封装还包括第二完整裸片,所述第二完整裸片包含第二装置层、所述第二装置层上方的第二硅衬底以及所述第二装置层下方的多个第二裸片凸块,其中:
·所述第一完整裸片比所述第二完整裸片高;
·所述第一模制化合物囊封所述第二完整裸片的侧壁和顶部表面;以及
·所述第二模制化合物覆盖所述第二装置层的底部表面且囊封所述多个第二裸片凸块中的每一个。
5.根据权利要求4所述的方法,其中所述第一完整裸片提供MEMS组件,且所述第二完整裸片提供控制所述MEMS组件的互补金属氧化物半导体(CMOS)控制器。
6.根据权利要求1所述的方法,其中所述第三模制化合物具有大于1E6 Ohm-cm的电阻率。
7.根据权利要求1所述的方法,其中所述第三模制化合物具有大于2W/m·K的热导率。
8.根据权利要求1所述的方法,其中所述第三模制化合物具有大于10W/m·K的热导率。
9.根据权利要求1所述的方法,其中所述第一模制化合物、所述第二模制化合物和所述第三模制化合物由不同材料形成。
10.根据权利要求1所述的方法,其中所述第二模制化合物和所述第三模制化合物由相同的材料形成。
11.根据权利要求1所述的方法,其中在所述第二模制化合物的所述薄化过程之前所述第二模制化合物具有5μm与200μm之间的厚度。
12.根据权利要求1所述的方法,其中在所述开口的所述底部处暴露的所述第一经薄化裸片的所述顶部表面是所述第一电介质层的顶部表面。
13.根据权利要求1所述的方法,还包括在所述第二模制化合物下方形成多层重布结构,其中所述多层重布结构包括所述多层重布结构的底部处的多个封装接触件,以及将所述多个封装接触件连接到所述多个第一裸片凸块中的某些第一裸片凸块的重布互连件。
14.根据权利要求13所述的方法,其中:
·所述多层重布结构是无玻璃的,且
·所述重布互连件与所述多个第一裸片凸块中的每一个之间的连接是无焊料的。
15.根据权利要求1所述的方法,其中提供所述模具封装包括:
·提供包含所述第一完整裸片和所述第一模制化合物的前体封装,其中所述第一模制化合物囊封所述第一完整裸片的所述侧壁和顶部表面,而所述第一装置层的所述底部表面和所述多个第一裸片凸块中的每一个暴露;
·在所述第一模制化合物下方施加所述第二模制化合物以覆盖所述第一装置层的所述底部表面且囊封所述多个第一裸片凸块中的每一个;以及
·向下薄化所述第一模制化合物以暴露所述第一硅衬底的所述背侧。
16.根据权利要求15所述的方法,其中提供所述前体封装包括:
·将第一非凸块裸片附接到载体的顶部表面,其中所述第一非凸块裸片包含所述第一装置层、所述第一装置层上方的所述第一电介质层以及所述第一电介质层上方的所述第一硅衬底;
·在所述载体的所述顶部表面上方施加所述第一模制化合物以囊封所述第一非凸块裸片;
·移除所述载体以暴露所述第一非凸块裸片的所述第一装置层的所述底部表面;
·在所述第一装置层的所述暴露底部表面处形成所述多个第一裸片凸块以完成所述第一完整裸片,其中所述多个第一裸片凸块未被所述第一模制化合物覆盖。
17.根据权利要求1所述的方法,其中所述第三模制化合物的一部分驻留于所述第一模制化合物上方。
18.根据权利要求1所述的方法,其中所述第一模制化合物的顶部表面和所述第三模制化合物的顶部表面是共面的。
19.根据权利要求18所述的方法,还包括在所述第一模制化合物的所述顶部表面和所述第三模制化合物的所述顶部表面上方施加第四模制化合物。
20.根据权利要求19所述的方法,其中所述第一模制化合物和所述第四模制化合物由相同的材料形成。
21.根据权利要求1所述的方法,其中所述第三模制化合物是通过压缩模制工艺来施加。
22.根据权利要求1所述的方法,其中用于施加所述第三模制化合物的模制压力低于1000psi。
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US10964554B2 (en) | 2021-03-30 |
CN113169081B (zh) | 2024-05-28 |
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US20200118838A1 (en) | 2020-04-16 |
EP3864689A1 (en) | 2021-08-18 |
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