CN110071106A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110071106A
CN110071106A CN201910057593.8A CN201910057593A CN110071106A CN 110071106 A CN110071106 A CN 110071106A CN 201910057593 A CN201910057593 A CN 201910057593A CN 110071106 A CN110071106 A CN 110071106A
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resistive element
capacitor
semiconductor device
circuit
terminal
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渕上千加志
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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Abstract

本发明提供一种可减少形成在半导体装置上的电路元件的面积的半导体装置。半导体装置包括：第1导电型区域，形成在基板上且形成有由绝缘膜包围的电阻元件；第2导电型区域，与电阻元件的上表面接触并层叠形成；电容器，经由层间绝缘层而形成在电阻元件上；过孔，将电阻元件的一端子及电容器的一端子电性串联连接；以及电源线及接地线，与电阻元件的另一端子及电容器的另一端子分别电性连接。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
在日本专利特开2016-111186号公报(专利文献1)中记载有一种半导体装置，为了免受静电放电(Electrostatic Discharge，ESD)的影响，其包括：检测电路，检测与被保护电路连接的电源线中产生的浪涌(surge)；相互串联连接的至少一个反相器；保护用晶体管，通过检测电路的输出来控制；以及时间常数电路，与此保护用晶体管连接。
发明内容
[发明所要解决的问题]
但是，在如专利文献1记载般的现有的半导体装置中，存在如下的缺点：构成检测电路的电阻元件及电容器并排地形成在表面上，它们的占有面积比半导体装置上的其他元件大。
本发明是鉴于所述问题点而成者，其目的在于提供一种可减少形成在半导体装置上的电路元件的占有面积的半导体装置。
[解决问题的技术手段]
本发明的半导体装置的特征在于包括：
基板；
第1导电型区域，形成在所述基板上且形成有由绝缘膜包围的电阻元件；
第2导电型区域，与所述电阻元件的上表面接触并层叠形成；
电容器，经由层间绝缘层而形成在所述电阻元件上；
过孔(via)，将所述电阻元件的一端子及所述电容器的一端子电性串联连接；以及
电源线及接地线，与所述电阻元件的另一端子及所述电容器的另一端子分别电性连接。
[发明的效果]
根据本发明的半导体装置，可不将电阻元件及电容器并排地形成在表面上，而将电阻元件与电容器两者重叠配置，因此可缩小包含所述电阻元件及所述电容器的电阻器电容器(Resistor-Capacitance，RC)电路的占有面积。进而，可通过具有深沟槽隔离(DeepTrench Isolation)结构的制造工艺来实现半导体装置的制造。
附图说明
图1是表示作为本发明的实施例的半导体装置的半导体集成电路的一例的电路图。
图2是表示本实施例的变形例的半导体集成电路的电路图。
图3是本实施例的半导体装置的与RC电路对应的部分的部分平面图。
图4是图3的XX线处的部分剖面图。
图5是图4的YY线处的部分剖面平面图。
图6是表示本实施例的变形例的电阻元件的部分剖面平面图。
符号的说明
100：半导体装置
102：保护对象电路
104：保护电路
111：RC串联电路
112：反相器电路
113：保护用NMOS晶体管
114：电阻元件
115：电容器
118：PMOS晶体管
120：NMOS晶体管
CPG：接触插塞
VIA：过孔
VDD：电源线
VSS：接地线
具体实施方式
以下，一面参照附图一面对本发明的实施例的半导体装置进行详细说明。再者，在实施例中，对实质上具有相同的功能及结构的构成要素标注相同的符号，由此省略重复说明。
图1是表示实施例的半导体装置的包含ESD保护电路的半导体集成电路的一例的电路图。图1中所示的保护电路104是用于连接在电源电位的电源线VDD与基准电位的接地线VSS之间的保护对象电路102的ESD保护者。如此图所示，现有的半导体装置100包含相当于半导体集成电路的保护对象电路102、及保护电路104来构成，保护对象电路102的一侧端子与电源线VDD连接，另一侧端子与接地线VSS连接。
如图1所示，保护电路104包括：RC串联电路111，与电源线VDD及接地线VSS连接；反相器电路112，与RC串联电路111、电源线VDD及接地线VSS连接；以及保护用N型金属氧化物半导体(N-Metal-Oxide-Semiconductor，NMOS)晶体管113，与反相器电路112、电源线VDD及接地线VSS连接。
RC串联电路111包括：在电源线VDD与接地线VSS之间串联连接的电阻元件114、及作为电容性负载的电容器115。
反相器电路112是通过将P型金属氧化物半导体(P-Metal-Oxide-Semiconductor，PMOS)晶体管118及NMOS晶体管120互补地配置来构成的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)反相器。即，反相器电路112使PMOS晶体管118的栅极与NMOS晶体管120的栅极连接，并将其连接点设为输入端子112in，使PMOS晶体管118的漏极与NMOS晶体管120的漏极连接，并将其连接点设为输出端子112out。RC串联电路111的电阻元件114及电容器115的连接点与输入端子112in连接。
保护用NMOS晶体管113的栅极与反相器电路112的输出端子112out连接，漏极与电源线VDD连接，源极与接地线VSS连接。
当被施加了因ESD而产生的高电压波形的电压(以下，称为“浪涌电压(surgevoltage)”)时，RC串联电路111、反相器电路112、保护用NMOS晶体管113的动作如以下般。即，若因ESD放电而朝电源线VDD与接地线VSS之间施加将电源线VDD侧作为正侧的浪涌电压(急速上升的高电压)，则输入端子112in的电位比浪涌电压的上升延迟上升。所述延迟依存于RC串联电路111的时间常数。若RC串联电路111的时间常数足够大，则在浪涌电压的施加结束之前，输入端子112in的电位保持为比反相器电路112的阈值低的状态，反相器电路112的NMOS晶体管120保持为断开的状态，PMOS晶体管118保持为接通的状态，其结果，电源线VDD的电压被施加至保护用NMOS晶体管113的栅极中，保护用NMOS晶体管113在被施加浪涌电压的期间内保持为接通状态。例如，ESD放电的持续时间为5纳秒至几百纳秒。
在如此构成的半导体装置100中，若浪涌电压被施加至电源线VDD或接地线VSS中，则保护电路104将所述浪涌电压作为触发，以消除电源线VDD与接地线VSS之间的电位差的方式运转，因此保护对象电路102得到保护。
在图1的例子中，连接有一个反相器电路，但反相器电路的个数并不限定于一个，也可以是三个以上的奇数个(保护用晶体管为NMOS晶体管的情况)。另外，在图1的例子的变形例中，例如在保护用晶体管为PMOS晶体管的情况下，反相器电路的个数也可以是两个以上的偶数个。
如图2所示，当电源线VDD保持在电源电压VDD时，由于RC串联电路111(电容器115)处于高阻抗状态，因此将电阻元件114与电容器115连接的输入端子112in的电位基本上处于高电平(VDD)。由于此高电平被施加至三个反相器中的初段的第1反相器电路1121的输入中，因此第1反相器电路1121的输出处于低电平(VSS)。此第1反相器电路1121的输出(低电平)决定第2反相器电路1122及第3反相器电路1123的各输出。此时，第2反相器电路1122的输出变成高电平，第3反相器电路1123的输出变成低电平。
因此，此时保护用NMOS晶体管113的栅极为低电平(VSS)，因此保护用NMOS晶体管113的通道关闭。因此，电流不从被施加了电源电压VDD的电源线VDD朝被施加了基准电位VSS的接地线VSS中流动。
继而，对在本实施例的半导体装置中，不将电阻元件及电容器并排形成在表面上，而将电阻元件114与电容器115(RC串联电路111)重叠配置进行说明。
如图3的与RC串联电路111对应的部分的部分平面图所示，作为形成在P型半导体基板Psub上且为第1导电型区域的N型井区域NWL，形成有由绝缘膜IIF(氧化硅膜)包围的电阻元件114。N型井区域NWL可通过将N型的杂质(例如磷)经由规定掩模开口而离子注入至半导体基板Psub的表层中来形成。也可以在绝缘膜IIF用的规定图案上实施干式蚀刻来挖沟，并将绝缘体埋入此沟中来形成电阻元件114。
如图4所示，在电阻元件114的上表面上，配置有与其接触并层叠形成的作为第2导电型区域的P型井区域PWL。使多晶硅膜在电阻元件114(N型井区域NWL)上成膜，而形成此多晶硅膜，并经由规定掩模开口图案而朝其表层中高浓度地离子注入P型的杂质(例如硼)，由此可形成P型井区域PWL。
电容器115是利用金属膜，经由层间绝缘层IIF2(氧化硅膜)而形成在电阻元件114上。
如图3所示，电容器115包含作为交指电容器(interdigital capacitor)IDC的一对金属的梳型电极(115a、115b)。梳型电极115a、梳型电极115b分支。梳型电极115a、梳型电极115b以彼此的齿部BRHa、齿部BRHb经由间隙部而咬合的方式相向。通过梳型电极115a、梳型电极115b来保持电容。
电阻元件114的一端子(N型掺杂剂高浓度扩散区域N+)及电容器115的一端子(梳型电极115a)通过过孔VIA而电性串联连接。
电阻元件114的另一端子(N型掺杂剂高浓度扩散区域N+2)经由接触插塞CPG而与电源线VDD电性连接。
另外，电容器115的另一端子(梳型电极115b)与接地线VSS电性连接。电容器115的梳型电极115b在其齿部BRHa各自的前端与根部，经由接触插塞CPG与P型掺杂剂高浓度扩散区域P+2而与P型井区域PWL连接。
如图5所示，电阻元件114是从一端子至另一端子(N+或N+2)为止连续的微带(microstrip)，且以曲折形式配置在P型半导体基板Psub与P型井区域PWL之间。
如图3、图4所示，过孔VIA作为反相器电路112(图1)的输入端子112in的输入侧而得到连接。
环状的绝缘体沟槽DTI以与电阻元件114(N型井区域NWL)及P型井区域PWL两者的侧面接触并包围两者的方式配置。
根据本实施例的半导体装置，不将电阻元件及电容器并排形成在基板表面上，通过用于深层分离绝缘结构的制造工艺，可将电阻元件114(曲折形式)及电容器115在膜厚方向上重叠配置。因此，可实现RC电路的占有面积的缩小。
再者，根据本实施例的半导体装置的变形例，如图6所示，也可以将电阻元件114的微带设为曲折形式以外的旋涡状的电阻元件114a来配置在P型半导体基板Psub与P型井区域PWL之间。

Claims (5)

1.一种半导体装置，其特征在于包括：
基板；
第1导电型区域，形成在所述基板上且形成有由绝缘膜包围的电阻元件；
第2导电型区域，与所述电阻元件的上表面接触并层叠形成；
电容器，经由层间绝缘层而形成在所述电阻元件上；
过孔，将所述电阻元件的一端子及所述电容器的一端子电性串联连接；以及
电源线及接地线，与所述电阻元件的另一端子及所述电容器的另一端子分别电性连接。
2.根据权利要求1所述的半导体装置，其特征在于，
所述电阻元件是从所述一端子至所述另一端子为止连续的微带，且以曲折形式配置在所述基板与所述第2导电型区域之间。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述电容器是包含隔着形成在所述层间绝缘层上的间隙部而相互相向的一对梳形电极的交指电容器。
4.根据权利要求3所述的半导体装置，其特征在于还包括：
至少一个反相器电路，输入侧与所述过孔连接，且在所述电源线及所述接地线之间与所述电源线及所述接地线分别连接；以及
保护电路，与所述反相器电路的输出侧连接。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于还包括：
以与所述电阻元件及所述第2导电型区域两者的侧面接触并包围两者的方式配置的环状的绝缘体沟槽。
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