CN102034812B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN102034812B
CN102034812B CN201010297980.8A CN201010297980A CN102034812B CN 102034812 B CN102034812 B CN 102034812B CN 201010297980 A CN201010297980 A CN 201010297980A CN 102034812 B CN102034812 B CN 102034812B
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CN102034812A (zh
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鹰巢博昭
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Ablic Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

在半导体装置中，在ESD保护用的N型MOS晶体管的衬底电位固定用P型扩散区与ESD保护用的N型MOS晶体管的源极及漏极区之间设置的沟槽分离区的深度，设定为比在内部元件的N型MOS晶体管的衬底电位固定用P型扩散区与内部元件的N型MOS晶体管的源极及漏极区之间设置的所述沟槽分离区的深度深。

Description

半导体装置
技术领域
本发明涉及具有在外部连接端子与内部电路区之间为了保护形成在所述内部电路区的内部元件免受ESD造成的破坏而形成的，ESD保护元件的半导体装置。
背景技术
在具有MOS型晶体管的半导体装置中，作为用于防止来自外部连接用的PAD的静电造成的内部电路的破坏的ESD保护元件，众所周知将N型MOS晶体管的栅极电位固定为接地(Vss)而设置为截止(OFF)状态的，所谓截止晶体管。
为了防止内部电路元件的ESD破坏，重要的是尽量将大比例的静电脉冲引入截止晶体管且对内部电路元件不传播，或者快速且较大的静电脉冲转化为缓慢且较小的信号后传输。
此外，截止晶体管与构成其它逻辑电路等的内部电路的MOS型晶体管不同，由于需要流尽一时引入的多量静电产生的电流，往往设定为数百微米级的较大的晶体管宽度(W宽度)。
因此存在截止晶体管的占有面积大，特别是在较小的IC芯片中成为整个IC的成本上升的原因的问题。
此外，截止晶体管往往采用将多个漏极区、源极区、栅极电极组合成梳齿形的形状，但通过采用组合多个晶体管的结构，难以使ESD保护用的N型MOS晶体管全体做均匀的动作，例如会在离外部连接端子的距离较近的部分产生电流集中，有时不能充分地发挥原来的ESD保护功能而被破坏。
作为其改善对策，还提出这样的例子：对应于离外部连接端子的距离，特别是使漏极区上的接触孔与栅极电极的距离，在离外部连接端子的距离越远时就越小而加快晶体管的动作的办法(例如，参照专利文献1)。
专利文献1：日本特开平7-45829号公报
发明内容
但是，为减小截止晶体管的占有面积而减小W宽度时，会无法充分地发挥保护功能。此外在改善例中，通过调整漏极区的，从接触部到栅极电极为止的距离，局部地调整晶体管动作速度，但是，由于随着漏极区的宽度的缩小无法确保所希望的接触宽度的，近年的包含高熔点金属的布线造成的布线的低电阻化，存在浪涌的传播速度进一步加快，有时仅由接触部到栅极电极为止的距离无法完全调整等的问题，此外，没有公开为了防止内部电路元件的ESD破坏，而以比内部电路元件低的电压可以进行停止(ォフトラ)动作，尽量将大比例的静电脉冲引入到截止晶体管并且不对内部电路元件传播的改善对策。
为了解决上述问题，本发明的半导体装置如下构成。
一种半导体装置，具有沟槽分离区，在内部电路区至少具有内部元件的N型MOS晶体管，在外部连接端子与所述内部电路区之间，具有保护所述内部元件的N型MOS晶体管或其它的内部元件免受ESD造成的破坏的ESD保护用的N型MOS晶体管，其中，在所述ESD保护用的N型MOS晶体管的衬底电位固定用P型扩散区与所述ESD保护用的N型MOS晶体管的源极及漏极区之间设置的所述沟槽分离区的深度，设定为比在所述内部元件的N型MOS晶体管的衬底电位固定用P型扩散区与所述内部元件的N型MOS晶体管的源极及漏极区之间设置的所述沟槽分离区的深度深。
通过这些方案，既不会增加工序也不会增加占有面积，而可以使继续ESD保护用的N型MOS晶体管的双极(bipolar)动作用的保持(hold)电压低于内部元件的N型MOS晶体管的保持电压，能够得到包括具有充分的ESD保护功能的ESD保护用的N型MOS晶体管的半导体装置。
(发明效果)
通过以上说明的方案，既不会增加工序也不会占有面积，而可以使继续ESD保护用的N型MOS晶体管的双极动作用的保持电压低于内部元件的N型MOS晶体管的保持电压，能够得到包括具有充分的ESD保护功能的ESD保护用的N型MOS晶体管的半导体装置。
附图说明
图1是表示本发明的半导体装置的ESD保护用的N型MOS晶体管和内部元件的N型MOS晶体管的一实施例的示意剖视图。
具体实施方式
实施例1
图1是表示本发明的半导体装置的ESD保护用的N型MOS晶体管和内部元件的N型MOS晶体管的一实施例的示意剖视图。
首先，从ESD保护用的N型MOS晶体管601开始进行说明。
在作为第一导电型半导体衬底的P型的硅衬底101上，形成由一对N型的高浓度杂质区构成的源极区201和漏极区202，在与其它的元件之间形成浅沟槽隔离(shallow trench isolation)的第一沟槽分离区301而绝缘分离。
在源极区201与漏极区202之间的P型的硅衬底101的沟道区的上部隔着由硅氧化膜等构成的栅极绝缘膜401而形成由多晶硅膜等构成的栅极电极402。此外，在ESD保护用的N型MOS晶体管601的衬底电位固定用P型扩散区501与源极区201之间，设置有第二沟槽分离区302。在此第二沟槽分离区302的深度形成得比其它的第一沟槽分离区深。
此外，虽然未作图示，但源极区201电连接成与栅极电极402相同的接地电位(Vss)，由此，ESD保护用的N型MOS晶体管601形成保持截止状态的，所谓的截止晶体管的状态。此外漏极区202与外部连接端子连接。
此外，在图1的例子中为了简洁，只示出由源极区201和漏极区202构成的ESD保护用的N型MOS晶体管，该源极区201和漏极区202由一对N型的高浓度杂质区构成，在实际的ESD保护用的N型MOS晶体管中，为使静电产生的大电流流过而需要较大的晶体管宽度，往往以具有多数源极及漏极区的方式形成。
接着，对构成内部元件的N型MOS晶体管602进行说明。
在作为第一导电型半导体衬底的P型的硅衬底101上，形成有由一对N型的高浓度杂质区构成的源极区201和漏极区202，在与其它元件之间形成浅沟槽隔离的沟槽分离区301而绝缘分离。
在源极区201与漏极区202之间的，形成内部元件的P型硅衬底101上部隔着由硅氧化膜等构成的栅极绝缘膜401而形成由多晶硅膜等构成的栅极电极402。在内部元件即N型MOS晶体管602的衬底电位固定用P型扩散区502与源极区201之间，设置有第一沟槽分离区301。此外，为了简洁，对于内部元件仅图示了N型MOS晶体管602，但在实际的IC中形成有多数P型的MOS晶体管或构成其它半导体电路的要素元件。
接着，一边比较ESD保护用的N型MOS晶体管601和内部元件的N型MOS晶体管602，一边说明本发明的特征。
在ESD保护用的N型MOS晶体管601的衬底电位固定用P型扩散区501与所述ESD保护用的N型MOS晶体管的源极区201及漏极区202之间设置的第二沟槽分离区302的深度，设定为比在内部元件的N型MOS晶体管602的衬底电位固定用P型扩散区502与所述内部元件的N型MOS晶体管的源极及漏极区之间设置的所述沟槽分离区301深。
由此，可以使继续ESD保护用的N型MOS晶体管601的双极动作用的保持电压低于内部元件的N型MOS晶体管602的保持电压，当从外部有大量的电流或脉冲被施加时，能够对ESD保护用的N型MOS晶体管601快速且优先地流过。因此，能够得到包括具有充分的ESD保护功能的ESD保护用的N型MOS晶体管601的半导体装置。
此外，实施例1中为了方便起见，示出ESD保护用的N型MOS晶体管601及内部元件的N型MOS晶体管602为常规结构的情形，但ESD保护用的N型MOS晶体管601及内部元件的N型MOS晶体管602也可以为DDD(Double Diffused Drain：双扩散漏端)结构或偏置漏极(offset drain)结构。
符号的说明
101P型的硅衬底；201源极区；202漏极区；301第一沟槽分离区；302第二沟槽分离区；401栅极氧化膜；402栅极电极；501 ESD保护用的N型的MOS晶体管601的衬底电位固定用P型扩散区；502内部元件的N型MOS晶体管602的衬底电位固定用P型扩散区；601 ESD保护用的N型的MOS晶体管；602内部元件的N型MOS晶体管。

Claims (3)

1.　一种半导体装置，具有沟槽分离区，在内部电路区至少具有内部元件即N型MOS晶体管，在外部连接端子与所述内部电路区之间，具有保护所述内部元件即N型MOS晶体管或其它的内部元件免受ESD造成的破坏的ESD保护用的N型MOS晶体管，其中，在所述ESD保护用的N型MOS晶体管的衬底电位固定用P型扩散区与所述ESD保护用的N型MOS晶体管的源极及漏极区之间设置的所述沟槽分离区的深度，设定为比在所述内部元件即N型MOS晶体管的衬底电位固定用P型扩散区与所述内部元件的N型MOS晶体管的源极及漏极区之间设置的所述沟槽分离区的深度深。
2.如权利要求1所述的半导体装置，其中所述ESD保护用的N型MOS晶体管及所述内部元件的N型MOS晶体管为DDD结构。
3.如权利要求1所述的半导体装置，其中所述ESD保护用的N型MOS晶体管及所述内部元件的N型MOS晶体管为偏置漏极结构。
CN201010297980.8A 2009-09-25 2010-09-21 半导体装置 Expired - Fee Related CN102034812B (zh)

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CN102034812A (zh) 2011-04-27
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US20110073947A1 (en) 2011-03-31

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