CN101373769A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101373769A
CN101373769A CNA2008101611628A CN200810161162A CN101373769A CN 101373769 A CN101373769 A CN 101373769A CN A2008101611628 A CNA2008101611628 A CN A2008101611628A CN 200810161162 A CN200810161162 A CN 200810161162A CN 101373769 A CN101373769 A CN 101373769A
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metal oxide
semiconductor device
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CN101373769B (zh
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鹰巢博昭
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Ablic Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及一种半导体器件。在包括由用于器件隔离的浅沟槽包围的用于静电放电保护的n型金属氧化物半导体晶体管的半导体器件中，为了抑制处于关断状态的关断泄露电流，在用于ESD保护的n型金属氧化物半导体晶体管的漏极区附近，形成经过与用于ESD保护的NMOS晶体管的所述漏极区接触的p型区的从外部连接端子接收信号的n型区。

Description

半导体器件
技术领域
本发明涉及包括金属氧化物半导体(MOS)晶体管的半导体器件。特别地，本发明涉及包括作为静电放电(下文称为ESD)保护元件的由浅沟槽结构隔离的n型MOS(NMOS)晶体管。
背景技术
在包括MOS晶体管的半导体器件中，一不导通晶体管被用作ESD保护元件用于防止由于由用于外部连接的焊盘的静电而导致的内部电路的击穿，该不导通晶体管是其栅极电位被固定在地(Vss)的处于不导通状态的NMOS晶体管。
由于不像形成例如逻辑电路的内部电路的普通MOS晶体管，所述不导通晶体管必须立即流过由静电产生的大量的电流，所以在很多情况下对于所述晶体管需要大约几百微米的大的宽度(宽度W)。
虽然所述不导通晶体管的栅极电位被固定在Vss以保持所述不导通晶体管处于不导通的状态，但是如在构成所述内部电路的NMOS晶体管中域值电压小于1V，某种程度上允许亚域值电流的产生。如上所述该不导通晶体管的宽度W大，并因此在工作中处于待机的关断漏泄电流变得更大，其导致了在带有所述不导通晶体管的整个集成电路(IC)的工作期间处于待机时电流损耗增加的问题。
特别是，在使用浅沟槽作为器件隔离的半导体器件的情况下，存在一个问题，邻近所述浅沟槽的区域包括例如由结构本身或其制造方法产生的易于产生漏泄电流的晶体缺陷层等的区域，因此难于减小所述不导通晶体管的关断漏泄电流。
作为减少所述保护元件的漏泄电流的方法，提出了在电源线(Vdd)和地(Vss)之间提供多个晶体管以便完全地切断其间的电流通路(例如，参见JP2002-231886A的图1)。
然而，当使得所述宽度W变小以减小所述不导通晶体管的关断漏泄电流时，保护功能不能被充分地实现。除此之外，在如JP2002-231886A提出的提供有多个晶体管以切断在电源线(Vdd)和地(Vss)之间的电流通路的半导体器件中，由于半导体器件包括多个晶体管，其占据的面积增加，导致了半导体器件成本的增加。
发明内容
为了解决上述问题，根据本发明的半导体器件如下构造。
在包括由用于器件隔离的浅沟槽环绕的用于静电放电保护的n型金属氧化物半导体晶体管的半导体器件中，用于静电放电保护的n型金属氧化物半导体晶体管形成在外部连接端子和内部电路区之间，以保护形成在内部电路区中的内部元件免于静电放电击穿，所述用于静电放电保护的n型金属氧化物半导体晶体管包括n型区，所述n型区以通过和所述漏极区相接触的p型区与所述漏极区分离的方式，布置在用于静电放电保护的n型金属氧化物半导体晶体管与栅电极相对的漏极区一侧上，并且从所述外部连接端子接收信号。
进一步，和所述用于ESD保护的NMOS晶体管的漏极区接触的p型区形成为具有一宽度，当等于或高于所述半导体器件的电源电压的电压施加在从外部连接端子接收信号的n型区时，其允许从所述外部连接端子接收信号的所述n型区通过穿通与用于ESD保护的NMOS晶体管的所述漏极区导通。
进一步，所述从外部连接端子接收信号的n型区以经过所述p型区由用于ESD保护的NMOS晶体管的漏极区包围的形状形成。
通过上述方法，可以获得一半导体器件，其包括用于ESD保护的NMOS晶体管，该NMOS晶体管提供有充分的ESD保护功能同时通过阻止所述漏泄电流特征到所述浅沟槽隔离的产生或通过避免产生漏泄电流的区域来保持所述关断漏泄电流小，而不增加制造步骤或其占据的面积。
附图说明
在附图中：
图1为示出了根据本发明第一实施例的半导体器件的用于ESD保护的NMOS晶体管的示意平面图；以及
图2为示出了根据本发明第二实施例的半导体器件的用于ESD保护的NMOS晶体管的示意平面图。
具体实施方式
(第一实施例)
图1为示出了根据本发明第一实施例的半导体器件的用于ESD保护的NMOS晶体管的示意平面图。
由n型重掺杂区形成的一对源极区501和漏极区503布置在p型半导体衬底上，由氧化硅膜等形成的栅极绝缘膜(未示出)置于所述源极区501和所述漏极区503之间，并且由多晶硅等形成的栅极电极502形成在所述栅极绝缘膜的上表面上。一浅沟槽结构被用于与其他元件的绝缘，并且晶体管的周界由浅沟槽隔离区504包围。
在图1的实施例中，示出了两个栅极电极502，以及分别置于所述栅极电极502每一侧上的两对源极区501和漏极区503。在漏极区503附近，经过与所述漏极区503接触的p型区602形成有从外部连接端子接收信号的n型区601。在这种情况下，所述p型区602形成为具有一宽度，当超过所述半导体器件的电源电压的电压施加到所述n型区601时，该宽度允许通过从外部连接接收信号的n型区601和所述漏极区503之间通过穿通的导通。在该实施例中，两个用于ESD保护的NMOS晶体管对称地提供有作为其中心的n型区601。也可能非对称地仅提供一个用于ESD保护的NMOS晶体管。
适当地结合在所述p型区602中的p型杂质浓度和所述p型区602的宽度，可以在所要施加的电压下形成在从外部连接端子接收信号的n型区601和所述漏极区503之间的穿通。在电压不高于所述电源电压的信号在半导体器件的正常工作过程中被施加到外部端子的状态下，如上所述选择所述p型区602的宽度，n型区601和漏极区503通过相反导电性的p型区602电性分离。因此，施加到外部端子的信号(电压)不会传输到用于ESD保护的NMOS晶体管的漏极区503，允许实质上防止用于ESD保护的NMOS的关断漏泄电流的产生。
另一方面，到外部连接端子的大电压(例如静电脉冲)的施加开始了由在从外部连接端子接收信号的n型区601和漏极区503之间的穿通引起的导电，导致用于ESD保护的NMOS晶体管的双极作用以充分地实现对内部电路元件的保护功能。
(第二实施例)
图2为示出了根据本发明第二实施例的半导体器件的用于ESD保护的NMOS晶体管的示意图。第二实施例不同于图1所示的第一实施例，在于从外部连接端子接收信号的n型区601完全被p型区602包围。
借助这种结构，从外部连接端子接收信号的n型区601没有与浅沟槽隔离区504接触的部分，因此不担心在邻近所述浅沟槽隔离区504的部分中漏泄电流，与图1所示的第一实施例相比较，其能够更有效地阻止漏泄电流的产生。其他部分由如图1的相同的参考标记标明，因此省略了它们的说明。
图1和图2的实施例示出了用于ESD保护的NMOS晶体管的例子，该用于ESD保护的NMOS晶体管为了简单而具有常规结构，但是本发明不限于此。无需说明的是本发明可以通过使用例如轻掺杂漏极(LDD)结构或者其中漏极区503与栅极电极502离开一定的宽度的偏移漏极结构而容易地实现。

Claims (6)

1.一种半导体器件，包括：
布置在半导体衬底上的用于静电放电保护的n型金属氧化物半导体晶体管，其置于外部连接端子和内部电路区之间以便布置在所述内部电路区中的内部元件被保护免于静电放电击穿；
p型区，布置在所述半导体衬底上与所述n型金属氧化物半导体晶体管的漏极区接触；
n型区，置于所述漏极区与所述n型金属氧化物半导体晶体管的栅极电极相对的侧上，通过所述p型区与所述漏极区分离，并从所述外部连接端子接收信号；以及
浅沟槽区，围绕所述n型金属氧化物半导体晶体管、所述p型区、以及所述n型区用于隔离。
2.根据权利要求1的半导体器件，其中所述p型区具有一宽度，该宽度允许当比所述半导体器件的电源电压高的电压施加到所述n型区时所述n型区和所述漏极之间的穿通引起的导通。
3.根据权利要求1的半导体器件，其中所述n型区完全由所述p型区包围。
4.根据权利要求1的半导体器件，其中多个用于静电放电保护的n型金属氧化物半导体晶体管相对于作为中心的所述n型区对称地布置。
5.根据权利要求1的半导体器件，其中用于静电放电保护的所述n型金属氧化物半导体晶体管为具有轻掺杂漏极结构的n型金属氧化物半导体晶体管。
6.根据权利要求1的半导体器件，其中用于静电放电保护的n型金属氧化物半导体晶体管为具有偏移漏极结构的n型金属氧化物半导体晶体管。
CN2008101611628A 2007-08-22 2008-08-22 半导体器件 Expired - Fee Related CN101373769B (zh)

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JP2011071329A (ja) * 2009-09-25 2011-04-07 Seiko Instruments Inc 半導体装置
JP2011071325A (ja) * 2009-09-25 2011-04-07 Seiko Instruments Inc 半導体装置
JP5546191B2 (ja) * 2009-09-25 2014-07-09 セイコーインスツル株式会社 半導体装置
JP5511353B2 (ja) * 2009-12-14 2014-06-04 セイコーインスツル株式会社 半導体装置
JP6656968B2 (ja) 2016-03-18 2020-03-04 エイブリック株式会社 Ｅｓｄ保護素子を有する半導体装置
JP7193053B2 (ja) * 2018-07-18 2022-12-20 株式会社東海理化電機製作所 半導体装置及びその製造方法

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JPH01243586A (ja) * 1988-03-25 1989-09-28 Hitachi Ltd 半導体装置
JPH1168043A (ja) * 1997-08-27 1999-03-09 Kawasaki Steel Corp Ｅｓｄ保護回路
JP3244065B2 (ja) * 1998-10-23 2002-01-07 日本電気株式会社 半導体静電保護素子及びその製造方法
JP2001168204A (ja) * 1999-12-13 2001-06-22 Toshiba Corp 半導体装置及びその製造方法
JP2002231886A (ja) 2001-01-31 2002-08-16 Matsushita Electric Ind Co Ltd Ｅｓｄ保護回路および半導体集積回路装置
US7217984B2 (en) * 2005-06-17 2007-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Divided drain implant for improved CMOS ESD performance
JP5078312B2 (ja) * 2005-10-19 2012-11-21 セイコーインスツル株式会社 半導体集積回路装置およびその製造方法

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TWI450380B (zh) 2014-08-21
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TW200929522A (en) 2009-07-01
US8283725B2 (en) 2012-10-09
KR20090020531A (ko) 2009-02-26
US20090050967A1 (en) 2009-02-26
JP2009049296A (ja) 2009-03-05
KR101566024B1 (ko) 2015-11-04

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