TWI450380B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TWI450380B TWI450380B TW097130993A TW97130993A TWI450380B TW I450380 B TWI450380 B TW I450380B TW 097130993 A TW097130993 A TW 097130993A TW 97130993 A TW97130993 A TW 97130993A TW I450380 B TWI450380 B TW I450380B
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- 239000004065 semiconductor Substances 0.000 title claims description 59
- 229910044991 metal oxide Inorganic materials 0.000 claims description 25
- 150000004706 metal oxides Chemical class 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
本發明係有關於包括金屬氧化物半導體(MOS)電晶體的半導體裝置。更特別而言,本發明係有關於藉由作為靜電放電(之後,稱為ESD)保護元件的淺渠溝結構所隔離之包括n型MOS(NMOS)電晶體的半導體裝置。
在包括MOS電晶體的半導體裝置中,截止電晶體(其為處於閘極電位係固定於地(VSS
)的截止狀態中之NMOS電晶體)係使用來作為用於防止由於自設置用於外部連接之焊墊所供應的靜電而導致之內部電路的擊穿之ESD保護元件。
因為與形成如邏輯電路的內部電路之一般MOS電晶體不同的是,截止電晶體必須立即使靜電所產生的大量電流流動,所以在許多情況中,電晶體需要約數百微米的大寬度(寬度W)。
雖然截止電晶體的閘極電位係固定於VSS
,以使截止電晶體保持於截止狀態,但是如在構成內部電路的NMOS電晶體中,臨界電壓小於1V,而容許次電流產生至某種程度。如以上所述,截止電晶體的寬度W是大的,因此在運作期間,待機的截止漏電流變成較大,這導致在含有截止電晶體的整個積體電路(IC)之運作期間,待機的電流消耗增加之問題。
特別而言,在淺渠溝係使用於裝置隔離的半導體裝置之情況中,有包括容易產生漏電流(起因於結構本身或其製造方法)之如晶體缺陷層或類似的區域之與淺渠溝相鄰的區域,因此難以降低截止電晶體的截止漏電流之問題。
就降低保護元件的漏電流之測量而言,提出在電源線(Vdd
)與地(Vss
)之間設置複數個電晶體,以完全切割其間的電流路徑(例如,見JP 2002-231886A的圖1)。
然而,當寬度W變小,以降低截止電晶體的截止漏電流時。不能充分地實施保護功能。此外,在複數個電晶體係設置為如JP 2002-231886A中所提出之切割電源線(Vdd
)與地(Vss
)之間的電流路徑之半導體裝置中,因為半導體裝置包括複數個電晶體,所以其佔據面積增加,而導致半導體裝置的成本增加。
為了解決以上所提及的問題,根據本發明的半導體裝置係建構如下。
在包括由用於裝置隔離的淺渠溝所圍繞之用於靜電放電保護的n型金屬氧化物半導體電晶體之半導體裝置中,用於靜電放電保護的n型金屬氧化物半導體電晶體係形成於外部連接端點與內部電路區域之間,使得保護形成於內部電路區域中的內部元件免於靜電放電擊穿,用於靜電放電保護的n型金屬氧化物半導體電晶體包括n型區域,n型區域係藉由與汲極區域相接觸的p型區域而與汲極區域分離的方式,而設置於與閘極電極相對之用於靜電放電保護的n型金屬氧化物半導體電晶體之汲極區域的一側,且接收來自外部連接端點的訊號。
另外,當等於或大於此半導體裝置的供應電源電壓之電壓係施加於接收來自外部連接端點的訊號之n型區域時,與用於ESD保護的NMOS電晶體之汲極區域相接觸的p型區域係形成具有使接收來自外部連接端點的訊號之n型區域能經由衝穿而與用於ESD保護的NMOS電晶體之汲極區域導通的此種寬度。
另外,接收來自外部連接端點的訊號之n型區域係以藉由經由p型區域之用於ESD保護的NMOS電晶體之汲極區域所圍繞的形式而形成。
經由如上述的手段,可藉由防止淺渠溝隔離的漏電流特徵之產生,或藉由避免產生漏電流的區域,得到具有充分ESD保護功能之包括用於ESD保護的NMOS電晶體之半導體裝置,而不會增加其製造步驟或佔據面積。
圖1係顯示根據本發明之第一實施例的半導體裝置之用於ESD保護的NMOS電晶體之概要平面圖。
由n型重摻雜雜質區域所構成的一對源極區域501及汲極區域503係配置於p型半導體基板上,由氧化矽膜或類似所製成的閘極絕緣膜(未顯示)係設置在源極區域501與汲極區域503之間,而由多晶矽或類似所製成的閘極電極502係形成於閘極絕緣膜的上表面上。淺渠溝結構係使用於與其他元件的絕緣,且電晶體的周圍係由淺渠溝隔離區域504所圍繞。
在圖1的實施例中,顯示兩個閘極電極502,及兩對源極區域501及汲極區域503中的每一個係設置於閘極電極502的任一側上。在汲極區域503的附近,形成經由與汲極區域503相接觸的p型區域602,接收來自外部連接端點的訊號之n型區域601。在此情況中,當超過此半導體裝置的電源供應電壓之電壓係施加於n型區域601時,p型區域602係形成具有能經由接收來自外部連接端點的訊號之n型區域601與汲極區域503之間的穿透而導通之此種寬度。在此實施例中,兩個用於ESD保護的NMOS電晶體係以n型區域601為其中心而對稱地設置。也可僅設置一個用於ESD保護的NMOS電晶體,而不對稱。
適當地將p型區域602中的p型雜質濃度與p型區域602的寬度結合,接收來自外部連接端點的訊號之n型區域601與汲極區域503之間的穿透可以想要施加的電壓實施。如以上所述選擇p型區域602的寬度,在此半導體裝置的正常運作期間,不大於電源供應電壓之電壓的訊號係施加於外部端點之狀態中,n型區域601與汲極區域503係藉由相反導電性的p型區域602來予以電性隔離。因此,施加於外部端點的訊號(電壓)不會傳送至用於ESD保護的NMOS電晶體之汲極區域503,而容許用於ESD保護的NMOS電晶體之截止漏電流的產生之基本防護。
另一方面,外部連接端點之大電壓(例如,靜電脈衝)的施加啟動因接收來自外部連接端點的訊號之n型區域601與汲極區域503之間的穿透所啟始的導通,而導致用於ESD保護的NMOS電晶體之雙載子動作,以充分地實施內部電路元件的保護功能。
圖2係顯示根據本發明之第二實施例的半導體裝置之用於ESD保護的NMOS電晶體之概要平面圖。第二實施例與圖1中所顯示的第一實施例之差異在於接收來自外部連接端點的訊號之n型區域601係完全由p型區域602所包圍。
具有此結構,接收來自外部連接端點的訊號之n型區域601沒有與淺渠溝隔離區域504相接觸的部分,因此不用擔心與淺渠溝隔離區域504相鄰的部分之漏電流,與圖1中所顯示的第一實施例相較,這樣可更有效地防止漏電流的產生。其他的部分係藉由與圖1相同的參考標號所表示,因此省略其說明。
為了簡化起見,圖1及圖2的實施例顯示具有習知結構之用於ESD保護的NMOS電晶體之例子,但是本發明不受限於此。不需說的是,本發明可藉由使用汲極區域503與閘極電極502相距某種寬度之如輕摻雜汲極(LDD)結構或偏移汲極結構的電晶體結構來予以輕易地實施。
501...源極區域
502...閘極電極
503...汲極區域
504...淺渠溝隔離區域
601...n型區域
602...p型區域
在附圖中:
圖1係顯示根據本發明之第一實施例的半導體裝置之用於ESD保護的NMOS電晶體之概要平面圖;以及
圖2係顯示根據本發明之第二實施例的半導體裝置之用於ESD保護的NMOS電晶體之概要平面圖。
501...源極區域
502...閘極電極
503...汲極區域
504...淺渠溝隔離區域
601...n型區域
602...p型區域
Claims (8)
- 一種半導體裝置,包含:n型金屬氧化物半導體電晶體,用於靜電放電保護,設置於半導體基板上,位於外部連接端點與內部電路區域之間,使得保護設置於該內部電路區域中的內部元件免於靜電放電擊穿;p型區域,係設置於該半導體基板上,與該n型金屬氧化物半導體電晶體的汲極區域的一側相接觸,即,相對於該n型金屬氧化物半導體電晶體的閘極電極,該汲極區域於該閘極電極及該p型區域之間;n型區域,係設置與該n型金屬氧化物半導體電晶體的該閘極電極相對之該汲極區域分離,藉由該p型區域而與該汲極區域完全隔離,未具有經由另一n型區域至該汲極區域的連接,且組構為接收來自該外部連接端點的訊號;以及淺渠溝區域,圍繞該n型金屬氧化物半導體電晶體、該p型區域、及該n型區域,作為隔離之用。
- 如申請專利範圍第1項之半導體裝置,其中當高於該半導體裝置的電源供應電壓之電壓係施加於該n型區域時,該p型區域具有能藉由該n型區域與該汲極區域之間的衝穿所啟始之導通的寬度。
- 如申請專利範圍第1項之半導體裝置,其中該n型區域完全由該p型區域所包圍。
- 如申請專利範圍第1項之半導體裝置,其中用於 靜電放電保護的複數個該n型金屬氧化物半導體電晶體係對於作為中心的該n型區域對稱地設置。
- 如申請專利範圍第1項之半導體裝置,其中用於靜電放電保護的該n型金屬氧化物半導體電晶體為具有輕摻雜汲極結構的n型金屬氧化物半導體電晶體。
- 如申請專利範圍第1項之半導體裝置,其中用於靜電放電保護的該n型金屬氧化物半導體電晶體為具有偏移汲極結構的n型金屬氧化物半導體電晶體。
- 一種半導體裝置,包含:第一n型金屬氧化物半導體電晶體及第二n型金屬氧化物半導體電晶體,用於靜電放電保護,設置於半導體基板上;第一p型區域,係設置於該半導體基板上,與該第一n型金屬氧化物半導體電晶體的汲極區域的一側相接觸,即,相對於該第一n型金屬氧化物半導體電晶體的閘極電極;第二p型區域,係設置於該半導體基板上,與該第二n型金屬氧化物半導體電晶體的汲極區域的一側相接觸,即,相對於該第二n型金屬氧化物半導體電晶體的閘極電極;以及n型區域,係於該第一p型區域及該第二p型區域之間,與各該第一n型金屬氧化物半導體電晶體及該第二n型金屬氧化物半導體電晶體的該汲極區域完全隔離,未具有經由另一n型區域至該汲極區域的連接,且組構為接收 來自該外部連接端點的訊號。
- 如申請專利範圍第7項之半導體裝置,進一步包含淺渠溝區域,圍繞該第一n型金屬氧化物半導體電晶體、該第二n型金屬氧化物半導體電晶體、該第一p型區域、該第二p型區域、及該n型區域,作為隔離之用。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007215948A JP5270877B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200929522A TW200929522A (en) | 2009-07-01 |
TWI450380B true TWI450380B (zh) | 2014-08-21 |
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Application Number | Title | Priority Date | Filing Date |
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TW097130993A TWI450380B (zh) | 2007-08-22 | 2008-08-14 | 半導體裝置 |
Country Status (5)
Country | Link |
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US (1) | US8283725B2 (zh) |
JP (1) | JP5270877B2 (zh) |
KR (1) | KR101566024B1 (zh) |
CN (1) | CN101373769B (zh) |
TW (1) | TWI450380B (zh) |
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JP5546191B2 (ja) * | 2009-09-25 | 2014-07-09 | セイコーインスツル株式会社 | 半導体装置 |
JP2011071325A (ja) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | 半導体装置 |
JP2011071329A (ja) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | 半導体装置 |
JP5511353B2 (ja) * | 2009-12-14 | 2014-06-04 | セイコーインスツル株式会社 | 半導体装置 |
JP6656968B2 (ja) | 2016-03-18 | 2020-03-04 | エイブリック株式会社 | Esd保護素子を有する半導体装置 |
JP7193053B2 (ja) * | 2018-07-18 | 2022-12-20 | 株式会社東海理化電機製作所 | 半導体装置及びその製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060284258A1 (en) * | 2005-06-17 | 2006-12-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Divided drain implant for improved CMOS ESD performance |
TW200731418A (en) * | 2005-10-19 | 2007-08-16 | Seiko Instr Inc | A semiconductor integrated circuit device and a manufacturing method for the same |
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JPH01243586A (ja) * | 1988-03-25 | 1989-09-28 | Hitachi Ltd | 半導体装置 |
JPH1168043A (ja) * | 1997-08-27 | 1999-03-09 | Kawasaki Steel Corp | Esd保護回路 |
JP3244065B2 (ja) * | 1998-10-23 | 2002-01-07 | 日本電気株式会社 | 半導体静電保護素子及びその製造方法 |
JP2001168204A (ja) * | 1999-12-13 | 2001-06-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002231886A (ja) | 2001-01-31 | 2002-08-16 | Matsushita Electric Ind Co Ltd | Esd保護回路および半導体集積回路装置 |
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- 2008-08-14 US US12/191,674 patent/US8283725B2/en active Active
- 2008-08-22 CN CN2008101611628A patent/CN101373769B/zh not_active Expired - Fee Related
- 2008-08-22 KR KR1020080082595A patent/KR101566024B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060284258A1 (en) * | 2005-06-17 | 2006-12-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Divided drain implant for improved CMOS ESD performance |
TW200731418A (en) * | 2005-10-19 | 2007-08-16 | Seiko Instr Inc | A semiconductor integrated circuit device and a manufacturing method for the same |
Also Published As
Publication number | Publication date |
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KR101566024B1 (ko) | 2015-11-04 |
KR20090020531A (ko) | 2009-02-26 |
JP2009049296A (ja) | 2009-03-05 |
US20090050967A1 (en) | 2009-02-26 |
CN101373769B (zh) | 2012-07-04 |
CN101373769A (zh) | 2009-02-25 |
US8283725B2 (en) | 2012-10-09 |
JP5270877B2 (ja) | 2013-08-21 |
TW200929522A (en) | 2009-07-01 |
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