JP2008205053A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2008205053A JP2008205053A JP2007037226A JP2007037226A JP2008205053A JP 2008205053 A JP2008205053 A JP 2008205053A JP 2007037226 A JP2007037226 A JP 2007037226A JP 2007037226 A JP2007037226 A JP 2007037226A JP 2008205053 A JP2008205053 A JP 2008205053A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
【解決手段】トレンチ分離構造を有し、高電源電圧回路部には少なくとも一つのウエル領域とMOS型トランジスタ、及び各素子を電気的に接続する配線を有する半導体装置において、ウエル領域の端部近傍のトレンチ分離領域の上部であって配線の下部である領域に、配線の電位によって、寄生的に形成される反転層の発生を防止するための反転層形成防止電極を形成し、電位は、その下部に位置する半導体基板の電位と同一にした。さらに反転層形成防止電極の下部には、半導体基板と同じ導電型の濃い不純物濃度領域からなるガードリング領域を設置し、半導体基板の電位を強固に固定し、またバイポーラ動作発生時においてキャリアを捕獲してラッチアップを防止できるようにした。
【選択図】なし
Description
またNウエル領域202の表面には第1の絶縁膜601を介して形成されたP型反転層形成防止電極702の下部に、P型反転層形成防止電極702とコンタクト領域411を介して電気的に接続された、Nウエル202の電位を強固に固定し、バイポーラ動作発生時においてキャリアを捕獲してラッチアップを防止するための、Nウエル202と同じ導電型の濃い不純物濃度領域からなるN型ガードリング領域422が形成されている点である。
201 Pウエル領域
202 Nウエル領域
301 トレンチ分離領域
411 コンタクト領域
421 P型ガードリング領域
422 N型ガードリング領域
501 N型の高濃度不純物領域
502 P型の高濃度不純物領域
601 第1の絶縁膜
701 N型反転層形成防止電極
702 P型反転層形成防止電極
801 第2の絶縁膜
901 配線
Claims (8)
- 半導体基板上に高電源電圧回路部と低電源電圧回路部とを有し、前記高電源電圧回路部および前記低電源電圧回路部における各素子をトレンチ分離領域により素子分離したトレンチ分離構造を有し、前記高電源電圧回路部には少なくとも一つのウエル領域とMOS型トランジスタ、及び各素子を電気的に接続する配線を有する半導体装置において、前記ウエル領域の端部近傍に配置された前記トレンチ分離領域の上部であって、前記配線の下部である領域に、前記配線の電位によって前記半導体基板の表面に寄生的に形成される反転層の発生を防止するための反転層形成防止電極が配置されていることを特徴とする半導体装置。
- 前記高電源電圧回路部は、第1導電型半導体基板と、第1導電型の第1ウエル及び第2導電型の第2ウエルから成り、前記第1ウエルと前記第2ウエルの接合部において、前記第1ウエルと前記第2ウエルのそれぞれの端部であって、前記トレン分離領域の上部であって配線の下部である領域に、前記反転層形成防止電極を有する請求項1記載の半導体装置。
- 前記第1ウエル上に形成された前記反転層形成防止電極の電位は、前記第1ウエルと等しく、前記第2ウエル上に形成された前記反転層形成防止電極の電位は、前記第2ウエルの電位と等しくされていることを特徴とする請求項2記載の半導体装置。
- 前記第1ウエル上に形成された前記反転層形成防止電極の下部には、前記第1ウエル上に形成された前記反転層形成防止電極と電気的に接続された、前記第1ウエルの電位を強固に固定し、またバイポーラ動作発生時においてキャリアを捕獲してラッチアップを防止するための、第1ウエルと同じ導電型の濃い不純物濃度領域からなるガードリング領域を有し、前記第2ウエル上に形成された前記反転層形成防止電極の下部には、前記第2ウエル上に形成された前記反転層形成防止電極と電気的に接続された、前記第2ウエルの電位を強固に固定し、またバイポーラ動作発生時においてキャリアを捕獲してラッチアップを防止するための、第2ウエルと同じ導電型の濃い不純物濃度領域からなるガードリング領域を有することを特徴とする請求項2記載の半導体装置。
- 前記高電源電圧回路部は、第1導電型半導体基板と、第2導電型の第2ウエルからなり、前記第1導電型半導体基板と第2ウエルの接合部付近において、前記第1導電型半導体基板と前記第2ウエルのそれぞれの端部であって、前記トレン分離領域の上部であって配線の下部である領域に、前記反転層形成防止電極を有することを特徴とする請求項1記載の半導体装置。
- 前記第1導電型半導体基板上に形成された前記反転層形成防止電極の電位は前記第1導電型半導体基板と等しく、前記第2ウエル上に形成された前記反転層形成防止電極の電位は、前記第2ウエルの電位と等しいことを特徴とする請求項5記載の半導体装置。
- 前記第1導電型半導体基板上に形成された前記反転層形成防止電極の下部には、前記第1導電型半導体基板上に形成された前記反転層形成防止電極と電気的に接続された、前記第1導電型半導体基板の電位を強固に固定し、またバイポーラ動作発生時においてキャリアを捕獲してラッチアップを防止するための、第1導電型半導体基板と同じ導電型の濃い不純物濃度領域からなるガードリング領域を有し、前記第2ウエル上に形成された前記反転層形成防止電極の下部には、前記第2ウエル上に形成された前記反転層形成防止電極と電気的に接続された、前記第2ウエルの電位を強固に固定し、またバイポーラ動作発生時においてキャリアを捕獲してラッチアップを防止するための、第2ウエルと同じ導電型の濃い不純物濃度領域からなるガードリング領域を有することを特徴とする請求項5記載の半導体装置。
- 前記反転層形成防止電極は、前記高電源電圧回路部に形成された前記MOS型トランジスタのゲート電極と同一の薄膜によって形成されていることを特徴とする請求項1ないし7のいずれか1項に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007037226A JP2008205053A (ja) | 2007-02-17 | 2007-02-17 | 半導体装置 |
US12/070,132 US7880240B2 (en) | 2007-02-17 | 2008-02-15 | Semiconductor device |
CN2008100966666A CN101271900B (zh) | 2007-02-17 | 2008-02-18 | 半导体器件 |
KR1020080014460A KR101442252B1 (ko) | 2007-02-17 | 2008-02-18 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007037226A JP2008205053A (ja) | 2007-02-17 | 2007-02-17 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
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JP2008205053A true JP2008205053A (ja) | 2008-09-04 |
Family
ID=39705909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007037226A Withdrawn JP2008205053A (ja) | 2007-02-17 | 2007-02-17 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7880240B2 (ja) |
JP (1) | JP2008205053A (ja) |
KR (1) | KR101442252B1 (ja) |
CN (1) | CN101271900B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5546191B2 (ja) * | 2009-09-25 | 2014-07-09 | セイコーインスツル株式会社 | 半導体装置 |
US8492866B1 (en) | 2012-01-09 | 2013-07-23 | International Business Machines Corporation | Isolated Zener diode |
US20230317722A1 (en) * | 2022-03-24 | 2023-10-05 | International Business Machines Corporation | Size-efficient mitigation of latchup and latchup propagation |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61248459A (ja) * | 1985-04-25 | 1986-11-05 | Nippon Telegr & Teleph Corp <Ntt> | 相補形mis半導体集積回路 |
JPH0492449A (ja) * | 1990-08-07 | 1992-03-25 | Seiko Epson Corp | 半導体装置 |
JP2000150806A (ja) * | 1998-11-16 | 2000-05-30 | Sharp Corp | 半導体装置及びその製造方法 |
JP2002009277A (ja) * | 2000-06-20 | 2002-01-11 | Oki Electric Ind Co Ltd | オフセットゲート型電界効果トランジスタ及び半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4654958A (en) * | 1985-02-11 | 1987-04-07 | Intel Corporation | Process for forming isolated silicon regions and field-effect devices on a silicon substrate |
JPH02172253A (ja) * | 1988-12-24 | 1990-07-03 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
KR0149256B1 (ko) * | 1995-08-25 | 1998-10-01 | 김주용 | 씨모스 트랜지스터 제조방법 |
JP2000058673A (ja) | 1998-08-14 | 2000-02-25 | Nec Corp | トレンチ分離構造を有する半導体装置 |
US6232165B1 (en) * | 1998-12-09 | 2001-05-15 | Winbond Electronics Corporation | Buried guard rings and method for forming the same |
GB2367945B (en) * | 2000-08-16 | 2004-10-20 | Secr Defence | Photodetector circuit |
JP3531808B2 (ja) * | 2000-10-31 | 2004-05-31 | シャープ株式会社 | 保護回路および半導体装置 |
JP4895430B2 (ja) * | 2001-03-22 | 2012-03-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
JP4898024B2 (ja) * | 2001-06-21 | 2012-03-14 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
CN1564318A (zh) * | 2004-03-26 | 2005-01-12 | 清华大学 | 0.35μm LDMOS高压功率显示驱动器件的设计方法 |
US7091079B2 (en) * | 2004-11-11 | 2006-08-15 | United Microelectronics Corp. | Method of forming devices having three different operation voltages |
JP4845410B2 (ja) * | 2005-03-31 | 2011-12-28 | 株式会社リコー | 半導体装置 |
-
2007
- 2007-02-17 JP JP2007037226A patent/JP2008205053A/ja not_active Withdrawn
-
2008
- 2008-02-15 US US12/070,132 patent/US7880240B2/en not_active Expired - Fee Related
- 2008-02-18 CN CN2008100966666A patent/CN101271900B/zh not_active Expired - Fee Related
- 2008-02-18 KR KR1020080014460A patent/KR101442252B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61248459A (ja) * | 1985-04-25 | 1986-11-05 | Nippon Telegr & Teleph Corp <Ntt> | 相補形mis半導体集積回路 |
JPH0492449A (ja) * | 1990-08-07 | 1992-03-25 | Seiko Epson Corp | 半導体装置 |
JP2000150806A (ja) * | 1998-11-16 | 2000-05-30 | Sharp Corp | 半導体装置及びその製造方法 |
JP2002009277A (ja) * | 2000-06-20 | 2002-01-11 | Oki Electric Ind Co Ltd | オフセットゲート型電界効果トランジスタ及び半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101271900B (zh) | 2012-03-21 |
US20080197425A1 (en) | 2008-08-21 |
CN101271900A (zh) | 2008-09-24 |
KR20080077052A (ko) | 2008-08-21 |
KR101442252B1 (ko) | 2014-09-23 |
US7880240B2 (en) | 2011-02-01 |
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