CN101271900A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101271900A
CN101271900A CNA2008100966666A CN200810096666A CN101271900A CN 101271900 A CN101271900 A CN 101271900A CN A2008100966666 A CNA2008100966666 A CN A2008100966666A CN 200810096666 A CN200810096666 A CN 200810096666A CN 101271900 A CN101271900 A CN 101271900A
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鹰巢博昭
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Ablic Inc
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Abstract

本发明涉及一种半导体器件。该半导体器件具有沟槽隔离结构和包含至少一个阱区域、MOS晶体管和用于电连接各个元件的互连的高压电路部分。用于防止反型层形成的电极形成靠近该阱区域的端部的该沟槽隔离区域之上并且在该互连之下的区域中，用于防止由于该互连的电位在该半导体衬底的表面上的反型层的寄生形成，并且固定在与其下的该半导体衬底相同的电位。此外，保护环区域由与该半导体衬底相同的导电类型的重掺杂杂质区域形成，其被设置在用于防止反型层形成的该电极之下并且固定在与该半导体衬底相同的电位以俘获载流子从而防止闩锁。

Description

半导体器件
 发明背景
1.技术领域
本发明涉及一种具有沟槽隔离结构的半导体器件，其应用于具有多电源电压的CMOS器件等。
2.背景技术
在具有使用多电源电压的CMOS器件的半导体器件中，提高形成诸如逻辑电路的内部电路的低压部分的集成度并且同时防止在器件隔离区域形成寄生晶体管以确保(secure)用于输入/输出电路等的高压部分的闩锁电阻(latch-upresistance)是重要的。
近年来，器件隔离通过沟槽隔离来实现，其在很多情况下比LOCOS隔离更适合用于更高的集成度。然而在LOCOS中，可以容易地形成用于防止寄生沟道的重掺杂杂质区域(即所谓的沟道截断区域或者场掺杂区域)以防止半导体衬底的反型(inversion)，并且因此，用于高压电路的器件隔离特性是很好的。另一方面，其中沟槽隔离被用于器件隔离的半导体器件存在的问题是，由于在沟槽隔离区域之上通过的互连的电位，因为寄生反型层形成在沟槽隔离区域下部的半导体衬底的表面上很容易形成寄生沟道，导致尤其形成了高压电源电路部分这样的问题。
现在参考图3来描述反型层和寄生沟道的形成和由于反型层和寄生沟道的形成而导致的闩锁。
图3是示出常规半导体器件的高压电路部分的一部分的横截面示意图。
作为第一阱区域的p型轻掺杂杂质区域的p阱区域201和作为第二阱区域的n型轻掺杂杂质区域的n阱区域202并排形成在作为第一导电类型的半导体衬底的p型硅衬底101上。作为n型MOS晶体管的源极区域和/或漏极区域的n型重掺杂杂质区域501例如形成在p阱区域201的表面上，而作为p型MOS晶体管的源极区域和/或漏极区域的p型重掺杂杂质区域502例如形成在n阱区域202的表面上。用于器件隔离的沟槽隔离区域301形成在n型重掺杂杂质区域501和p型重掺杂杂质区域502之间。由铝等形成的用于电连接各个元件的互连901通过是氧化硅膜等的第一绝缘膜601布置在其上。
在例如使用电源电压为30V的高压电路中，有时将30V的电位施加到互连901上。由于p阱区域201的电位固定在接地电平(0V)，n型反型层911容易形成在p阱区域201中的沟槽隔离区域301的下面。然后，由n型重掺杂杂质区域501、n型反型层911和n阱区域202形成的寄生晶体管被置于导电以容许开态电流。由于由开态电流导致的n阱区域202的电位上升，由p型重掺杂杂质区域502、n阱区域202和p型硅衬底101形成的垂直寄生PNP晶体管被开启。这导致p阱区域201的电位降并且发生所谓的闩锁现象。
然而，为了确保用于高压电路部分的足够的闩锁电阻，需要增加阱的深度以抑制寄生双极效应(parasitic bipolar action)，并且，为了减少在NMOS晶体管和PMOS晶体管之间的漏电流以及为了确保高耐压特性(withstandcharacteristics)，有必要使沟槽隔离部分的宽度加大。因此，存在一个问题，当低压电路部分使用与高压电路部分的沟槽隔离结构相同的沟槽隔离结构时，需要更高的集成度的在低压部分中的器件集成度降低。
作为对其改进的措施，提出了一种使得高压电路部分的阱的深度大于低压电路部分的阱的深度的方法或者一种使得高压电路部分的沟槽隔离部分的宽度大于低压电路部分的沟槽隔离部分的宽度的方法(例如参见JP 2000-58673A)。
然而，如上所述，在具有多电源电压的半导体器件中，其元件被沟槽隔离隔离，为了确保用于高压电路部分的足够的闩锁电阻，需要增加阱的深度以抑制寄生双极效应，并且，为了减少在NMOS晶体管和PMOS晶体管之间的漏电流以及确保对反型的高耐压特性，有必要使沟槽隔离部分的宽度加大。因此，存在一个问题，当低压电路部分使用与高压电路部分的沟槽隔离结构相同的沟槽隔离结构时，相对于高度集成的需要低压部分中器件集成度降低。
虽然已经提出了一种改进，其中使高压电路部分的阱的深度大于低压电路部分的阱的深度或者使高压电路部分的沟槽隔离部分的宽度大于低压电路部分的沟槽隔离部分的宽度，但是存在制造步骤数量的增加以及沟槽隔离部分的宽度增加导致成本提高的问题。
发明内容
 为了解决上述问题，根据本发明，一种半导体器件如下构造。
根据本发明，提供了一种半导体器件，包括：形成在半导体衬底上的高压电路部分和低压电路部分；沟槽隔离结构，其隔离高压电路部分中的元件和低压电路部分中的元件，该高压电路部分包括：至少一个阱区域；MOS晶体管；和用于电连接相应器件的互连；和防止反型层形成的电极，其被设置在靠近该至少一个阱区域的端部的该沟槽隔离区域之上并且在该互连之下的区域中，以防止由于互连电位而在该半导体衬底的表面上的反型层的寄生形成。
用于防止反型层的形成的电极的电位与定位在其下的半导体衬底的电位相同。
此外，由与半导体衬底相同的导电类型的重掺杂杂质区域形成的保护环区域被设置在用于防止反型层形成的电极之下并且与其电连接，使得半导体衬底的电位被稳定地固定，并且，当发生双极效应时，俘获载流子以防止闩锁。
由于该上述方法，可以提供一种半导体器件，其中制造步骤的数量不会增加，可以确保足够的器件隔离特性和闩锁电阻用于高压电路部分，并且虽然低压电路部分使用与高压电路部分相同的沟槽隔离结构，集成度较高。
附图说明
在附图中：
图1是示出根据本发明的半导体器件的高压电路部分的第一实施例的横截面示意图；
图2是示出根据本发明的半导体器件的高压电路部分的第二实施例的横截面示意图；以及
图3是示出常规半导体器件的高压电路部分的一部分的横截面示意图。
具体实施方式
(实施例1)
图1是示出根据本发明的半导体器件的高压电路部分的第一实施例的横截面示意图。
作为第一阱的p型轻掺杂杂质区域的p阱区域201和作为第二阱的n型轻掺杂杂质区域的n阱区域202并排形成在作为第一导电类型的半导体衬底的p型硅衬底101上。是n型MOS晶体管的源极区域和/或漏极区域的n型重掺杂杂质区域501例如形成在p阱区域201的表面，而是p型MOS晶体管的源极和/或漏极区域的p型重掺杂杂质区域502例如形成在n阱区域202的表面。用于器件隔离的沟槽隔离区域301形成在n型重掺杂杂质区域501和p型重掺杂杂质区域502之间。
用于防止n型反型层形成的电极701由多晶硅薄膜或者由与形成MOS晶体管的栅电极相同的薄膜的金属形成，其经过第一绝缘膜601形成在p阱区域201上用于器件隔离的沟槽隔离区域301之上，其中该第一绝缘膜601为沿着与n阱的接合面的氧化硅薄膜等。虽然并未示出，用于防止n型反型层形成的电极701连接到与p阱区域201相同的电位并且固定在例如接地电平。
用于防止p型反型层形成的电极702由多晶硅薄膜或者由与形成MOS晶体管的栅电极相同的薄膜的金属形成，其经过第一绝缘膜601形成在n阱区域202上用于器件隔离的沟槽隔离区域301之上，其中该第一绝缘膜601为沿着与p阱的接合面(junction surface)的氧化硅薄膜等。虽然并未示出，用于防止p型反型层形成的电极702连接到与n阱区域202相同的电位并且固定在例如电源电压。
用于电连接器件的由铝等形成的互连901经过第二绝缘膜801形成在用于防止n型反型层形成的电极701和用于防止p型反型层形成的电极702之上。
在此，例如当高达30V的电位被施加到互连901时，因为用于防止n型反型层形成的电极701布置在互连901和p阱区域201之间并且防止n型反型层形成的电极701的电位被固定到与p阱区域201相同的电位，没有n型反型层形成在p阱区域201的表面上。
例如当低至0V的电位被施加到互连901时，由于在互连901和固定到例如高达30V的电源电压的n阱区域202的表面之间的电位差例如大，p型反型层将有可能形成在n阱区域202的表面上。然而根据本发明，因为用于防止p型反型层形成的电极702布置在互连901和n阱区域202之间并且用于防止p型反型层形成的电极702的电位被固定到与n阱区域202相同的电位，即使当与n阱区域202相比，相对较低的电位被施加到互连901时，没有p型反型层形成在n阱区域202的表面上。
如上所述，根据本发明，可以有效地防止反型层的形成，并且可以预先防止可能的闩锁发生。
第一绝缘膜601存在于图1所示的实施例中，但是第一绝缘膜601并不是必须的。
此外，关于半导体衬底和阱区域的组合，在图1所示的实施例中，p型硅衬底是第一导电类型的半导体衬底，p阱是第一阱，且n阱是第二阱。然而，在n型硅衬底是第一导电类型的半导体衬底的情况下，n阱是第一阱，且p阱是第二阱，其极性可以与图1中所示的实施例的极性相反。
当半导体器件被构造为只具有一种导电类型的阱区域，例如，当p型硅衬底是第一导电类型的半导体衬底且n阱是第二阱时，通过将p型硅衬底作为图1所示的实施例的p阱区域201，可以产生相似的效果。以相同的方式，当n型硅衬底是第一导体类型的半导体衬底并且p阱是第二阱的情况下，其是相反的组合并且类似于n型硅衬底是第一导体类型的半导体衬底，n阱是第一阱，并且p阱是第二阱的的情况，它们的极性可以是相反的。
应当注意的是在根据本发明的半导体器件的低压电路部分(未示出)低工作电压使得发生寄生双极效应和闩锁的可能性较低。不需要上文描述的用于防止反型层形成的电极，因此允许更高的集成度。
(实施例2)
图2是示出根据本发明的半导体器件的高压电路部分的第二实施例的横截面示意图。
作为第一阱的p型轻掺杂杂质区域的p阱区域201和作为第二阱的n型轻掺杂杂质区域的n阱区域202并排形成在作为第一导电类型的半导体衬底的p型硅衬底101上。是n型MOS晶体管的源极区域和/或漏极区域的n型重掺杂杂质区域501例如形成在p阱区域201的表面上，而是p型MOS晶体管的源极区域和/或漏极区域的p型重掺杂杂质区域502例如形成在n阱区域202的表面上。用于元件隔离的沟槽隔离区域301形成在n型重掺杂杂质区域501和p型重掺杂杂质区域502之间。
该实施例与图1所示的实施例的区别在于：重掺杂杂质区域的p型保护环区域421与p阱区域201的导电类型相同，其形成在p阱区域201的表面上且位于电极701之下，电极701用于防止n型反型层形成并且经过第一绝缘薄膜601形成，并且该p型保护环区域421通过接触区域411电连接到用于防止n型反型层形成的电极701，该接触区域411用于稳定地固定p阱区域201的电位并且当双极效应发生时用于捕获载流子以防止闩锁；并且在于，重掺杂杂质区域的n型保护环区域422与n阱区域202的导电类型相同，其形成在n阱区域202的表面上且位于电极702之下，电极702用于防止p型反型层形成并且经过第一绝缘薄膜601形成，并且n型保护环区域422通过接触区域411电连接到用于防止p型反型层形成的电极702，接触区域411用于稳定地固定n阱区域202的电位并且当双极效应发生时用于捕获载流子以防止闩锁。
用于电连接器件的互连901由铝等形成，其经过第二绝缘膜801形成在用于防止n型反型层形成的电极701和用于防止p型反型层形成的电极702之上。
在此，例如当高达30V的电位被施加到互连901时，因为用于防止n型反型层形成的电极701布置在互连901和p阱区域201之间而没有n型反型层形成在p阱区域201的表面上，并且因为用于防止n型反型层形成的电极701电连接到具有与p阱区域201相同的导电类型的重掺杂杂质区域的p型保护环区域421，该p型保护环区域421用于稳定地固定布置在其下的p阱区域201的电位，并且用于当双极效应发生时俘获载流子以防止闩锁，用于防止n型反型层形成的电极701的电位被固定到与p阱区域201相同的电位。
例如当低至0V的电位被施加到互连901时，例如由于在互连901和固定到高达30V的电源电压的n阱区域202的表面之间的电位差较大，p型反型层将有可能形成在n阱区域202的表面上。然而根据本发明，没有p型反型层形成在n阱区域202的表面上，因为用于防止p型反型层形成的电极702布置在互连901和n阱区域202之间并且因为用于防止p型反型层形成的电极702电连接到重掺杂杂质区域的n型保护环区域422，该n型保护环区域422与n阱区域202具有相同的导电类型，用于稳定地固定布置在其下的n阱区域202的电位并且用于在双极效应发生时俘获载流子以防止闩锁，用于防止反型层形成的p型电极702的电位被固定到与n阱区域202相同的电位。
在图2中所示的实施例中，因为除图1所示的实施例之外，p型保护环区域421和n型保护环区域422作为保护环用于稳定地固定p阱区域201和n阱区域202的电位并且用于在双极效应发生时俘获载流子以防止闩锁，相对于图1所示的实施例可以进一步改善闩锁电阻。此外，由于p型保护环区域421和n型保护环区域422分别布置在用于防止p型反型层形成的电极701之下和用于防止n型反型层形成的电极702之下，无需附加的区域并且不会发生成本的提高。
应当注意的是，关于半导体衬底和阱区域的组合，类似于图1所示的实施例，几种组合都是可能的，此处省略对其的描述。
关于其它部件，相似的数字用于表示在图1中所示的相同或者相似的部件，在此省略对其的描述。
如上所述，根据本发明，可以获得一种半导体器件，其中制造步骤的数量没有增加，可以确保足够的器件隔离特性和闩锁电阻用于高压电路部分，并且虽然低压电路部分使用的沟槽隔离结构与高压电路部分的沟槽隔离结构相同，但集成规模较大。

Claims (8)

1、一种半导体器件，包括：
半导体衬底；
布置在该半导体衬底上的高压电路部分和低压电路部分；
沟槽隔离结构，其通过沟槽隔离区域隔离在该高压电路部分和在该低压电路部分中的元件，
该高压电路部分包括：
阱区域；
MOS晶体管；和
用于电连接各元件的互连；和
用于防止反型层形成的电极，其提供设置在靠近该阱区域的端部的该沟槽隔离区域之上并且位于该互连之下的区域中，用于防止由于该互连的电位而在该半导体衬底的表面上反型层的寄生形成。
2、如权利要求1所述的半导体器件，
其中该高压电路部分进一步包括：
第一导电类型的半导体衬底；
该第一导电类型的第一阱；和
第二导电类型的第二阱，并且
其中该用于防止反型层形成的电极形成在该第一阱端部的区域和该第二阱端部的区域的每一区域中，位于该第一阱和该第二阱之间的接合处，位于该沟槽隔离区域之上和该互连之下。
3、如权利要求2所述的半导体器件，
其中形成在第一阱之上的用于防止反型层形成的电极的电位与该第一阱的电位相同，并且
其中形成在第二阱之上的用于防止反型层形成的电极的电位与该第二阱的电位相同。
4、如权利要求2所述的半导体器件，进一步包括：
第一保护环区域，由与该第一阱相同的导电类型的重掺杂杂质区域形成，其被设置在该第一阱之上形成的用于防止反型层形成的电极之下且与在该第一阱之上形成的用于防止反型层形成的电极电连接，用于稳定地固定该第一阱的电位，并且当发生双极效应时俘获载流子以防止闩锁；和
第二保护环区域，其由与该第二阱相同的导电类型的重掺杂杂质区域形成，其被设置在该第二阱之上形成的用于防止反型层形成的电极之下且与在该第二阱之上形成的用于防止反型层形成的电极电连接，用于稳定地固定该第二阱的电位，并且当发生双极效应时俘获载流子以防止闩锁。
5、如权利要求1所述的半导体器件，
其中该高压电路部分包括：
第一导电类型的半导体衬底；和
第二导电类型的第二阱，并且
其中用于防止反型层形成的电极形成在该第一导电类型的半导体衬底端部的区域和该第二阱端部的区域的每一区域中，位于该第一导电类型的半导体衬底和该第二阱之间的接合处的附近，位于该沟槽隔离区域之上和该互连之下。
6、如权利要求5所述的半导体器件，
其中形成在第一导电类型的该半导体衬底之上的用于防止反型层形成的电极的电位与该第一导电类型的半导体衬底的电位相同，并且
其中形成在第二阱之上的用于防止反型层形成的电极的电位与该第二阱的电位相同。
7、如权利要求5所述的半导体器件，进一步包括：
第一保护环区域，其由与第一导电类型的该半导体衬底相同的导电类型的重掺杂杂质区域形成，其被设置在形成在第一导电类型的半导体衬底之上的用于防止反型层形成的电极之下且与形成在第一导电类型的半导体衬底之上的用于防止反型层形成的电极电连接，用于稳定地固定第一导电类型的半导体衬底的电位，并且当发生双极效应时俘获载流子以防止闩锁；和
第二保护环区域，其由与该第二阱相同的导电类型的重掺杂杂质区域形成，其被设置在形成在该第二阱之上的用于防止反型层形成的电极之下且与形成在该第二阱之上的用于防止反型层形成的电极电连接，用于稳定地固定该第二阱的电位，并且当发生双极效应时俘获载流子以防止闩锁。
8、如权利要求1所述的半导体器件，
其中用于防止反型层形成的电极由与形成在高压电路部分中形成的MOS晶体管的栅电极的薄膜相同的薄膜形成。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023180831A1 (en) * 2022-03-24 2023-09-28 International Business Machines Corporation Size-efficient mitigation of latchup and latchup propagation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5546191B2 (ja) * 2009-09-25 2014-07-09 セイコーインスツル株式会社 半導体装置
US8492866B1 (en) * 2012-01-09 2013-07-23 International Business Machines Corporation Isolated Zener diode

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654958A (en) * 1985-02-11 1987-04-07 Intel Corporation Process for forming isolated silicon regions and field-effect devices on a silicon substrate
JPH0770685B2 (ja) * 1985-04-25 1995-07-31 日本電信電話株式会社 相補形ｍｉｓ半導体集積回路
JPH02172253A (ja) * 1988-12-24 1990-07-03 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0492449A (ja) * 1990-08-07 1992-03-25 Seiko Epson Corp 半導体装置
KR0149256B1 (ko) * 1995-08-25 1998-10-01 김주용 씨모스 트랜지스터 제조방법
JP2000058673A (ja) 1998-08-14 2000-02-25 Nec Corp トレンチ分離構造を有する半導体装置
JP3414656B2 (ja) * 1998-11-16 2003-06-09 シャープ株式会社 半導体装置及びその製造方法
US6232165B1 (en) * 1998-12-09 2001-05-15 Winbond Electronics Corporation Buried guard rings and method for forming the same
JP4577948B2 (ja) * 2000-06-20 2010-11-10 Ｏｋｉセミコンダクタ株式会社 オフセットゲート型電界効果トランジスタ
GB2367945B (en) * 2000-08-16 2004-10-20 Secr Defence Photodetector circuit
JP3531808B2 (ja) * 2000-10-31 2004-05-31 シャープ株式会社 保護回路および半導体装置
JP4895430B2 (ja) * 2001-03-22 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP4898024B2 (ja) * 2001-06-21 2012-03-14 セイコーインスツル株式会社 半導体装置の製造方法
CN1564318A (zh) * 2004-03-26 2005-01-12 清华大学 0.35μm LDMOS高压功率显示驱动器件的设计方法
US7091079B2 (en) * 2004-11-11 2006-08-15 United Microelectronics Corp. Method of forming devices having three different operation voltages
JP4845410B2 (ja) * 2005-03-31 2011-12-28 株式会社リコー 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023180831A1 (en) * 2022-03-24 2023-09-28 International Business Machines Corporation Size-efficient mitigation of latchup and latchup propagation

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